Wafer exposure method and device, storage medium and electronic equipment

Abstract

The invention discloses a wafer exposure method and device, a storage medium and electronic equipment. The method comprises the following steps: providing a wafer; forming a photoresist on the wafer; dividing the photoresist into a valid region and an invalid region based on the wafer and the exposure region information; exposure is carried out according to the position information of the effective area, and in the step of exposure according to the position information of the effective area, the photoresist in the effective area is exposed, and the photoresist in the invalid area is not exposed. According to the wafer and the exposure area information, the photoresist on the wafer is divided into the effective area and the invalid area, and exposure is performed according to the position information of the effective area, so that accurate exposure of the effective area can be realized; by exposing the photoresist in the effective region and not exposing the photoresist in the ineffective region, the wafer coverage area of the photoresist in the ineffective region can be ensured, the connection strength of the photoresist in the ineffective region and the wafer is improved, the photoresist stripping defect in the ineffective region is reduced, and the manufacturing yield is improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductors, and in particular to a wafer exposure method, device, storage medium and electronic equipment. Background Art

[0002] With the advancement of semiconductor technology, the density of integrated circuits is increasing, while feature sizes are shrinking. Photolithography and exposure techniques play a crucial role in semiconductor manufacturing. During the semiconductor device manufacturing process, the patterning of thin film layers and ion implantation into semiconductors are all defined through photolithography. The specific steps include spin-coating photoresist onto the wafer surface to form a photoresist layer, exposing and developing the photoresist layer to transfer the pattern on the mask to the photoresist layer on the wafer surface.

[0003] However, the current photoresist on the edge of the wafer cannot obtain a good exposure pattern after exposure, and will cause the photoresist on the edge of the wafer to peel off and leave many particles. These particles fall onto the surface or back of the wafer, causing damage to the wafer and affecting the wafer yield. Summary of the Invention

[0004] The technical problem solved by the present invention is how to improve the wafer yield.

[0005] To solve the above technical problems, an embodiment of the present invention provides a wafer exposure method, comprising: providing a wafer; forming a photoresist on the wafer; dividing the photoresist into a valid area and an invalid area based on the wafer and exposure area information; exposing according to the position information of the valid area, and in the step of exposing according to the position information of the valid area, exposing the photoresist in the valid area and not exposing the photoresist in the invalid area.

[0006] Optionally, the step of dividing the wafer into effective areas and invalid areas includes: constructing a division grid based on exposure area information, the division grid including cells arranged in an array; dividing the photoresist according to the division grid to obtain effective areas and invalid areas.

[0007] Optionally, the step of dividing the photoresist includes: aligning the center point of the dividing grid with the center point of the wafer, the line connecting the center point of the dividing grid and the center point of the wafer being the projection ray; based on the projection ray, projecting the wafer and the dividing grid to overlap.

[0008] Optionally, the wafer exposure method also includes: performing simulated exposure based on the effective area to obtain simulated exposure parameters of the effective area; in the step of exposing according to the position information of the effective area, exposing the position information of the effective area at least according to the simulated exposure parameters of the effective area.

[0009] Optionally, the step of performing simulated exposure based on the effective area includes: obtaining simulated exposure parameters of the invalid area according to the simulated exposure parameters of the effective area; the step of exposing the position information of the effective area includes: exposing the position information of the effective area according to the simulated exposure parameters of the effective area and the simulated exposure parameters of the invalid area.

[0010] Optionally, the wafer exposure method further includes: after exposing according to the position information of the effective area, washing the edge of the photoresist.

[0011] Optionally, the simulated exposure parameters include: exposure area, exposure dose, exposure time, exposure intensity and exposure wavelength.

[0012] Correspondingly, the present invention also provides a wafer exposure device, including: a division module, which divides the photoresist on the wafer into a valid area and an invalid area based on the wafer and exposure area information; a control module, wherein the control unit performs exposure according to the position information of the valid area, and in the step of exposing according to the position information of the valid area, the photoresist in the valid area is exposed and the photoresist in the invalid area is not exposed.

[0013] Accordingly, the present invention also provides a storage medium on which computer instructions are stored, and the computer instructions execute the steps of the above method when executed.

[0014] Correspondingly, the present invention also provides an electronic device, comprising a memory and a processor, wherein the memory stores computer instructions that can be executed on the processor, and the processor executes the steps of the above method when executing the computer instructions.

[0015] Compared with the prior art, the technical solution of the embodiment of the present invention has the following beneficial effects:

[0016] By adopting the wafer exposure method in the embodiment of the present invention, the photoresist on the wafer is divided into an effective area and an invalid area according to the wafer and exposure area information, and exposure is performed according to the position information of the effective area, so that precise exposure of the effective area can be achieved; in addition, the present invention avoids the patterning of the photoresist in the invalid area by exposing the photoresist in the effective area and not exposing the photoresist in the invalid area, thereby ensuring the coverage area of the wafer by the photoresist in the invalid area, ensuring the contact area between the photoresist in the invalid area and the wafer, improving the connection strength between the photoresist in the invalid area and the wafer, reducing the occurrence of photoresist peeling defects in the invalid area, thereby improving the manufacturing yield, and by not exposing the photoresist in the invalid area, reducing the generation of peeling defect sources, which can effectively reduce the control requirements of the edge washing process, expand the process window of the edge washing process, and thus reduce the process cost and improve the process efficiency.

[0017] Furthermore, the technical solution of the present invention constructs cells arranged in an array according to the exposure area information, and divides the photoresist according to the cells arranged in an array to obtain effective areas and invalid areas, thereby achieving accurate division of the wafer and reducing the occurrence of photoresist stripping defects in the invalid areas, thereby improving the manufacturing yield. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 1 is a schematic flow chart of a wafer exposure method according to an embodiment of the present invention;

[0019] Figure 2 1 is a schematic structural diagram of a wafer in a wafer exposure method according to an embodiment of the present invention;

[0020] Figure 3 1 is a schematic diagram of a process for dividing a wafer into an effective area and an ineffective area in an embodiment of the present invention;

[0021] Figure 4 1 is a schematic diagram of a process for dividing the photoresist in an embodiment of the present invention;

[0022] Figure 5 This is a schematic diagram of the structure of wafer division in one embodiment of the present invention;

[0023] Figure 6 is a schematic structural diagram of wafer division in another embodiment of the present invention;

[0024] Figure 7 1 is a schematic diagram of a process of simulated exposure in an embodiment of the present invention;

[0025] Figure 8 is a trend diagram of the number of peeling defects in the wafer according to the embodiment of the present invention,

[0026] Figure 9It is a structural schematic diagram of a wafer exposure device in an embodiment of the present invention. DETAILED DESCRIPTION

[0027] It should be noted that the terms “surface” and “on” in this specification are used to describe relative positional relationships in space and are not limited to whether there is direct contact.

[0028] The current wafer exposure method comprises the following steps: providing a wafer; forming a photoresist on the wafer; and exposing the photoresist on the wafer.

[0029] In some embodiments, the wafer includes a central area and an edge area, and the simulated exposure of the simulated layout includes: simulating calculation or copying exposure information of the central area and exposing the edge area.

[0030] Since the edge area is incomplete, after the edge area is exposed, the photoresist coverage of the edge area is reduced, which easily generates a peeling defect source. After the subsequent etching process, the peeling defect source is easy to fall into the interior of the wafer, thereby affecting the yield.

[0031] At present, in order to solve the above problems, a side cleaning process is usually adopted to remove the photoresist on the edge area to prevent the incomplete exposure pattern on the edge area from forming a defect peeling source after the subsequent etching process and falling into the interior of the wafer, affecting the yield. However, if the side cleaning process is not thorough, the risk of forming a defect peeling source will still be difficult to completely avoid, affecting the yield; and if the parameters of the side cleaning process are precisely controlled to completely remove the photoresist on the edge area, it will lead to an increase in process cost and a decrease in process efficiency.

[0032] To solve the above technical problems, the present invention provides a semiconductor structure and a method for forming the same. According to the wafer and exposure area information, the photoresist on the wafer is divided into an effective area and an invalid area, and exposure is performed according to the position information of the effective area, so as to achieve precise exposure of the effective area. In addition, the present invention avoids patterning of the photoresist in the invalid area by exposing the photoresist in the effective area and not exposing the photoresist in the invalid area, thereby ensuring the coverage area of the wafer by the photoresist in the invalid area, ensuring the contact area between the photoresist in the invalid area and the wafer, improving the connection strength between the photoresist in the invalid area and the wafer, reducing the occurrence of photoresist peeling defects in the invalid area, thereby improving the manufacturing yield, and by not exposing the photoresist in the invalid area, reducing the generation of peeling defect sources, which can effectively reduce the control requirements of the edge washing process, expand the process window of the edge washing process, and thus reduce the process cost and improve the process efficiency.

[0033] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0034] Figure 1 1 is a flow chart of the steps of the wafer exposure method according to an embodiment of the present invention, including:

[0035] Step S11: providing a wafer;

[0036] Step S12: forming a photoresist on the wafer;

[0037] Step S13: dividing the photoresist into a valid area and an invalid area based on the wafer and exposure area information;

[0038] Step S14: performing exposure according to the position information of the effective area. In the step of performing exposure according to the position information of the effective area, the photoresist in the effective area is exposed and the photoresist in the ineffective area is not exposed.

[0039] By adopting the above-mentioned wafer exposure method, the photoresist on the wafer is divided into an effective area and an invalid area according to the wafer and exposure area information, and exposure is performed according to the position information of the effective area, so that precise exposure of the effective area can be achieved; in addition, the present invention avoids the patterning of the photoresist in the invalid area by exposing the photoresist in the effective area and not exposing the photoresist in the invalid area, thereby ensuring the coverage area of the wafer by the photoresist in the invalid area, ensuring the contact area between the photoresist in the invalid area and the wafer, improving the connection strength between the photoresist in the invalid area and the wafer, reducing the occurrence of photoresist peeling defects in the invalid area, thereby improving the manufacturing yield, and by not exposing the photoresist in the invalid area, reducing the generation of peeling defect sources, which can effectively reduce the control requirements of the edge washing process, expand the process window of the edge washing process, and thus reduce the process cost and improve the process efficiency.

[0040] The following describes each step of the wafer exposure method in detail.

[0041] In step S11 , the wafer 200 is a silicon wafer 200 , and the diameter of the wafer 200 is 150 mm, 200 mm, or 300 mm.

[0042] In step S12, Figure 1 Based on reference Figure 2The steps of forming the photoresist 201 include: fixing the wafer 200 on a rotating table, dripping the photoresist 201 on the center through a nozzle (the amount is about 1ml~5ml, depending on the size of the wafer 200); rotating at a low speed (500 rpm~1000 rpm) to spread the photoresist 201 over the entire surface of the wafer 200; rotating at a high speed (1000 rpm~6000 rpm, for 30 seconds~60 seconds) to form a uniform film using centrifugal force and shake off excess glue; using a solvent or a mechanical scraper to remove the photoresist 201 residue on the edge of the wafer 200 to avoid contamination in subsequent processes.

[0043] In some embodiments of the present invention, before the step of forming the photoresist 201, the surface of the wafer 200 is also pretreated, specifically including: cleaning the surface of the wafer 200 to remove particles, organic matter and metal pollution on the surface of the wafer 200; baking the surface of the wafer 200 at 150°C~200°C to remove surface moisture and enhance the adhesion of the photoresist 201; and coating hexamethyldisilazane on the surface of the wafer 200 to improve hydrophobicity and prevent the photoresist 201 from falling off.

[0044] In step S13, please refer to Figure 3 as well as Figure 5 The step of dividing the wafer 200 into an effective area 301 and an ineffective area 302 includes:

[0045] Step S131: constructing a division grid based on the exposure area information, wherein the division grid includes cells arranged in an array;

[0046] Step S132 : dividing the photoresist 201 according to the division grid to obtain an effective area 301 and an ineffective area 302 .

[0047] In some embodiments of the present invention, the exposure area information in step S131 includes the shape and size of the exposure area.

[0048] For example, the shape of the exposure area is a rectangle, the size of the exposure area is the length information of each side of the rectangle, the shape of the exposure area is the same as the shape and size of the cell, and specifically, the size of the rectangular cell is 20 mm×20 mm.

[0049] In other embodiments, the size of the exposure area is 26 mm×33 mm or 22 mm×22 mm.

[0050] In some embodiments of the present invention, when the size of the wafer 200 is 8 inches (200 mm) and the size of the exposure area is 20 mm×20 mm, a 10×10 exposure array is required to expose the photoresist 201 on the surface of the wafer 200 100 times.

[0051] The size of the grid array is the same as that of the exposure array.

[0052] In other embodiments of the present invention, the shape of the exposure area is a triangle, the size of the exposure area is the length information of each side of the triangle, and the shape and size of the exposure area are the same as those of the unit cell.

[0053] In some embodiments of the present invention, constructing a division grid in step S131 includes: setting a plurality of first division lines and a plurality of division scanning lines according to the size of the wafer 200, the first division lines and the second division lines being perpendicular to each other, and the plurality of first division lines and the plurality of second division lines being distributed in a grid shape; setting a plurality of first interval data of the first division lines and a plurality of second interval data of the second division lines; and constructing a division grid according to the first interval data and the second interval data.

[0054] The first spacing data is characterized by the distance between two adjacent first dividing lines; the second spacing data is characterized by the distance between two adjacent second dividing lines, and the first spacing data and the second spacing data respectively correspond to the size of the exposure area.

[0055] In the above scheme, cells arranged in an array are constructed according to the exposure area information, and the photoresist 201 is divided according to the cells arranged in an array to obtain effective areas 301 and invalid areas 302, thereby achieving accurate division of the wafer 200 and reducing the occurrence of photoresist stripping defects in the invalid areas, thereby improving the manufacturing yield.

[0056] Please refer to Figure 4 In step S132, the step of dividing the photoresist 201 includes:

[0057] S1321: Aligning the center point of the divided grid with the center point of the wafer 200, wherein the line connecting the center point of the divided grid and the center point of the wafer 200 is a projection ray;

[0058] S1322: Based on the projection ray, the wafer 200 is projected and overlapped with the divided grid.

[0059] In some embodiments of the present invention, please refer to Figure 5 The effective area 301 in step S132 is characterized as follows: after the wafer 200 and the divided grid projection coincide with each other, when all grid points in the cell are located within the wafer 200, the projection area on the wafer 200 corresponding to the cell is the effective area 301, and the rest is the invalid area 302 (red frame area).

[0060] In some embodiments of the present invention, please refer to Figure 6 The effective area 401 in step S132 is characterized as follows: after the wafer 200 overlaps with the divided grid projection, when the area of the photoresist 201 on the wafer 200 corresponding to the cell is greater than the preset area, the projection area on the wafer 200 corresponding to the cell is the effective area 401; when the area of the photoresist 201 on the wafer 200 corresponding to the cell is less than the preset area, the projection area on the wafer 200 corresponding to the cell is the invalid area 402 (red frame area).

[0061] In a specific embodiment, the preset area is half of the area of the cell.

[0062] In the above scheme, when the area of the photoresist 201 on the wafer 200 corresponding to the cell is more than half of the area of the cell, the cell is determined to be a valid area 401, and subsequent exposure can be performed on the position of the valid area 401; when the area of the photoresist 201 on the wafer 200 corresponding to the cell is less than half of the area of the cell, the cell is determined to be an invalid area 402. By judging the size of the area of the photoresist 201 on the wafer 200 corresponding to the cell, the valid area 401 and the cancelled area are determined, thereby improving the utilization rate of the wafer 200.

[0063] Please refer to Figure 7 In some embodiments of the present invention, the wafer exposure method further includes:

[0064] Step S15: performing simulated exposure based on the effective area to obtain simulated exposure parameters of the effective area;

[0065] Step S16: in the step of performing exposure according to the position information of the effective area, the position information of the effective area is exposed at least according to the simulated exposure parameters of the effective area.

[0066] In some embodiments of the present invention, performing simulated exposure based on the effective area in step S15 includes: obtaining simulated exposure parameters of the ineffective area according to simulated exposure parameters of the effective area;

[0067] The step of exposing the position information of the effective area includes: exposing the position information of the effective area according to the simulated exposure parameters of the effective area and the simulated exposure parameters of the invalid area.

[0068] The position information of the effective area is represented by the center position of the cell corresponding to the effective area.

[0069] In some embodiments of the present invention, the step of obtaining the simulated exposure parameters of the invalid area includes: simulating and calculating or copying the simulated exposure parameters on the valid area to perform simulated exposure on the invalid area.

[0070] The simulated exposure parameters include: exposure area, exposure dose, exposure time, exposure intensity and exposure wavelength.

[0071] Specifically, in some embodiments of the present invention, the step of exposing the position information of the effective area includes: loading the mask containing the target pattern into the photolithography machine and calibrating it; matching the alignment mark on the wafer with the mask to ensure the accuracy of the exposure position; according to the position of the effective area, moving the workbench of the photolithography machine in a step-by-step manner, and each time the exposure of an exposure area is completed, the workbench moves to the next exposure area position, and repeats the exposure until the entire wafer is covered.

[0072] In some embodiments of the present invention, the wafer exposure method further includes: after exposing according to the position information of the effective area, edge washing the photoresist.

[0073] The photoresist edge washing range is 1 mm to 3 mm from the edge of the wafer.

[0074] The step of cleaning the edge of the photoresist includes: using a cleaning solvent (such as acetone) to dissolve the photoresist on the edge of the wafer. The specific cleaning steps are: rotating the wafer (rotation speed is 500rpm~1000rpm); using a nozzle to spray the cleaning solvent at 1 mm to 3 mm from the edge of the wafer; after the solvent dissolves the photoresist, it is thrown out by centrifugal force; and drying the cleaned wafer surface.

[0075] Please refer to Figure 8 , Figure 8 This is a trend chart of the number of wafer spalling defects, with time plotted on the horizontal axis and the number of spalling defects plotted on the vertical axis. The data represents the number of wafer spalling defects at different times. Before the time indicated by the red box, exposure was performed using a conventional wafer exposure method; after the time indicated by the red box, exposure was performed using the exposure method of the present invention.

[0076] Depend on Figure 8 It can be seen that before the time indicated by the red box, the traditional wafer exposure method was used, and the number of peeling defects in the wafer reached a maximum of 2110ea; after the time indicated by the red box, the wafer exposure method of the embodiment of the present invention was used, and the number of peeling defects in the wafer was kept within 100ea. It can be seen that the wafer exposure method of the embodiment of the present invention can reduce the number of peeling defects, ensure the integrity of the wafer, and improve the wafer yield.

[0077] The peeling defect is characterized by the partial peeling of the photoresist on the wafer surface due to insufficient adhesion or stress problems. After the subsequent etching process, the defective peeling source falls into the interior of the wafer, which affects the yield.

[0078] In summary, by adopting the above-mentioned wafer exposure method, the photoresist on the wafer is divided into a valid area and an invalid area according to the wafer and exposure area information, and exposure is performed according to the position information of the valid area, so as to achieve precise exposure of the valid area; in addition, the present invention avoids the situation where an incomplete exposure image and photoresist peeling defects are generated due to exposure of the photoresist in the invalid area by exposing the photoresist in the valid area and not exposing the photoresist in the invalid area, thereby ensuring the integrity of the wafer and improving the wafer yield. In addition, in the present invention, by not exposing the photoresist in the invalid area, the generation of peeling defect sources is avoided, and there is no need to accurately control the parameters of the wafer edge washing process subsequently, thereby reducing the process cost and improving the process efficiency.

[0079] Please refer to Figure 9 The present invention further provides a wafer exposure device 500, comprising:

[0080] A division module 501 divides the photoresist on the wafer into a valid area and an invalid area based on the wafer and exposure area information;

[0081] The control module 502 is configured to perform exposure according to the position information of the effective area. In the step of performing exposure according to the position information of the effective area, the photoresist in the effective area is exposed and the photoresist in the ineffective area is not exposed.

[0082] In some embodiments of the present invention, the partitioning module further includes:

[0083] A construction unit, wherein the construction unit is adapted to construct a division grid based on the exposure area information, wherein the division grid includes cells arranged in an array;

[0084] An acquisition unit is configured to divide the photoresist according to the division grid to obtain a valid area and an invalid area.

[0085] Wherein, the acquisition unit further includes:

[0086] an alignment unit, adapted to align a center point of the divided grid with a center point of the wafer, wherein a line connecting the center point of the divided grid and the center point of the wafer is a projection ray;

[0087] A projection unit is configured to project and overlap the wafer with the divided grid based on the projection ray.

[0088] In some embodiments of the present invention, the wafer exposure device uses the only exposure method of the present invention for exposure.

[0089] Accordingly, the present invention also provides a storage medium on which computer instructions are stored, and the steps of the above method are executed when the computer instructions are executed.

[0090] Correspondingly, the present invention also provides an electronic device, comprising a memory and a processor, wherein the memory stores computer instructions that can be run on the processor, and the processor executes the steps of the above method when running the computer instructions.

[0091] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be based on the scope defined by the claims.

Claims

1. A wafer exposure method, characterized in that: include: Provide wafers; forming a photoresist on the wafer; Based on the wafer and exposure area information, dividing the photoresist into a valid area and an invalid area; Exposure is performed according to the position information of the effective area. In the step of exposing according to the position information of the effective area, the photoresist in the effective area is exposed and the photoresist in the ineffective area is not exposed.

2. The wafer exposure method according to claim 1, wherein: The step of dividing the wafer into an effective area and an ineffective area comprises: Constructing a division grid based on the exposure area information, wherein the division grid includes cells arranged in an array; The photoresist is divided according to the division grid to obtain effective areas and ineffective areas.

3. The wafer exposure method according to claim 2, wherein: The step of dividing the photoresist includes: aligning the center point of the dividing grid with the center point of the wafer, wherein the line connecting the center point of the dividing grid and the center point of the wafer is a projection ray; Based on the projection ray, the wafer is projected and overlapped with the divided grid.

4. The wafer exposure method according to claim 1, wherein: Also includes: Performing simulated exposure based on the effective area to obtain simulated exposure parameters of the effective area; In the step of performing exposure according to the position information of the effective area, the position information of the effective area is exposed at least according to a simulated exposure parameter of the effective area.

5. The wafer exposure method according to claim 4, wherein: The step of performing simulated exposure based on the effective area includes: obtaining simulated exposure parameters of the ineffective area according to the simulated exposure parameters of the effective area; The step of exposing the position information of the effective area includes: exposing the position information of the effective area according to the simulated exposure parameters of the effective area and the simulated exposure parameters of the invalid area.

6. The wafer exposure method according to claim 1, wherein: Also includes: After exposure according to the position information of the effective area, the photoresist is edge-washed.

7. The wafer exposure method according to claim 4, wherein: The simulated exposure parameters include: exposure area, exposure dose, exposure time, exposure intensity and exposure wavelength.

8. A wafer exposure device, characterized in that: include: A division module, based on the wafer and exposure area information, divides the photoresist on the wafer into a valid area and an invalid area; The control module is configured to perform exposure according to the position information of the effective area. In the step of performing exposure according to the position information of the effective area, the photoresist in the effective area is exposed and the photoresist in the ineffective area is not exposed.

9. A storage medium having computer instructions stored thereon, characterized in that: When the computer instructions are executed, the steps of the method according to any one of claims 1 to 7 are executed.

10. An electronic device comprising a memory and a processor, wherein the memory stores computer instructions that can be executed on the processor, wherein: When the processor executes the computer instructions, the steps of the method according to any one of claims 1 to 7 are performed.

Images