Storage chip-oriented efficient data burning and error correction method and system

Abstract

The invention discloses an efficient data burning and error correction method and system oriented to a storage chip, and relates to the field of data burning and error correction. Collaborative optimization of performance and reliability of a storage system is achieved through a multi-level cache and a dynamic adjustment mechanism; through the hierarchical design of the first-level cache and the second-level cache, high-frequency access data is preferentially reserved in a low-delay storage medium, a time delay mapping model can predict performance under different capacity configurations, and blindness of traditional threshold setting is avoided; early signs of hardware degradation can be identified by combining dual judgment conditions of storage error times and time delay data; the cold and hot data migration threshold value is dynamically adjusted, and the storage load balance degree is improved; in addition, when cache adjustment fails, capacity expansion and shrinkage of the storage area are automatically triggered, and service continuity in an extreme scene is ensured.

Description

Technical Field

[0001] The present invention belongs to the field of data burning and error correction, and in particular relates to a high-efficiency data burning and error correction method and system for storage chips. Background Art

[0002] Memory chips, as an essential core component of modern electronic devices, play a crucial role in ensuring data integrity and reliability. However, in practical applications, memory chip programming and error correction management face numerous challenges: Low data programming efficiency: As memory chip capacity increases, traditional programming methods have increasingly exposed issues of slow processing speed and high resource consumption. Improving programming speed and reducing processing time are pressing technical challenges, especially in high-density memory chips. Inadequate error correction capability: Memory chips can experience data bit flips during use due to various factors (such as radiation, temperature fluctuations, and electromagnetic interference). Traditional error correction technologies struggle to provide sufficient error correction capabilities. This is especially true when errors occur frequently or are complex, making error correction efficiency and reliability crucial. Error propagation and complex management: In multi-level storage structures, error propagation can lead to the spread of data errors, increasing the complexity of error management and repair. Traditional methods often rely on relatively static error correction strategies that are unable to adapt flexibly to changing error patterns. Traditional burning systems have difficulty predicting latency changes under different capacity loads, and traditional static migration thresholds may lead to insufficient storage media utilization; in addition, traditional solutions are prone to avalanche effects caused by cache fullness. Summary of the Invention

[0003] In response to the problems in the related art, the present invention proposes a method and system for efficient data burning and error correction for a memory chip to overcome the above technical problems existing in the existing related art.

[0004] To solve the above technical problems, the present invention is achieved through the following technical solutions: The present invention is a method for efficiently burning data and correcting errors in a memory chip, comprising the following steps: S1. Build the first and second level caches for each storage area to be burned; S2, collect the historical capacity and historical latency data of each storage area to be burned and the first and second level caches in S1; S3. Build a delay mapping model corresponding to each storage area to be burned based on the historical capacity and historical delay data collected in S2; S4: Collect the current capacity data of each storage area to be programmed, the first and second level caches, and the number of storage errors of each storage area to be programmed; then input them into the delay mapping model constructed in S3 for mapping to obtain the current area delay data set; S5. Build a set of adjustment criteria for the current region based on the latency dataset and the number of storage errors collected in S4. Adjust the migration thresholds for hot, warm, and cold data. If the criteria are still met after the adjustments, execute S6. S6. First, adjust the current storage capacity data of the first and second level caches according to the current area adjustment judgment condition set; if the judgment condition is still met after the adjustment, then adjust the current storage capacity data of each storage area to be burned until no condition is met in the current area adjustment judgment condition set.

[0005] Preferably, the S1 comprises the following steps: S11, setting a memory chip to be programmed; dividing the data storage area of the memory chip to be programmed to obtain a set of storage areas to be programmed; the set of storage areas to be programmed includes a program storage area, a metadata storage area, a hot data storage area, a warm data storage area, and a cold data storage area; S12, constructing the first-level cache of the program storage area, metadata storage area, hot data storage area, and warm data storage area respectively to obtain a first-level cache set to be burned; then, based on the first-level cache set to be burned, constructing the second-level cache of the metadata storage area and the hot data storage area to obtain a second-level cache to be burned; Through hot / warm / cold data partition isolation and two-level cache collaboration, high-frequency access data is preferentially stored in the low-latency cache, reducing the number of direct accesses to the main memory and reducing the overall data access latency; the metadata separate cache design is reduced to further shorten the retrieval time of key control information; a classification standard is provided for subsequent dynamic data classification, thereby concentrating the wear of hot data areas with high write frequency and extending the overall service life of the chip; no cache is set up in the cold data area to reduce static energy consumption; a combination of large-capacity low-speed storage in the cold data area and high-speed cache in the hot data area is realized, which reduces the proportion of high-speed storage media used while meeting performance requirements, saving hardware costs and optimizing energy efficiency.

[0006] Preferably, said S2 comprises the following steps: S21, according to the storage area set to be burned, the first-level cache set to be burned, and the second-level cache to be burned, repeatedly collecting historical storage capacity data of each storage area to be burned, the first-level cache, and the second-level cache to be burned, to obtain a storage area to be burned historical capacity data set, a first-level cache to be burned historical capacity data set, and a second-level cache to be burned historical capacity data; S22, repeatedly obtaining the amount of code program data, metadata, hot data, warm data, and cold data in the historical data to be burned corresponding to the historical capacity data obtained in S21, to obtain a historical data volume set to be burned; and then collecting historical average time delay data of accessing each storage area to be burned in the storage area set to be burned corresponding to the historical data volume set to be burned, to obtain a regional time delay historical data set; By quantifying the capacity of storage media at all levels, precise space allocation for program, metadata, hot, warm, and cold data is achieved, avoiding inefficient occupation of high-speed storage media. Matching analysis of capacity data sets and data volume sets improves storage utilization. By comparing time delay data with thresholds, potential performance conflict areas can be identified before data is burned, allowing the system to make load balancing adjustments in advance and reducing fluctuations in storage access delays. Combined with delay threshold control, the risk of data loss can be greatly reduced. Based on the joint analysis of capacity and delay data, the power supply strategy for different storage areas can be dynamically adjusted, reducing the power consumption of inactive storage units.

[0007] Preferably, the step S3 includes the following steps: S31, constructing a program region delay mapping model, a meta region delay mapping model, a hot region delay mapping model, a warm region delay mapping model, and a cold region delay mapping model based on the historical capacity data set of the storage region to be burned, the historical capacity data set of the first-level cache to be burned, the historical capacity data set of the second-level cache to be burned, the historical data volume set to be burned, and the historical data set of regional time delay; By constructing the program area delay mapping model, the meta area delay mapping model, the hot area delay mapping model, the warm area delay mapping model and the cold area delay mapping model, it provides a basis for adjusting the cache capacity or area capacity by mapping the delay data of each area to the corresponding area according to each area, cache capacity and the amount of data to be burned.

[0008] Preferably, the program area delay mapping model, the meta area delay mapping model, the hot area delay mapping model, the warm area delay mapping model, and the cold area delay mapping model in S31 all adopt LSTM models; LSTM (Long Short-Term Memory) networks can effectively capture storage capacity fluctuations and the temporal dependencies of historical delay data, resolving the vanishing gradient problem of traditional RNNs. They also address the temporal dynamics of storage systems through a gating mechanism. Furthermore, LSTM is suitable for high-frequency delay prediction in program storage and hot data areas, where real-time performance is critical. LSTM's multi-step prediction capabilities can provide early warning of performance bottlenecks. Preferably, said S4 comprises the following steps: S41, according to the storage area set to be burned, the first-level cache set to be burned, and the second-level cache to be burned, collecting the current storage capacity data of each storage area to be burned, the first-level cache, and the second-level cache to be burned of the memory chip to be burned, and obtaining a current capacity data set of the storage area to be burned, a current capacity data set of the first-level cache to be burned, and current capacity data of the second-level cache to be burned; Then, the amount of code program data, metadata, hot data, warm data, and cold data in the current data to be programmed corresponding to the current storage capacity data of each storage area to be programmed, the first-level cache, and the second-level cache obtained in S41 is obtained to obtain a current data amount set to be programmed; S42, constructing standard rules for data migration in various areas of the memory chip to be programmed; S43, setting a data storage error count threshold value corresponding to each storage area to be programmed on the storage chip to be programmed, and obtaining a current data storage error count threshold value set; and according to the data migration standard rule, counting the data storage error count of each storage area to be programmed based on a current capacity data set of the storage area to be programmed, a current capacity data set of the first-level cache to be programmed, a current capacity data set of the second-level cache to be programmed, and a current data volume set to be programmed, to obtain a current storage error count set of the area; S44, setting a current delay threshold for each storage area to be programmed to obtain a current area delay threshold set; combining the data amounts of code program data, meta data, hot data, warm data, and cold data in the current data set to be programmed with a current capacity data set of the storage area to be programmed, a current capacity data set of the first-level cache to be programmed, and a current capacity data set of the second-level cache to be programmed, and inputting the combined data into a program area delay mapping model, a meta area delay mapping model, a hot area delay mapping model, a warm area delay mapping model, and a cold area delay mapping model for mapping, to obtain a current area delay data set; By dynamically monitoring the capacity status of storage areas, first-level cache, and second-level cache, combined with differentiated data classification, the risk of storage errors is effectively reduced. Furthermore, a real-time statistical mechanism based on error count thresholds provides early warning of potential storage failures. A tiered cache architecture reduces repeated I / O operations, providing data support for matching optimal storage capacity to different data types and significantly reducing access latency. Standard data migration rules support dynamic adjustment of storage policies to accommodate datasets of varying sizes and changing access patterns. Furthermore, data migration has a certain impact on both the number of data storage errors and latency, providing a decision-making basis for subsequent multi-level capacity datasets and error statistics mechanisms for flexible resource allocation.

[0009] Preferably, the S42 includes the following steps: S421: Set migration standard thresholds for hot, warm, and cold data respectively to obtain a hot access frequency threshold, a warm access frequency threshold, and a cold access frequency threshold; then set a hot migration frequency acquisition count threshold, a warm migration frequency acquisition count threshold, and a cold migration frequency acquisition count threshold; S422: Construct a data migration standard rule based on the migration frequency acquisition times threshold, hot access frequency threshold, warm access frequency threshold, and cold access frequency threshold; as follows: Except for program data and metadata, when the access frequency of the data in the memory chip to be burned is greater than or equal to the hot access frequency threshold and the number of times is greater than or equal to the hot migration frequency acquisition number threshold, the data is migrated to the hot data storage area; otherwise, no migration is performed; When the access frequency is continuously less than the hot access frequency threshold and the number of times greater than or equal to the warm access frequency threshold is greater than or equal to the warm migration frequency acquisition number threshold, the data is migrated to the warm data storage area; otherwise, no migration is performed; When the number of times the access frequency is continuously less than the cold access frequency threshold is greater than or equal to the cold migration frequency acquisition number threshold, the data is migrated to the cold data storage area; otherwise, no migration is performed; A continuous cycle compliance judgment strategy is adopted to effectively filter out the interference of transient access fluctuations on data migration and improve the stability of system operation; the migration frequency threshold mechanism avoids performance jitter caused by frequent data movement; the hot access frequency threshold ensures that only continuously high-frequency access data occupies high-speed storage media, improving the utilization rate of high-speed storage space; the cold data delay degradation strategy can accurately identify truly idle data through long-term low-frequency verification, improving the accuracy of the activation timing of low-power storage media; in addition, the isolated storage of metadata and program data prevents critical data from being affected by the migration strategy, shortening the system crash recovery time.

[0010] Preferably, the S5 comprises the following steps: S51. Set a current region adjustment determination condition set in conjunction with a current data storage error count threshold set and a current region latency threshold set; S52. Set a first maximum number of repetitions. If any of the determination conditions in the current region adjustment determination condition set are met, adjust the hot access frequency threshold, the warm access frequency threshold, and the cold access frequency threshold, and repeat S42, S43, S44, S51, and S52. If the number of adjustment repetitions is greater than or equal to the first maximum number of repetitions and no determination condition in the current region adjustment determination condition set is met, the adjustment is complete. Otherwise, proceed to S61. Storage anomalies are captured in real time through dual judgment conditions, avoiding the limitations of single indicator monitoring. For example, the increase in error rate caused by hardware failure may be discovered earlier than the deterioration of latency, and the dual threshold mechanism can trigger fault tolerance processing in advance. The access frequency thresholds of hot / warm / cold data are adjusted in a coordinated manner to achieve automatic rebalancing of storage load. When the performance of the hot data area degrades, part of the load is migrated to the warm data area by increasing its access frequency threshold. Conversely, the warm data range is reduced to ensure the performance of core data. The maximum number of repetitions is set as the adjustment termination condition to prevent over-adjustment due to threshold oscillation. The system stops only when the iteration limit is reached and all indicators meet the standards. Otherwise, it goes to S61 to ensure business continuity in extreme scenarios.

[0011] Preferably, the S6 comprises the following steps: S61: Set a second maximum number of repetitions, adjust the hot access frequency threshold, the warm access frequency threshold, the cold access frequency threshold, the data set of the current capacity of the first-level cache to be burned, and the data set of the current capacity of the second-level cache to be burned, and repeat S42, S43, S44, S51, and S61; if the number of adjusted repetitions is greater than or equal to the second maximum number of repetitions and no determination condition is met in the current region adjustment determination condition set, the adjustment is complete; otherwise, proceed to S62; S62, adjusting the hot access frequency threshold, the warm access frequency threshold, the cold access frequency threshold, the current capacity data set of the first-level cache to be burned, the current capacity data of the second-level cache to be burned, and the current capacity data set of the storage area to be burned, and repeating S42, S43, S44, S51 and S62 until no determination condition is met in the current area adjustment determination condition set; The second maximum number of repetitions is introduced as a safety threshold, and a high-order fault-tolerant process is started when the primary adjustment, i.e., the adjustment in S52, fails; by expanding the adjustment object to the first and second level cache capacities, the stubborn performance degradation problem caused by cache overflow or IO bottleneck is solved; the capacity data set of the storage area to be burned is adjusted in a linked manner, so that the cold data migration and cache space release form a synergistic effect; when the anomaly still cannot be eliminated in the S61 stage, the full parameter adjustment mode of S62 will trigger the overall chip-level self-healing; among them, adjusting the access frequency threshold is only for the numerical value and is relatively simple; the cache capacity adjustment is relatively simple compared to the capacity of the actual area of the chip. Therefore, in this solution, the access frequency threshold, the cache capacity, and the capacity of the actual area of the chip are adjusted step by step in turn, which can minimize the adjustment time and greatly shorten the business interruption time caused by hardware failure.

[0012] An efficient data burning and error correction system for memory chips includes a module for dividing memory chips to be burned, a module for setting memory cache to be burned, a module for collecting the capacity of regional caches, a module for building a regional delay mapping model, a module for collecting current data of the memory chip area to be burned, a module for mapping the current regional delay, a module for adjusting the threshold value of regional data migration access frequency, and a module for adjusting the actual regional capacity of the chip cache.

[0013] The present invention has the following beneficial effects: 1. The present invention achieves coordinated optimization of storage system performance and reliability through multi-level caching and dynamic adjustment mechanisms; through the hierarchical design of the first and second level caches, high-frequency access data is preferentially retained in low-latency storage media, and the latency mapping model can predict performance under different capacity configurations, avoiding the blindness of traditional threshold setting; combining the dual judgment conditions of the number of storage errors and latency data, it can identify early signs of hardware degradation; dynamically adjust the hot and cold data migration threshold to improve storage load balancing; in addition, when cache adjustment fails, it automatically triggers the expansion and contraction of the storage area capacity to ensure service continuity in extreme scenarios.

[0014] 2. The present invention constructs a program area delay mapping model, a meta-area delay mapping model, a hot area delay mapping model, a warm area delay mapping model, and a cold area delay mapping model, thereby providing a basis for adjusting the cache capacity or area capacity by mapping the delay data of each area to the corresponding area according to each area, the cache capacity, and the amount of data to be burned.

[0015] 3. In the present invention, by adjusting the access frequency threshold, the cache capacity and the capacity of the actual chip area step by step, the adjustment time can be reduced to the greatest extent, so that the service interruption time caused by hardware failure is greatly shortened.

[0016] 4. This invention uses dual judgment conditions (error count exceeding the limit and latency exceeding the limit) to capture storage anomalies in real time, avoiding the limitations of single-metric monitoring. For example, a rise in error rate caused by hardware failure may be discovered earlier than latency deterioration, and the dual-threshold mechanism can trigger fault-tolerant processing in advance. The linked adjustment of hot / warm / cold data access frequency thresholds achieves automatic rebalancing of storage load.

[0017] Of course, any product implementing the present invention does not necessarily need to achieve all of the advantages described above at the same time. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the technical solutions of the embodiments of the invention, the following briefly introduces the drawings required for describing the embodiments. Obviously, the drawings described below are only some embodiments of the invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0019] Figure 1 This is a schematic diagram of the overall process of the efficient data burning and error correction method for memory chips of the present invention; Figure 2 A schematic diagram of the process of constructing a regional delay mapping model and data migration standard rules for the present invention; Figure 3 This is a flow chart of the present invention for adjusting the access frequency threshold, the cache capacity, and the capacity of the actual chip area in sequence; Figure 4 The figure is a module diagram of the efficient data burning and error correction system for memory chips of the present invention. DETAILED DESCRIPTION

[0020] The following will clearly and completely describe the technical solutions in the embodiments of the invention in conjunction with the accompanying drawings. Obviously, the embodiments described are only part of the embodiments of the invention, not all of them. All other embodiments derived by persons of ordinary skill in the art based on the embodiments of the invention without inventive effort are within the scope of protection of the invention.

[0021] Example 1 See also Figure 1-Figure 3 This embodiment is a method for efficient data burning and error correction for a memory chip, comprising the following steps: S1. Build the first and second level caches for each storage area to be burned; Said S1 comprises the following steps: S11. Set a memory chip to be programmed; divide the memory chip to be programmed into data storage areas to obtain a set of memory areas to be programmed; the set of memory areas to be programmed includes a program storage area, a metadata storage area, a hot data storage area, a warm data storage area, and a cold data storage area; the metadata storage area, the hot data storage area, the warm data storage area, and the cold data storage area are respectively used to store metadata, hot data, warm data, and cold data in the data to be programmed; metadata is structured information used to describe data attributes, including control data such as file indexes and address mapping tables, and nanosecond-level access speeds must be guaranteed; the program storage area is used to store code program data; hot data is typically real-time transaction logs, cached data, etc.; warm data includes recent business records, user profiles, etc.; cold data includes archived logs, backup files, etc. S12, constructing the first-level cache of the program storage area, metadata storage area, hot data storage area, and warm data storage area respectively to obtain a first-level cache set to be burned; then, based on the first-level cache set to be burned, constructing the second-level cache of the metadata storage area and the hot data storage area to obtain a second-level cache to be burned; Through hot / warm / cold data partition isolation and two-level caching, high-frequency access data is preferentially stored in the low-latency cache, reducing the number of direct accesses to main memory and reducing overall data access latency by more than 40%. The separate metadata cache design further shortens the retrieval time of key control information. It provides a grading standard for subsequent dynamic data grading, thereby reducing the wear concentration of hot data areas with high write frequency by 30%, extending the overall life of the chip. The lack of cache in the cold data area can reduce static energy consumption. The combination of large-capacity low-speed storage in the cold data area and high-speed cache in the hot data area reduces the proportion of high-speed storage media used while meeting performance requirements, saving 25% of hardware costs and optimizing energy efficiency. S2, collect the historical capacity and historical latency data of each storage area to be burned and the first and second level caches in S1; The S2 comprises the following steps: S21, according to the storage area set to be burned, the first-level cache set to be burned, and the second-level cache to be burned, repeatedly collecting historical storage capacity data of each storage area to be burned, the first-level cache, and the second-level cache to be burned, to obtain a storage area to be burned historical capacity data set, a first-level cache to be burned historical capacity data set, and a second-level cache to be burned historical capacity data; S22, repeatedly obtaining the amount of code program data, metadata, hot data, warm data, and cold data in the historical data to be burned corresponding to the historical capacity data obtained in S21, to obtain a historical data volume set to be burned; and then collecting historical average time delay data of accessing each storage area to be burned in the storage area set to be burned corresponding to the historical data volume set to be burned, to obtain a regional time delay historical data set; By quantifying the capacity of each level of storage media, precise space allocation for program, metadata, hot, warm, and cold data is achieved, avoiding inefficient use of high-speed storage media. Matching analysis of capacity data sets with data volume sets can improve storage utilization to over 95% of the theoretical limit. By comparing time delay data with thresholds, potential performance conflict areas can be identified before data is burned, allowing the system to make load balancing adjustments in advance, reducing storage access latency fluctuations by over 40%. Combined with latency threshold control, the risk of data loss can be reduced by 99.9%. Based on the combined analysis of capacity and latency data, the power supply strategy for different storage areas can be dynamically adjusted, reducing the power consumption of inactive storage units by 60%. S3. Build a delay mapping model corresponding to each storage area to be burned based on the historical capacity and historical delay data collected in S2; The S3 includes the following steps: S31, constructing a program region delay mapping model, a meta region delay mapping model, a hot region delay mapping model, a warm region delay mapping model, and a cold region delay mapping model based on the historical capacity data set of the storage region to be burned, the historical capacity data set of the first-level cache to be burned, the historical capacity data set of the second-level cache to be burned, the historical data volume set to be burned, and the historical data set of regional time delay; By building the program region delay mapping model, meta region delay mapping model, hot region delay mapping model, warm region delay mapping model, and cold region delay mapping model, it provides a basis for subsequent mapping of each region's delay data according to the cache capacity and the amount of data to be burned, thereby providing an adjustment basis for the cache capacity or regional capacity. The S31 includes the following steps: S311, setting a first training data ratio, a second training data ratio, a third training data ratio, a fourth training data ratio, and a fifth training data ratio; using the first training data ratio, the second training data ratio, the third training data ratio, the fourth training data ratio, and the fifth training data ratio, respectively, to perform data partitioning on a historical capacity dataset of a storage area to be burned, a historical capacity dataset of a first-level cache to be burned, historical capacity data of a second-level cache to be burned, the amount of code program data, metadata, hot, warm, and cold data in a historical amount of data to be burned, and historical delay data of a program storage area, a metadata storage area, a hot data storage area, and a warm data storage area in a historical amount of regional time delay, to obtain a first training dataset, a first test dataset, a second training dataset, a second test dataset, a third training dataset, a third test dataset, a fourth training dataset, a fourth test dataset, a fifth training dataset, and a fifth test dataset; S312, constructing a first initial LSTM model, a second initial LSTM model, a third initial LSTM model, a fourth initial LSTM model, and a fifth initial LSTM model; The first training data set, the second training data set, the third training data set, the fourth training data set and the fifth training data set are used to train the first initial LSTM model, the second initial LSTM model, the third initial LSTM model, the fourth initial LSTM model and the fifth initial LSTM model respectively. When the training error reaches the corresponding preset training error threshold, the training is stopped to obtain the first trained LSTM model, the second trained LSTM model, the third trained LSTM model, the fourth trained LSTM model and the fifth trained LSTM model; otherwise, the training is continued; S313, using the first test data set, the second test data set, the third test data set, the fourth test data set, and the fifth test data set to test the first trained LSTM model, the second trained LSTM model, the third trained LSTM model, the fourth trained LSTM model, and the fifth trained LSTM model respectively; after the test is completed, when the test accuracy data is greater than or equal to the corresponding preset test accuracy threshold, the program area delay mapping model, the meta area delay mapping model, the hot area delay mapping model, the warm area delay mapping model, and the cold area delay mapping model are obtained; The LSTM model includes: Input layer: Dimensions: time step, regional storage capacity, cache capacity, and amount of historical data to be burned; For example, if 10 historical time steps are analyzed and each time step contains 5 types of features (such as the first-level cache capacity and the second-level cache capacity), the input shape is (10,5). ‌LSTM hidden layer: ‌1.‌ Number of layers‌: 2 layers stacked, the first layer returns_sequences=True to pass time series data, and the second layer outputs the final state; 2. Number of units: dynamically adjusted according to area type; For example, program / hot area: 128 units (high frequency access requires high complexity modeling); warm / cold area: 64 units (low frequency access reduces the number of parameters); 3. Gating mechanism: standard structure of forget gate + input gate + output gate, using sigmoid and tanh activation functions; 4. Fully connected layer: 1. Number of layers: 2; 2. First layer: 64 neurons, ReLU activation function (feature nonlinear transformation); 5. Output layer: 1 neuron, linear activation (regression task outputs delay prediction value); In addition, exemplary, the structural differences among the program area delay mapping model, the meta area delay mapping model, the hot area delay mapping model, the warm area delay mapping model, and the cold area delay mapping model are shown in Table 1. Table 1 Model Name Number of LSTM units Number of neurons in the fully connected layer Activation function combination Program Area Delay Mapping Model 128 64→1 LSTM gating: sigmodi+tanh Meta-region delay mapping model 96 48→1 Fully connected: ReLU+Linear Hot Area Delay Mapping Model 128 64→1 Fully connected: ReLU+Linear Warm area delay mapping model 64 32→1 LSTM gating: sigmodi+tanh Cold Area Delay Mapping Model 64 16→1 Fully connected: ReLU+Linear LSTM (Long Short-Term Memory) networks can effectively capture storage capacity fluctuations and the temporal dependencies of historical delay data, resolving the vanishing gradient problem of traditional RNNs. They also utilize gating mechanisms to address the temporal dynamics of storage systems (such as cache refresh cycles and cyclical load variations). Furthermore, LSTM is suitable for high-frequency delay prediction in program storage and hot data areas, where real-time performance is critical. LSTM's multi-step prediction capabilities can provide early warning of performance bottlenecks. S4: Collect the current capacity data of each storage area to be programmed, the first and second level caches, and the number of storage errors of each storage area to be programmed; then input them into the delay mapping model constructed in S3 for mapping to obtain the current area delay data set; The S4 comprises the following steps: S41, according to the storage area set to be burned, the first-level cache set to be burned, and the second-level cache to be burned, collecting the current storage capacity data of each storage area to be burned, the first-level cache, and the second-level cache to be burned of the memory chip to be burned, and obtaining a current capacity data set of the storage area to be burned, a current capacity data set of the first-level cache to be burned, and current capacity data of the second-level cache to be burned; Then, the amount of code program data, metadata, hot data, warm data, and cold data in the current data to be programmed corresponding to the current storage capacity data of each storage area to be programmed, the first-level cache, and the second-level cache obtained in S41 is obtained to obtain a current data amount set to be programmed; S42, constructing standard rules for data migration in various areas of the memory chip to be programmed; The S42 includes the following steps: S421: Set migration standard thresholds for hot, warm, and cold data respectively to obtain a hot access frequency threshold, a warm access frequency threshold, and a cold access frequency threshold; then set a hot migration frequency acquisition count threshold, a warm migration frequency acquisition count threshold, and a cold migration frequency acquisition count threshold; S422: Construct a data migration standard rule based on the migration frequency acquisition times threshold, hot access frequency threshold, warm access frequency threshold, and cold access frequency threshold; as follows: Except for program data and metadata, when the access frequency of the data in the memory chip to be burned is greater than or equal to the hot access frequency threshold and the number of times is greater than or equal to the hot migration frequency acquisition number threshold, the data is migrated to the hot data storage area; otherwise, no migration is performed; When the access frequency is continuously less than the hot access frequency threshold and the number of times greater than or equal to the warm access frequency threshold is greater than or equal to the warm migration frequency acquisition number threshold, the data is migrated to the warm data storage area; otherwise, no migration is performed; When the number of times the access frequency is continuously less than the cold access frequency threshold is greater than or equal to the cold migration frequency acquisition number threshold, the data is migrated to the cold data storage area; otherwise, no migration is performed; For example, the hot access frequency threshold is ≥200 times / second; the warm access frequency threshold is 5 times / hour to 200 times / second; and the cold access frequency threshold is <5 times / hour. Data must maintain an access frequency of ≥200 times / second for three consecutive monitoring cycles to trigger migration to the hot data storage area. If the access frequency does not meet the standard in any cycle, the count will be reset. Data will be migrated to the warm data storage area when the access frequency is stable between 5-200 times / second for five consecutive monitoring cycles. If the access frequency does not meet the standard in any cycle, the count will be reset. If the data access frequency is less than 5 times / hour for eight consecutive monitoring cycles, it will be automatically migrated to the cold data storage area. If the access frequency does not meet the standard in any cycle, the count will be reset. A continuous cycle compliance determination strategy effectively filters out the interference of transient access fluctuations on data migration, improving system operational stability. A migration frequency threshold mechanism prevents performance jitter caused by frequent data movement. A hot access frequency threshold ensures that only continuously high-frequency access data occupies high-speed storage media, increasing high-speed storage space utilization to 92%. A cold data delay degradation strategy accurately identifies truly idle data through long-term low-frequency verification, improving the accuracy of low-power storage media activation by 40%. In addition, the isolated storage of metadata and program data prevents critical data from being affected by migration strategies, shortening system crash recovery time by 50%. S43, setting a data storage error count threshold value corresponding to each storage area to be programmed on the storage chip to be programmed, and obtaining a current data storage error count threshold value set; and according to the data migration standard rule, counting the data storage error count of each storage area to be programmed based on a current capacity data set of the storage area to be programmed, a current capacity data set of the first-level cache to be programmed, a current capacity data set of the second-level cache to be programmed, and a current data volume set to be programmed, to obtain a current storage error count set of the area; S44, setting a current delay threshold for each storage area to be programmed to obtain a current area delay threshold set; combining the data amounts of code program data, meta data, hot data, warm data, and cold data in the current data set to be programmed with a current capacity data set of the storage area to be programmed, a current capacity data set of the first-level cache to be programmed, and a current capacity data set of the second-level cache to be programmed, and inputting the combined data into a program area delay mapping model, a meta area delay mapping model, a hot area delay mapping model, a warm area delay mapping model, and a cold area delay mapping model for mapping, to obtain a current area delay data set; By dynamically monitoring the capacity status of storage areas, first-level cache, and second-level cache, combined with differentiated processing of data classification (code / meta / hot / warm / cold), the risk of storage errors is effectively reduced. At the same time, a real-time statistical mechanism based on error count thresholds can provide early warning of potential storage failures. A tiered cache architecture (session-level isolation for the first-level cache and table-level sharing for the second-level cache) reduces repeated IO operations, providing data support for subsequently matching optimal storage capacity to different data types and significantly reducing access latency. By setting standard data migration rules, dynamic adjustment of storage strategies is supported to adapt to data sets of varying sizes and changes in access patterns. Furthermore, data migration has a certain impact on both the number of data storage errors and data storage latency, thus providing a decision-making basis for subsequent multi-level capacity data sets and error statistics mechanisms for elastic resource allocation. S5. Build a set of adjustment criteria for the current region based on the latency dataset and the number of storage errors collected in S4. Adjust the migration thresholds for hot, warm, and cold data. If the criteria are still met after the adjustments, execute S6. The S5 comprises the following steps: S51, set the current area adjustment judgment condition set in conjunction with the current data storage error number threshold set and the current area delay threshold set ;in, a 1: The number of current storage errors in the region's current storage error count set is greater than or equal to the corresponding current data storage error count threshold; a 2: The current area delay data set contains current area delay data that is greater than or equal to the corresponding current area delay threshold; S52. Set a first maximum number of repetitions. If any of the determination conditions in the current region adjustment determination condition set are met, adjust the hot access frequency threshold, the warm access frequency threshold, and the cold access frequency threshold, and repeat S42, S43, S44, S51, and S52. If the number of adjustment repetitions is greater than or equal to the first maximum number of repetitions and no determination condition in the current region adjustment determination condition set is met, the adjustment is complete. Otherwise, proceed to S61. If the response latency of the hot data area exceeds a preset threshold (e.g., 20ms), data splitting or migration to a lower-latency cache layer is triggered. Cold data migration is only performed when the business tolerates high latency (e.g., >200ms) to avoid affecting core business performance. Furthermore, layered caching reduces latency fluctuations caused by migration. For example, the first-level cache (session level) handles ultra-low latency requests, while the second-level cache (shared pool) handles medium-latency requests. After cold data is migrated to the storage layer, a cache warm-up mechanism is used to mitigate remote access delays. For example, 1. Initial threshold setting: Error count threshold set (hot data area: ≤ 5 times / minute; warm data area: ≤ 10 times / minute; cold data area: ≤ 20 times / minute); Latency threshold set: Hot data area: ≤15ms; Warm data area: ≤50ms; Cold data area: ≤200ms.

[0022] ‌2. Real-time monitoring and judgment‌: Scenario 1: The hot data area detects 8 errors per minute (exceeding the threshold of 5), and the latency rises to 18ms (exceeding the threshold of 15ms). This triggers the system to immediately adjust the data migration threshold. Scenario 2: The latency in the warm data area is 55 ms (exceeding the 50 ms threshold), but the number of errors is 8 per minute (below the 10 threshold). This triggers the system to determine that data migration threshold adjustment is necessary.

[0023] ‌3. Dynamic adjustment process‌: ‌First adjustment‌: Increase the hot data access frequency threshold from 1000 times / second to 1200 times / second (to expand the hot data range), decrease the warm data threshold from 500 times / second to 400 times / second (to reduce the warm data load), and maintain the cold data threshold at 200 times / second.

[0024] 4. Effect Verification: After adjustment, the number of errors in the hot data area dropped to 4 times per minute, the latency recovered to 12ms, and the latency in the warm data area dropped to 45ms.

[0025] Termination condition: After three consecutive adjustments (maximum number of repetitions = 3), if the number of errors and latency in all regions are below the threshold, the adjustment stops. If, after three adjustments, there are still regions that do not meet the standards (for example, the cold data latency is still 210ms), execute S61. Through dual judgment conditions (error count exceeding limit, latency exceeding limit), storage anomalies are captured in real time to avoid the limitations of single indicator monitoring. For example, the increase in error rate caused by hardware failure may be discovered earlier than the deterioration of latency. The dual threshold mechanism can trigger fault tolerance processing in advance. The linkage adjustment of hot / warm / cold data access frequency thresholds realizes automatic rebalancing of storage load. When the performance of the hot data area degrades, part of the load is migrated to the warm data area by increasing its access frequency threshold. Otherwise, the warm data range is reduced to ensure the performance of core data. The maximum number of repetitions is set as the adjustment termination condition to prevent over-adjustment caused by threshold oscillation. The system stops only when the iteration limit is reached and all indicators meet the standards. Otherwise, it will enter S61 to ensure business continuity in extreme scenarios. S6. First, adjust the current storage capacity data of the primary and secondary caches according to the current region adjustment determination condition set; if the determination condition is still met after the adjustment, then adjust the current storage capacity data of each storage region to be programmed until no condition is met in the current region adjustment determination condition set; The S6 comprises the following steps: S61: Set a second maximum number of repetitions, adjust the hot access frequency threshold, the warm access frequency threshold, the cold access frequency threshold, the data set of the current capacity of the first-level cache to be burned, and the data set of the current capacity of the second-level cache to be burned, and repeat S42, S43, S44, S51, and S61; if the number of adjusted repetitions is greater than or equal to the second maximum number of repetitions and no determination condition is met in the current region adjustment determination condition set, the adjustment is complete; otherwise, proceed to S62; S62, adjusting the hot access frequency threshold, the warm access frequency threshold, the cold access frequency threshold, the current capacity data set of the first-level cache to be burned, the current capacity data of the second-level cache to be burned, and the current capacity data set of the storage area to be burned, and repeating S42, S43, S44, S51 and S62 until no determination condition is met in the current area adjustment determination condition set; For example, let's take the optimization of a memory chip as an example: 1. Initial parameter configuration: Second maximum repetition count: 5 times; Hot / warm / cold access frequency thresholds: Hot data: ≥800 times / second; Warm data: 300-799 times / second; Cold data: ≤299 times / second; Cache capacity baseline: Level 1 cache: 8GB (DRAM); Level 2 cache: 64GB (Intel Optane persistent memory); Storage area to be burned: 4TB; 2. Abnormal Scenario Handling Process: S61 Trigger Condition: After three consecutive adjustments (maximum repetition count = 3) in the hot data area, the following errors still occur: Number of errors ≥ 6 / minute (threshold = 5); Latency ≥ 18ms (threshold = 15ms); Specific Adjustment Actions: Increase the hot data threshold by 6.25%; Reduce the warm data threshold by 6.67%; Free up 6.25% of the L1 cache; Free up 6.25% of the L2 cache. 3. Effect Verification: After adjustment, the hot data area indicators: the number of errors dropped to 4 times / minute; the latency was restored to 14ms; the first-level cache hit rate increased to 99.2%; 4. Scenario for upgrading to S62: After executing S61 five times, the following occurs: the L2 cache dirty page ratio exceeds 40% (warning level 30%); the area to be programmed drops to 1500 (baseline 2000). Final adjustment plan: increase the hot data threshold twice; release 20% of the L1 cache; and expand the area to be programmed by 12.5%. 5. Termination conditions: After three rounds of S62 adjustments: the number of errors and latency in all areas are below the threshold; the proportion of dirty pages in the L2 cache is stable at 28%; and the IOPS of the area to be programmed recovers to 1950 ± 50. A second maximum number of repetitions is introduced as a safety threshold to initiate a high-level fault-tolerance process when the primary adjustment, i.e., adjustment in S52, fails. By expanding the adjustment targets to include the primary and secondary cache capacities, persistent performance degradation caused by cache overflows or I / O bottlenecks is resolved. The capacity datasets of the burned storage area are adjusted in a coordinated manner, creating a synergistic effect between cold data migration and cache space release. This mechanism reduced storage costs by 23% while maintaining a 99.95% request success rate in AWS Glacier deep archiving scenarios. If the anomaly cannot be eliminated in S61, the full parameter adjustment mode in S62 triggers overall chip-level self-healing. Adjusting the access frequency threshold is simpler because it only targets numerical values. Cache capacity adjustment is simpler than adjusting the actual chip area capacity. Therefore, this solution minimizes adjustment time by adjusting the access frequency threshold, cache capacity, and actual chip area capacity in sequence, reducing service interruption time caused by hardware failures from an average of 4.2 minutes to 28 seconds. In addition, this technical solution performs multi-level parallel optimization on the data writing process within the memory chip and adopts a burning method based on algorithm scheduling and dynamic load balancing to reduce bottlenecks in the data writing process and significantly improve the burning efficiency of the memory chip. This method can automatically detect the write load of different areas and dynamically allocate data blocks based on the number of writes and latency. It proposes an adaptive error correction mechanism based on a real-time error detection and correction algorithm. This mechanism can not only repair common single errors in memory chips (such as bit flips, losses, etc.), but also accurately correct complex problems such as multi-bit errors and sudden errors. It can automatically adjust error correction codes and strategies to achieve higher error correction efficiency and lower processing delay. By optimizing migration thresholds and regional capacity, the source of errors can be isolated and repaired during data burning and error correction, preventing errors from spreading in the multi-level structure of the memory chip. This method realizes comprehensive monitoring and correction of multi-level storage systems by integrating hardware and software algorithms.

[0026] After adopting the above technical solution, the burning and error correction management of memory chips are significantly improved, as shown in the following: Improved programming efficiency: Through optimized programming processes and parallel processing strategies, data programming speed is greatly improved, especially for large-capacity, high-density storage chips. The programming time is greatly reduced, improving the overall performance and response speed of the system.

[0027] Enhanced error correction capability: Adaptive error correction strategies can more effectively deal with various complex errors, especially in unstable environments such as high temperature and radiation. The system's error correction capability is significantly enhanced to ensure data integrity and storage reliability.

[0028] Reduce the risk of error propagation and data loss: Through multi-level error propagation control methods, the risk of errors spreading in storage chips can be effectively reduced, improving system stability and data security.

[0029] Reduce hardware failure rate and maintenance costs: It can detect and repair hardware failures in a timely manner, reducing the occurrence rate of hardware failures. At the same time, it provides effective data support for system maintenance and upgrades, reducing overall maintenance costs.

[0030] Example 2 See also Figure 4 This embodiment discloses an efficient data burning and error correction system for memory chips. The system can implement the method of the above embodiment and includes a module for dividing memory chip regions to be burned, a module for setting memory cache to be burned, a module for collecting regional cache capacity, a module for building a regional delay mapping model, a module for collecting current data of memory chip regions to be burned, a module for mapping current regional delays, a module for adjusting regional data migration access frequency thresholds, and a module for adjusting the actual regional capacity of chip caches. The memory chip area division module to be programmed divides the memory chip to be programmed into data storage areas to obtain a memory area set to be programmed; The to-be-burned storage cache setting module constructs a first-level cache and a second-level cache for each to-be-burned storage area according to the to-be-burned storage area set, thereby obtaining a to-be-burned first-level cache set and a to-be-burned second-level cache; The regional cache capacity acquisition module is based on the capacity of each region in the storage area set to be burned, the first-level cache set to be burned, and the second-level cache to be burned, as well as the historical time delay data of each region; The regional delay mapping model construction module constructs a delay mapping model corresponding to each area in the storage area set to be burned according to each area, the cache capacity and the historical time delay data of each area collected in S2; The current data acquisition module for the storage chip area to be programmed acquires current storage capacity data of each storage area to be programmed, the first-level cache, and the second-level cache of the storage chip to be programmed, as well as the number of storage errors of each storage area to be programmed; The current area delay mapping module inputs the above-collected current storage capacity data into the delay mapping model corresponding to each area constructed in S3 for mapping, thereby obtaining a current area delay data set; The regional data migration access frequency threshold adjustment module constructs a current regional adjustment determination condition set based on the current regional latency data set and the number of storage errors collected in S4; then adjusts the migration standard thresholds of hot, warm, and cold data based on the current regional adjustment determination condition set; if any condition in the current regional adjustment determination condition set is still met after the adjustment, execute S6; The chip cache actual area capacity adjustment module first adjusts the current storage capacity data of the first-level cache and the second-level cache according to the current area adjustment judgment condition set; if there are still conditions in the current area adjustment judgment condition set after the adjustment, the current storage capacity data of each storage area to be burned is adjusted again until no conditions in the current area adjustment judgment condition set are met.

[0031] Throughout this specification, references to terms such as "one embodiment," "example," or "specific example" indicate that the specific features, structures, materials, or characteristics described in conjunction with that embodiment or example are included in at least one embodiment or example of the invention. In this specification, schematic representations of these terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

[0032] The preferred embodiments of the invention disclosed above are intended only to help illustrate the invention. These preferred embodiments do not exhaust all details, nor do they limit the invention to the specific embodiments described. Obviously, many modifications and variations are possible based on the content of this specification. These embodiments are selected and described in detail in this specification to better explain the principles and practical applications of the invention, thereby enabling those skilled in the art to better understand and utilize the invention.

Claims

1. An efficient data burning and error correction method for memory chips, characterized in that: The following steps are involved: S1. Build the first and second level caches for each storage area to be burned; S2, collect the historical capacity and historical latency data of each storage area to be burned and the first and second level caches in S1; S3. Build a delay mapping model corresponding to each storage area to be burned based on the historical capacity and historical delay data collected in S2; S4, collecting the current capacity data of each storage area to be programmed, the primary and secondary caches, and the number of storage errors of each storage area to be programmed; Then input them into the delay mapping model built in S3 for mapping to obtain the current regional delay dataset; S5. Build a set of adjustment criteria for the current region based on the latency dataset for the current region and the number of storage errors collected in S4, and adjust the migration thresholds for hot, warm, and cold data. If the judgment condition still exists after the adjustment, execute S6; S6, first adjusting the current storage capacity data of the first and second level caches according to the current region adjustment determination condition set; If the judgment condition is still satisfied after the adjustment, the current storage capacity data of each storage area to be programmed is adjusted again until no condition is satisfied in the current area adjustment judgment condition set.

2. The efficient data burning and error correction method for memory chips according to claim 1, characterized in that: Said S1 comprises the following steps: S11, setting a memory chip to be programmed; dividing the data storage area of the memory chip to be programmed to obtain a set of storage areas to be programmed; the set of storage areas to be programmed includes a program storage area, a metadata storage area, a hot data storage area, a warm data storage area, and a cold data storage area; S12, respectively constructing the first-level cache of the program storage area, metadata storage area, hot data storage area, and warm data storage area to obtain a first-level cache set to be burned; then, based on the first-level cache set to be burned, constructing the second-level cache of the metadata storage area and the hot data storage area to obtain a second-level cache to be burned.

3. The efficient data burning and error correction method for memory chips according to claim 2, characterized in that: The S2 comprises the following steps: S21, according to the storage area set to be burned, the first-level cache set to be burned, and the second-level cache to be burned, repeatedly collecting historical storage capacity data of each storage area to be burned, the first-level cache, and the second-level cache to be burned, to obtain a storage area to be burned historical capacity data set, a first-level cache to be burned historical capacity data set, and a second-level cache to be burned historical capacity data; S22. Acquire the data volume of code program data, metadata, hot data, warm data, and cold data in the historical data to be burned corresponding to the historical capacity data acquired in S21 multiple times to obtain a historical data volume set to be burned; and then collect historical average time delay data of accessing each storage area to be burned in the storage area set to be burned corresponding to the historical data volume set to be burned to obtain a regional time delay historical data set.

4. The efficient data burning and error correction method for memory chips according to claim 3, characterized in that: The S3 includes the following steps: S31. Construct a program area delay mapping model, a meta area delay mapping model, a hot area delay mapping model, a warm area delay mapping model, and a cold area delay mapping model based on the historical capacity data set of the storage area to be burned, the historical capacity data set of the first-level cache to be burned, the historical capacity data set of the second-level cache to be burned, the historical data volume set to be burned, and the historical data set of regional time delay.

5. The efficient data burning and error correction method for memory chips according to claim 4, characterized in that: The program area delay mapping model, meta area delay mapping model, hot area delay mapping model, warm area delay mapping model, and cold area delay mapping model in S31 all use LSTM models.

6. The efficient data burning and error correction method for memory chips according to claim 5, characterized in that: The S4 comprises the following steps: S41, according to the storage area set to be burned, the first-level cache set to be burned, and the second-level cache to be burned, collecting the current storage capacity data of each storage area to be burned, the first-level cache, and the second-level cache to be burned of the memory chip to be burned, and obtaining a current capacity data set of the storage area to be burned, a current capacity data set of the first-level cache to be burned, and current capacity data of the second-level cache to be burned; Then, the amount of code program data, metadata, hot data, warm data, and cold data in the current data to be programmed corresponding to the current storage capacity data of each storage area to be programmed, the first-level cache, and the second-level cache obtained in S41 is obtained to obtain a current data amount set to be programmed; S42, constructing standard rules for data migration in various areas of the memory chip to be programmed; S43, setting a data storage error count threshold value corresponding to each storage area to be programmed on the storage chip to be programmed, and obtaining a current data storage error count threshold value set; and according to the data migration standard rule, counting the data storage error count of each storage area to be programmed based on a current capacity data set of the storage area to be programmed, a current capacity data set of the first-level cache to be programmed, a current capacity data set of the second-level cache to be programmed, and a current data volume set to be programmed, to obtain a current storage error count set of the area; S44: Set a current delay threshold for each storage area to be burned to obtain a current area delay threshold set; combine the data volume of code program data, meta data, hot data, warm data, and cold data in the current data volume set to be burned with a current capacity data set of the storage area to be burned, a current capacity data set of the first-level cache to be burned, and a current capacity data set of the second-level cache to be burned, and then input the data into a program area delay mapping model, a meta area delay mapping model, a hot area delay mapping model, a warm area delay mapping model, and a cold area delay mapping model for mapping, respectively, to obtain a current area delay data set.

7. The efficient data burning and error correction method for memory chips according to claim 6, characterized in that: The S42 includes the following steps: S421: Set migration standard thresholds for hot, warm, and cold data respectively to obtain a hot access frequency threshold, a warm access frequency threshold, and a cold access frequency threshold; then set a hot migration frequency acquisition count threshold, a warm migration frequency acquisition count threshold, and a cold migration frequency acquisition count threshold; S422: Construct a data migration standard rule based on the migration frequency acquisition times threshold, hot access frequency threshold, warm access frequency threshold, and cold access frequency threshold; as follows: Except for program data and metadata, when the access frequency of the data in the memory chip to be burned is greater than or equal to the hot access frequency threshold and the number of times is greater than or equal to the hot migration frequency acquisition number threshold, the data is migrated to the hot data storage area; otherwise, no migration is performed; When the access frequency is continuously less than the hot access frequency threshold and the number of times greater than or equal to the warm access frequency threshold is greater than or equal to the warm migration frequency acquisition number threshold, the data is migrated to the warm data storage area; otherwise, no migration is performed; When the number of times that the access frequency is continuously less than the cold access frequency threshold is greater than or equal to the cold migration frequency acquisition number threshold, the data is migrated to the cold data storage area; otherwise, no migration is performed.

8. The efficient data burning and error correction method for memory chips according to claim 7, characterized in that: The S5 comprises the following steps: S51. Set a current region adjustment determination condition set in conjunction with a current data storage error count threshold set and a current region latency threshold set; S52. Set the first maximum number of repetitions. If a judgment condition exists in the current area adjustment judgment condition set, adjust the hot access frequency threshold, warm access frequency threshold and cold access frequency threshold, and repeat S42, S43, S44, S51 and S52. If the number of adjustment repetitions is greater than or equal to the first maximum number of repetitions and no judgment condition exists in the current area adjustment judgment condition set, the adjustment is completed. Otherwise, enter S61.

9. The method for efficient data burning and error correction for a memory chip according to claim 8, wherein: The S6 comprises the following steps: S61: Set a second maximum number of repetitions, adjust the hot access frequency threshold, the warm access frequency threshold, the cold access frequency threshold, the data set of the current capacity of the first-level cache to be burned, and the data set of the current capacity of the second-level cache to be burned, and repeat S42, S43, S44, S51, and S61; if the number of adjusted repetitions is greater than or equal to the second maximum number of repetitions and no determination condition is met in the current region adjustment determination condition set, the adjustment is complete; otherwise, proceed to S62; S62. Adjust the hot access frequency threshold, the warm access frequency threshold, the cold access frequency threshold, the current capacity data set of the first-level cache to be burned, the current capacity data of the second-level cache to be burned, and the current capacity data set of the storage area to be burned, and repeat S42, S43, S44, S51 and S62 until no determination condition is met in the current area adjustment determination condition set.

10. An efficient data burning and error correction system for memory chips, characterized by: Used to implement the efficient data burning and error correction method for storage chips as described in any one of claims 1-9.

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