Memory control method and storage device

Abstract

The invention provides a memory control method and a storage device. The method comprises the following steps: determining a first coding rule according to the type of first data; according to a first coding rule, coding first sub-data in the first data to generate a first error correction code corresponding to the first data, and not coding second sub-data in the first data; storing the first data and the first error correction code in a first entity unit; reading second data and a first error correction code from the first entity unit; and correcting an error in the second data based on the first error correction code. Therefore, the data reading speed can be effectively improved on the premise of not influencing the data protection capability of the storage device.

Description

Technical Field

[0001] The present invention relates to the field of memory control technology, and in particular to a memory control method and a storage device. Background Art

[0002] In solid-state storage devices (SSDs), due to the characteristics of their internal flash memory technology, data is prone to various types of errors during storage, especially bit flip errors. This requires the SSD controller to integrate error checking and correction (ECC) circuits to ensure data integrity.

[0003] In solid-state drives (SSDs), the Error Correction Code (ECC) circuit is a key component used to detect and correct bit errors that occur within storage cells. ECC adds redundant information to the original data, enabling the SSD controller to detect and correct a certain number of bit errors when reading data, thereby maintaining data integrity and reliability. Although ECC can significantly improve data reliability, its correction capability has an upper limit, meaning that ECC can only correct erroneous bits within a specific range. If the errors occurring within a storage block exceed the maximum error rate that the ECC algorithm can tolerate (commonly referred to as the "erasure capability" of the erasure code), then even with the presence of the ECC mechanism, the data in that block cannot be recovered, which will result in irrecoverable data loss.

[0004] In view of this, how to effectively manage NAND flash memory has become one of the core topics of concern to engineers in the industry. Summary of the Invention

[0005] The present invention provides a memory control method and a memory device, which can improve the decoding efficiency of the memory device.

[0006] An embodiment of the present invention provides a memory control method for a storage device, wherein the storage device includes a memory module, and the memory control method includes: obtaining first data; detecting the type of the first data; determining a first encoding rule corresponding to the first data based on the type; encoding first sub-data in the first data according to the first encoding rule to generate a first error correction code corresponding to the first data, and not encoding second sub-data in the first data; after obtaining the first error correction code, storing the first data and the first error correction code in at least one first physical unit in the memory module; after storing the first data and the first error correction code in the at least one first physical unit, reading second data and the first error correction code from the at least one first physical unit; and correcting errors in the second data based on the first error correction code.

[0007] An embodiment of the present invention further provides a storage device, which includes a connection interface, a memory module, and a memory controller. The connection interface is used to connect to a host system. The memory controller is connected to the connection interface and the memory module. The memory controller is used to: obtain first data; detect the type of the first data; determine a first encoding rule corresponding to the first data based on the type; encode the first sub-data in the first data according to the first encoding rule to generate a first error correction code corresponding to the first data, and not encode the second sub-data in the first data; after obtaining the first error correction code, store the first data and the first error correction code in at least one first physical unit in the memory module; after storing the first data and the first error correction code in the at least one first physical unit, read second data and the first error correction code from the at least one first physical unit; and correct errors in the second data based on the first error correction code.

[0008] Based on the above, after determining the type of the first data, a first encoding rule corresponding to the first data can be determined. Based on the first encoding rule, the first sub-data within the first data can be encoded to generate a first error correction code, and the first data and the first error correction code can be stored in the memory module. Specifically, the second sub-data within the first data is not encoded. Subsequently, after reading the second data and the first error correction code from the first physical unit, errors in the second data can be corrected based on the first error correction code. This improves the decoding efficiency of one or more special types of data and increases data read speed. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 is a schematic diagram of a data storage system according to an embodiment of the present invention;

[0010] Figure 2 is a schematic diagram of a memory controller according to an embodiment of the present invention;

[0011] Figure 3 is a schematic diagram of a management memory module according to an embodiment of the present invention;

[0012] Figure 4 is a schematic diagram of encoding first sub-data in first data to generate a first error correction code according to an embodiment of the present invention;

[0013] Figure 5 is a schematic diagram of encoding first sub-data in first data to generate a first error correction code according to an embodiment of the present invention;

[0014] Figure 6 is a schematic diagram showing determining first sub-data from first data according to a data screening mask according to an embodiment of the present invention;

[0015] Figure 7 is a schematic diagram of decoding second data based on a first error correction code according to an embodiment of the present invention;

[0016] Figure 8 FIG. 4 is a flowchart of a memory control method according to an embodiment of the present invention. DETAILED DESCRIPTION

[0017] Reference will now be made in detail to exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Whenever possible, the same reference numerals are used in the drawings and the description to refer to the same or like parts.

[0018] Figure 1 Schematic diagram of a data storage system according to an embodiment of the present invention. Figure 1 The data storage system 10 includes a host system 11 and a storage device 12. The storage device 12 can be connected to the host system 11 and can be used to store data from the host system 11. For example, the host system 11 can be a smartphone, a tablet computer, a laptop computer, a desktop computer, an industrial computer, a game console, a server, or a computer system installed in a specific carrier (such as a vehicle, aircraft, or ship), and the type of host system 11 is not limited to this. In addition, the storage device 12 can include a solid-state drive, a USB flash drive, a memory card, or other types of non-volatile storage devices.

[0019] The storage device 12 includes a connection interface 121, a memory module 122, and a memory controller 123. The connection interface 121 is used to connect the storage device 12 to the host system 11. For example, the connection interface 121 may support an embedded Multi-Media Card (eMMC), Universal Flash Storage (UFS), Peripheral Component Interconnect Express (PCI Express), Non-Volatile Memory Express (NVM express), Serial Advanced Technology Attachment (SATA), Universal Serial Bus (USB), or other types of connection interface standards. Therefore, the storage device 12 can communicate with the host system 11 (e.g., exchange signals, instructions, and / or data) via the connection interface 121.

[0020] The memory module 122 is used to store data. For example, the memory module 122 may include one or more rewritable non-volatile memory modules. Each rewritable non-volatile memory module may include one or more memory cell arrays. The memory cells in the memory cell array store data in the form of a voltage (also known as a threshold voltage). For example, the memory module 122 may include a single-level cell (SLC) NAND flash memory module, a multi-level cell (MLC) NAND flash memory module, a triple-level cell (TLC) NAND flash memory module, a quad-level cell (QLC) NAND flash memory module, and / or other memory modules having the same or similar characteristics.

[0021] The memory controller 123 is connected to the connection interface 121 and the memory module 122. The memory controller 123 can be considered the control core of the memory device 12 and is used to control the memory device 12. For example, the memory controller 123 can be used to control or manage all or part of the operation of the memory device 12. For example, the memory controller 123 may include a central processing unit (CPU), or other programmable general-purpose or special-purpose microprocessor, a digital signal processor (DSP), a programmable controller, an application-specific integrated circuit (ASIC), a programmable logic device (PLD), or other similar devices or a combination of these devices. In one embodiment, the memory controller 123 may include a flash memory controller.

[0022] The memory controller 123 can send a command sequence to the memory module 122 to access the memory module 122. For example, the memory controller 123 can send a write command sequence to the memory module 122 to instruct the memory module 122 to store data in a specific memory cell. For example, the memory controller 123 can send a read command sequence to the memory module 122 to instruct the memory module 122 to read data from a specific memory cell. For example, the memory controller 123 can send an erase command sequence to the memory module 122 to instruct the memory module 122 to erase data stored in a specific memory cell. Furthermore, the memory controller 123 can send other types of command sequences to the memory module 122 to instruct the memory module 122 to perform other types of operations, and the present invention is not limited thereto. The memory module 122 can receive the command sequence from the memory controller 123 and access the memory cells within the memory module 122 according to the command sequence.

[0023] Figure 2 FIG is a schematic diagram of a memory controller according to an embodiment of the present invention. Figure 1 and Figure 2 The memory controller 123 includes a host interface 21, a memory interface 22, and a memory control circuit 23. The host interface 21 is used to connect to the host system 11 through the connection interface 121 to communicate with the host system 11. The memory interface 22 is used to connect to the memory module 122 to access the memory module 122.

[0024] The memory control circuit 23 is connected to the host interface 21 and the memory interface 22. The memory control circuit 23 can be used to control or manage all or part of the operation of the memory controller 123. For example, the memory control circuit 23 can communicate with the host system 11 via the host interface 21 and access the memory module 122 via the memory interface 22. For example, the memory control circuit 23 may include a control circuit such as an embedded controller or a microcontroller. In the following embodiments, the description of the memory control circuit 23 is equivalent to the description of the memory controller 123.

[0025] In one embodiment, the memory controller 123 may further include a buffer memory 24. The buffer memory 24 is connected to the memory control circuit 23 and is used to cache data. For example, the buffer memory 24 may be used to cache instructions from the host system 11, data from the host system 11, and / or data from the memory module 122.

[0026] In one embodiment, the memory controller 123 may further include an error correction circuit 25. The error correction circuit 25 is connected to the memory control circuit 23 and is used to encode and decode data to ensure data accuracy. For example, the error correction circuit 25 may support various encoding / decoding algorithms such as low-density parity check code (LDPC code), BCH code, Reed-Solomon code (RS code), and exclusive OR (XOR) code. In one embodiment, the memory controller 123 may also include various other types of circuit modules (such as power management circuits), and the present invention is not limited thereto.

[0027] Figure 3 FIG is a schematic diagram of a management memory module according to an embodiment of the present invention. Figures 1 to 3 The memory module 122 includes a plurality of physical units 301 ( 1 ) to 301 (B). Each physical unit includes a plurality of storage cells and is used for non-volatile data storage.

[0028] In one embodiment, a physical unit may include a physical programming unit. In one embodiment, a physical programming unit may include multiple physical sectors. For example, the data capacity of a physical sector may be 512 bytes (B), and a physical programming unit may include 32 physical sectors. However, the data capacity of a physical sector and / or the total number of physical sectors included in a physical programming unit may be adjusted according to practical needs, and the present invention is not limited thereto. In one embodiment, a physical programming unit may be regarded as a physical page. For example, the storage capacity of a physical programming unit may be 16 kilobytes, and the present invention is not limited thereto.

[0029] In one embodiment, a physical programming unit is the smallest unit to which data is written synchronously in the memory module 122. For example, when a programming operation (also referred to as a write operation) is performed on a physical programming unit to write data to the physical programming unit, multiple memory cells in the physical programming unit may be programmed synchronously to store corresponding data. For example, when programming a physical programming unit, a write voltage may be applied to the physical programming unit to change the threshold voltage of at least some of the memory cells in the physical programming unit. For example, the threshold voltage of a memory cell may reflect the bit data stored in the memory cell.

[0030] In one embodiment, a physical erase unit may include multiple physical programming units. Multiple physical programming units in a physical erase unit can be erased simultaneously. For example, when performing an erase operation on a physical erase unit, an erase voltage may be applied to multiple physical programming units in the physical erase unit to change the threshold voltage of at least some of the memory cells in these physical programming units. By performing an erase operation on a physical erase unit, data stored in the physical erase unit can be cleared. In one embodiment, a physical erase unit can be considered a physical block.

[0031] In one embodiment, the memory control circuit 23 can logically associate the physical units 301(1)-301(A) and 301(A+1)-301(B) with the data area 31 and the idle area 32, respectively. The physical units 301(1)-301(A) in the data area 31 all store data (also called user data) from the host system 11. For example, any physical unit in the data area 31 can store valid data and / or invalid data. In addition, the physical units 301(A+1)-301(B) in the idle area 32 do not store data (e.g., valid data).

[0032] In one embodiment, if a physical unit does not store valid data, the physical unit may be associated with the idle area 32. Furthermore, the physical units in the idle area 32 may be erased to clear the data in the physical units. In one embodiment, the physical units in the idle area 32 are also referred to as idle physical units. In one embodiment, the idle area 32 is also referred to as a free pool.

[0033] In one embodiment, when data is to be stored, the memory control circuit 23 may select one or more physical cells from the idle area 32 and instruct the memory module 122 to store the data in the selected physical cells. After the data is stored in the physical cells, the physical cells may be associated with the data area 31. In other words, one or more physical cells may be used alternately between the data area 31 and the idle area 32.

[0034] In one embodiment, the memory control circuit 23 may configure a plurality of logical units 302(1)-302(C) to map the physical units (i.e., physical units 301(1)-301(A)) in the data area 31. For example, a logical unit may correspond to a logical block address (LBA) or other logical management unit. A logical unit may be mapped to one or more physical units.

[0035] In one embodiment, if a physical unit is currently mapped by any logical unit, the memory control circuit 23 may determine that the data currently stored in the physical unit includes valid data. Conversely, if a physical unit is currently not mapped by any logical unit, the memory control circuit 23 may determine that the physical unit does not currently store any valid data.

[0036] In one embodiment, the memory control circuit 23 may record the mapping relationship between the logical units and the physical units in at least one management table (also referred to as a logical-to-physical mapping table). In one embodiment, the memory control circuit 23 may instruct the memory module 122 to perform operations such as data read, write, or erase based on the information in the management table (i.e., the logical-to-physical mapping table).

[0037] In one embodiment, the memory control circuit 23 can obtain data to be stored (also referred to as first data). The first data can generally refer to various data to be stored in the memory module 122. For example, the first data may include data from the host system 11 (e.g., user data), program code for operating the storage device 12 (also referred to as firmware code), and / or data for managing the storage device 12 (also referred to as system data). User data refers to data that a user wants to save, such as documents, images, video files, etc. In addition, the program code for operating the storage device 12 may include firmware code. This firmware code may be stored in the memory controller 123 or the memory module 122.

[0038] In one embodiment, the system data includes one or more types of management data for a file system of the storage device 12. For example, the system data may include management data for various file systems such as FAT32, exFAT (Extended File Allocation Table), NTFS, ext4, F2FS (Flash-Friendly File System), YAFFS, APFS (Apple File System), Btrfs, or ZFS. The system data is crucial for managing and maintaining the file system and its structure of the storage device 12. Different types of storage devices 12 may use different file systems, and the data structures within different types of file systems may also differ.

[0039] FAT32 was the most common file system for early USB flash drives. It offers wide compatibility, and nearly all operating systems can read and write to FAT32-formatted USB flash drives. However, FAT32 has a file size limit of 4GB. exFAT was developed by Microsoft to address the limitations of FAT32, particularly its support for large files. exFAT supports larger files and is well supported in both Windows and macOS, gradually becoming the new standard for USB flash drives. NTFS is primarily used on Windows operating systems. While some USB flash drives may use NTFS, its cross-platform compatibility is not as good as FAT32 or exFAT. Ext4 is commonly found on eMMC storage in Android devices. Ext4 is a journaling file system that provides improved data integrity and recovery capabilities and is widely used in Linux systems. F2FS is a flash-optimized file system primarily used in Android devices to improve performance and extend flash memory life. YAFFS was once used as a file system for embedded systems, particularly on Android devices with earlier kernel versions. Btrfs is an advanced file system designed for Linux that supports replication, snapshots, and checksums. Although it is still under development, it has been adopted in some scenarios. ZFS is another advanced file system that was originally developed by Sun Microsystems and is now found in many systems. It provides features such as data redundancy, compression, snapshots, etc., making it well suited for data center environments.

[0040] The above products share some file systems as follows:

[0041] FAT32 and exFAT: These two file systems are commonly used on various types of removable storage devices, including USB flash drives and SSDs (when used as external drives) due to their wide compatibility. ext4: Although primarily used in Linux operating systems, it can be found on a variety of storage media, such as eMMC, UFS, and SSDs, particularly in Android devices and Linux servers. F2FS: Primarily used on eMMC and UFS storage on mobile devices to accommodate the characteristics and requirements of flash memory.

[0042] In one embodiment, the system data includes File Allocation Table (FAT) data. In the storage field, FAT data is considered part of the file system. When writing FAT data to the memory module 122, FAT data exhibits different characteristics than when writing user data. These differences are primarily reflected in the data distribution characteristics and the distribution requirements for "1" and "0".

[0043] FAT data is structured metadata used to record file allocation within the file system. Each FAT entry (typically 16 or 32 bits) indicates the location of the next cluster within a file's cluster, or indicates whether a cluster is unused. Unused clusters are typically marked with a specific value (such as all zeros), while clusters allocated to files contain the address pointing to the next cluster in the chain. This structured data typically exhibits a high degree of regularity, meaning the distribution of "1s" and "0s" within the FAT data follows a specific pattern. For example, unused cluster entries are all zeros, while entries pointing to other clusters display a mix of "1s" and "0s."

[0044] On the other hand, user data is typically unstructured and can be in any form, including text, images, and videos. The distribution of user data is typically random. Furthermore, to reduce the risk of bit-flip errors, user data is randomized before being written to memory module 122. For example, the data with the best randomization effect can be selected and written to memory module 122. Therefore, in user data, the state of each bit ("1" or "0") has no obvious regularity.

[0045] In one embodiment, for first data (such as, but not limited to, the aforementioned FAT data) having a structured feature (i.e., a predetermined bit value or bit sequence), the memory control circuit 23 may not encode the portion of the first data having the structured feature through the error correction circuit 25 before storing the first data in the memory module 122. Similarly, after reading the data (also referred to as the second data) having the structured feature from the memory module 122, the memory control circuit 23 may not decode the portion of the second data having the structured feature through the error correction circuit 25. That is, during the data access process, it is not necessary to encode and decode the portion of the data having the structured feature. As a result, the error correction capability of the error correction code for this portion of data can be reallocated, for example, to correct potential errors in the remaining portion of the same data that does not have the structured feature.

[0046] In one embodiment, for a FAT32 file system, taking an 8GB USB flash drive as an example, the maximum possible number of bytes occupied by its FAT data (i.e., the size of a single FAT data table) is calculated as follows:

[0047] The FAT data size of the FAT32 file system depends on the total number of clusters and the size of each FAT item. For FAT32, each FAT item occupies 4 bytes (32 bits) because FAT32 can manage larger disk spaces and more clusters.

[0048] To calculate the maximum capacity of FAT data on an 8GB USB drive, assume that the maximum volume size supported by FAT32 is 2TB. Cluster sizes in FAT32 typically range from 512 bytes to 32KB, depending on the total volume size. For an 8GB USB drive, a common cluster size is 4KB (4096 bytes). For an 8GB USB drive, assuming a 4KB (4096-byte) cluster size, the number of clusters can be calculated as follows:

[0049] (i.e. 2,097,152 clusters)

[0050] Furthermore, assuming that each FAT entry occupies 4 bytes, the size of the FAT data can be calculated as follows:

[0051] 2097152 × 4 (bytes) = 8388608 bytes = 8MB

[0052] Furthermore, the maximum possible value of the number of bytes occupied by FAT data (i.e., the size of a single FAT data) can be expressed in hexadecimal as follows:

[0053] 2×1024×1024 clusters = 0x0020000

[0054] Alternatively, it can be converted to binary representation as follows: 0000 0000 0010 0000 0000 0000 0000 0000

[0056] As described above, if a FAT data entry is represented in binary, the first 10 bits of the FAT data can be considered as data having the aforementioned structural characteristics (i.e., 10 consecutive zeros), while the remaining bits of the FAT data do not have the aforementioned structural characteristics. However, other types of management data may have corresponding and / or different structural characteristics, and the present invention is not limited thereto.

[0057] For example, in the exFAT file system, the aforementioned structured management data may include FAT data and cluster bitmap data. This FAT data is used to track cluster allocation status. Furthermore, the cluster bitmap data is used to record which clusters are in use and / or which clusters are free. Alternatively, in the ext4 file system, the aforementioned structured management data may include block bitmap data. Block bitmap data is used to track whether blocks on the disk are allocated. Alternatively, in the F2FS file system, the aforementioned structured management data may include management data for node segments and data segments, which is used to manage the allocation of metadata and user data. This mechanism helps improve read and write efficiency and reduce fragmentation. Alternatively, in the XFS file system, the aforementioned structured management data may include allocation group data, which contains metadata, such as space allocation data, providing a more flexible way to manage and restore file allocation information. Furthermore, many other types of management data may also have the aforementioned or similar structured features, which are not discussed here.

[0058] In one embodiment, after obtaining the first data, the memory control circuit 23 may detect the type of the first data. For example, the memory control circuit 23 may determine whether the first data is data with structured features (such as the one or more types of management data described above) or data without structured features (such as user data or firmware data).

[0059] In one embodiment, if the first data type is structured data, the memory control circuit 23 may further determine which type of management data the first data type belongs to among the one or more aforementioned types of management data. For example, the memory control circuit 23 may determine whether the first data type belongs to management data for various file systems, such as FAT32, exFAT, NTFS, ext4, F2FS, YAFFS, APFS, Btrfs, or ZFS. Furthermore, the types of structured data may be further specified or expanded based on practical needs, and the present invention is not limited thereto.

[0060] In one embodiment, after determining the type of the first data, the memory control circuit 23 may determine an encoding rule corresponding to the first data (also referred to as a first encoding rule) based on the type of the first data. For example, if the first data type has the aforementioned structural characteristics, the memory control circuit 23 may determine the first encoding rule as an encoding rule that supports dynamic adjustment of the encoding / decoding mechanism. Thereafter, for the first data having the aforementioned structural characteristics, the memory control circuit 23 may dynamically adjust the encoding / decoding mechanism corresponding to the first data based on the first encoding rule. The relevant operational details will be described in detail later.

[0061] However, if the first data does not have the aforementioned structural characteristics, the memory control circuit 23 may determine the first encoding rule as a conventional encoding rule. For example, for first data that does not have the aforementioned structural characteristics, the memory control circuit 23 may instruct the error correction circuit 25 to perform conventional encoding / decoding operations on the first data based on the conventional encoding rules. For example, this conventional encoding / decoding operation may include the error correction circuit 25 encoding the entire first data (i.e., all data in the first data) to obtain an error correction code corresponding to the first data. The error correction circuit 25 may then correct errors in the first data based on this error correction code.

[0062] In other words, in one embodiment, if the type of the first data is a certain type (also referred to as the first type), the memory control circuit 23 may determine a certain candidate encoding rule (also referred to as the first candidate encoding rule) as the first encoding rule. Alternatively, if the type of the first data is another type (also referred to as the second type), the memory control circuit 23 may determine another candidate encoding rule (also referred to as the second candidate encoding rule) as the first encoding rule. The first type is different from the second type, and the first candidate encoding rule is different from the second candidate encoding rule. In the following embodiment, the first encoding rule that supports the dynamic adjustment of the encoding / decoding mechanism is described in detail.

[0063] In one embodiment, after determining the first encoding rule, the memory control circuit 23 may encode a portion of the first data (also referred to as the first sub-data) through the error correction circuit 25 according to the first encoding rule to generate an error correction code corresponding to the first data (also referred to as the first error correction code). However, the memory control circuit 23 and the error correction circuit 25 may not encode another portion of the first data (also referred to as the second sub-data). Alternatively, from another perspective, the aforementioned operation of generating the first error correction code only involves encoding the first sub-data of the first data and does not involve encoding the second sub-data of the first data.

[0064] Figure 4is a schematic diagram showing encoding the first sub-data in the first data to generate a first error correction code according to an embodiment of the present invention. Figure 4 Assume that data 41 is the first data. Data 41 includes sub-data 411 (i.e., the second sub-data) and sub-data 412 (i.e., the first sub-data). According to the first encoding rule, memory control circuit 23 can encode sub-data 412 via error correction circuit 25 to generate error correction code 42 (i.e., the first error correction code). In particular, the generation of error correction code 42 does not involve encoding sub-data 411. It should be noted that the position or distribution of the first sub-data in the first data can be set or adjusted according to practical needs and is not limited by the present invention.

[0065] Figure 5 is a schematic diagram showing encoding the first sub-data in the first data to generate a first error correction code according to an embodiment of the present invention. Figure 5 Assume that data 51 is the first data. Data 51 includes sub-data 511 (i.e., the first sub-data) and sub-data 512 (i.e., the second sub-data). According to the first encoding rule, the memory control circuit 23 can encode sub-data 511 via the error correction circuit 25 to obtain an error correction code 52 (i.e., the first error correction code). In particular, the generation of error correction code 52 does not involve encoding sub-data 512. However, the first sub-data may be located elsewhere in the first data, such as in the middle or end of the first data, and the present invention is not limited thereto.

[0066] In one embodiment, after obtaining the first error correction code (eg Figure 4 Error correction code 42 or Figure 5 After the error correction code 52 in the memory module is generated, the memory control circuit 23 may store the first data (including the encoded first sub-data and the unencoded second sub-data) and the first error correction code in at least one physical unit (also referred to as the first physical unit) in the memory module 122.

[0067] For example, assuming the first physical unit is at least one physical page (also referred to as the first physical page) in the memory module 122, the memory control circuit 23 may store the first data (including the encoded first sub-data and the unencoded second sub-data) in the data area (also referred to as the data bit area) of the first physical page, and store the first error correction code in the idle area (also referred to as the redundant bit area) of the first physical page. That is, the first data (including the encoded first sub-data and the unencoded second sub-data) is stored in the data area (i.e., the data bit area) of the first physical page, while the first error correction code is stored in the idle area (i.e., the redundant bit area) of the first physical page. This completes the encoding and storage of the first data.

[0068] In one embodiment, the memory control circuit 23 may store the first data (including the encoded first sub-data and the unencoded second sub-data) in a data area (also referred to as a data bit area) of a first physical page, and store the first error correction code in a data area (also referred to as a data bit area) of a second physical page. The memory control circuit 23 may then encode the first error correction code via the error correction circuit 25 to generate a second error correction code, and store the second error correction code in an idle area (also referred to as a redundant bit area) of the second physical page. Specifically, the encoding rule by which the memory control circuit 23 encodes the first error correction code via the error correction circuit 25 to generate the second error correction code may be selected to apply the first encoding rule or the second encoding rule in the context of this application, and will not be further described herein.

[0069] In one embodiment, after determining the first encoding rule, the memory control circuit 23 may perform partial data extraction on the first data according to the first encoding rule to obtain first sub-data. The memory control circuit 23 may then encode the first sub-data via the error correction circuit 25 to generate a first error correction code.

[0070] In one embodiment, based on the first encoding rule, the memory control circuit 23 may further determine a mask (also referred to as a data filtering mask). This data filtering mask has a preset length corresponding to the first encoding rule. For example, the length of this data filtering mask (i.e., the preset length) may be determined based on the first encoding rule. For example, when the first encoding rule changes, the length of the determined data filtering mask may change accordingly. Based on this data filtering mask, the memory control circuit 23 may determine the first sub-data from the first data. The aforementioned preset length may be 1KB, 2KB, 4KB, 8KB, or 16KB, etc., and the present invention is not limited thereto.

[0071] In one embodiment, if the first encoding rule is a candidate encoding rule (e.g., the first candidate encoding rule), the memory control circuit 23 may determine a data filtering mask (also referred to as the first data filtering mask) as the data filtering mask. Alternatively, if the first encoding rule is another candidate encoding rule (e.g., the second candidate encoding rule), the memory control circuit 23 may determine another data filtering mask (also referred to as the second data filtering mask) as the data filtering mask. The first data filtering mask may be different from the second data filtering mask. For example, the length of the first data filtering mask (also referred to as the first preset length) may be different from the length of the second data filtering mask (also referred to as the second preset length).

[0072] In one embodiment, after determining the data filtering mask, the memory control circuit 23 may align the data filtering mask with the first data according to an alignment rule. For example, this alignment rule may be determined based on the first encoding rule. For example, when the first encoding rule changes, this alignment rule may change accordingly. For example, when the first encoding rule is a candidate encoding rule (such as the first candidate encoding rule), the memory control circuit 23 may determine a candidate alignment rule (also referred to as the first candidate alignment rule) as this alignment rule. Alternatively, when the first encoding rule is another candidate encoding rule (such as the second candidate encoding rule), the memory control circuit 23 may determine another candidate alignment rule (also referred to as the second candidate alignment rule) as this alignment rule. The first candidate alignment rule may be different from the second candidate alignment rule.

[0073] In one embodiment, after aligning the data filter mask with the first data, the memory control circuit 23 may extract at least one bit (also referred to as the first bit) from the first data as the first sub-data based on the length of the data filter mask. In one embodiment, the first bit may refer to any bit in the first data that is within the overlapping range of the data filter mask and the first data after the data filter mask and the first data are aligned. Alternatively, in one embodiment, the first bit may refer to any bit in the first data that is outside the overlapping range of the data filter mask and the first data after the data filter mask and the first data are aligned.

[0074] Figure 6 FIG2 is a schematic diagram illustrating determining first sub-data from first data based on a data filter mask according to an embodiment of the present invention. Referring to the figure, assume that data 61 is the first data. Based on data filter mask 601, memory control circuit 23 can determine sub-data 611 and 612 from data 61.

[0075] In one embodiment, the memory control circuit 23 may determine the sub-data 611 as the first sub-data and the data 612 as the second sub-data. Alternatively, in one embodiment, the memory control circuit 23 may determine the sub-data 612 as the first sub-data and the data 611 as the second sub-data.

[0076] In one embodiment, it is assumed that the alignment rule adopted is that the data filter mask is aligned with the first bit of the first data. According to this alignment rule, the memory control circuit 23 can align the data filter mask 601 with the first bit of the data 61, such as Figure 6After aligning the data filter mask 601 with the data 61, the memory control circuit 23 can determine a critical point (also called a first critical point) 602 and a critical point (also called a second critical point) 603 based on the overlap range between the data filter mask 601 and the data 61. The overlap range between the data filter mask 601 and the data 61 is between the critical points 602 and 603.

[0077] In one embodiment, the memory control circuit 23 may determine the data (i.e., sub-data 611) between the critical points 602 and 603 in the data 61 as the first sub-data. For example, the memory control circuit 23 may extract each bit (i.e., the first bit) from the sub-data 611 as the first sub-data. At the same time, the memory control circuit 23 may determine the data (i.e., sub-data 612) not between the critical points 602 and 603 in the data 61 as the second sub-data. Figure 5 In the embodiment, sub-data 611 may be encoded to generate an error correction code corresponding to data 61 (ie, a first error correction code), and sub-data 612 is not used to generate an error correction code corresponding to data 61 (ie, a first error correction code).

[0078] Alternatively, in one embodiment, the memory control circuit 23 may determine the data (i.e., sub-data 612) in the data 61 that is not between the critical points 602 and 603 as the first sub-data. For example, the memory control circuit 23 may extract each bit (i.e., the first bit) from the sub-data 612 as the first sub-data. At the same time, the memory control circuit 23 may determine the data (i.e., sub-data 611) in the data 61 that is between the critical points 602 and 603 as the second sub-data. Thereafter, similar to Figure 4 In the embodiment, the sub-data 612 may be encoded to generate an error correction code corresponding to the data 61 (ie, the first error correction code), and the sub-data 611 is not used to generate an error correction code corresponding to the data 61 (ie, the first error correction code).

[0079] In one embodiment, the second sub-data in the first data includes at least one bit (also referred to as the second bit). The second bit is not involved in the aforementioned encoding of the first sub-data to generate the first error correction code. In particular, the second bit (or second sub-data) has a preset data form corresponding to the determined first encoding rule. For example, this preset data form may be at least one bit "0" and / or at least one bit "1" arranged according to a preset arrangement rule. This preset data form may be determined based on the first encoding rule. For example, when the first encoding rule changes, the preset data form may change accordingly. For example, when the first encoding rule is a candidate encoding rule (e.g., the first candidate encoding rule), the memory control circuit 23 may determine a candidate data form (also referred to as the first candidate data form) as the preset data form. Alternatively, when the first encoding rule is another candidate encoding rule (e.g., the second candidate encoding rule), the memory control circuit 23 may determine another candidate data form (also referred to as the second candidate data form) as the preset data form. The first candidate data form may be different from the second candidate data form.

[0080] In one embodiment, after storing the first data (including the encoded first sub-data and the unencoded second sub-data) and the first error correction code in the memory module 122 (e.g., the first physical unit), the memory control circuit 23 may read the first data and the first error correction code from the first physical unit. For example, the first data (including the encoded first sub-data and the unencoded second sub-data) may be read from the data area (i.e., the data bit area) of the first physical page, while the first error correction code may be read from the idle area (i.e., the redundant bit area) of the first physical page.

[0081] It should be noted that to avoid confusion in terminology and description between the first data previously written and the first data subsequently read, in the following embodiments, the first data read from the first physical unit will be referred to as the second data. That is, the length of the second data and the storage location of the second data in the memory module 122 (i.e., the first physical unit) are respectively identical to the length of the first data and the storage location of the first data in the memory module 122 (i.e., the first physical unit). Furthermore, any discrepancy in data content between the first data and the second data can be considered to be caused by a read error (or read error) generated when reading data from the first physical unit. After obtaining the second data, the error correction circuit 25 can correct the error in the second data based on the first error correction code.

[0082] In one embodiment, after reading the second data and the first error correction code from the first physical unit, the memory control circuit 23 may query an encoding rule corresponding to the second data (also referred to as a second encoding rule). For example, the second encoding rule is the same as the first encoding rule previously used when storing the first data.

[0083] In one embodiment, the memory control circuit 23 may record the encoding rules corresponding to at least part of the data in a management table. Thereafter, the memory control circuit 23 may query the management table to obtain the encoding rules corresponding to each data (including the second encoding rule).

[0084] In one embodiment, after determining the second encoding rule (i.e., the aforementioned first encoding rule), the memory control circuit 23 may determine a portion of the data (also referred to as the third sub-data) from the second data based on this second encoding rule. For example, the distribution position of the third sub-data in the second data may be the same as the distribution position of the first sub-data in the first data. The memory control circuit 23 may then instruct the error correction circuit 25 to decode the third sub-data based on the first error correction code to correct errors in the third sub-data. However, it should be noted that this first error correction code will not be used to decode the remaining data (also referred to as the fourth sub-data) in the second data. For example, the distribution position of the fourth sub-data in the second data may be the same as the distribution position of the second sub-data in the first data.

[0085] In one embodiment, after determining the second encoding rule (i.e., the aforementioned first encoding rule), the memory control circuit 23 may determine a predetermined data form corresponding to the fourth sub-data based on the second encoding rule. For example, the predetermined data form corresponding to the fourth sub-data may be the same as the predetermined data form corresponding to the second sub-data. Then, without decoding the fourth sub-data based on the first error correction code, the memory control circuit 23 may correct errors in the fourth sub-data based on the determined predetermined data form.

[0086] In one embodiment, if the second encoding rule is a candidate encoding rule (e.g., the first candidate encoding rule), the memory control circuit 23 may determine a candidate data form (e.g., the first candidate data form) as the preset data form. Alternatively, if the second encoding rule is another candidate encoding rule (e.g., the second candidate encoding rule), the memory control circuit 23 may determine another candidate data form (e.g., the second candidate data form) as the preset data form. For example, the distribution state of bits "0" and / or "1" reflected or presented by the first candidate data form may be different from the distribution state of bits "0" and / or "1" reflected or presented by the second candidate data form.

[0087] Figure 7 is a schematic diagram showing how to correct the second data based on the first error correction code according to an embodiment of the present invention. Figure 7, assuming that data 71 is the second data and error correction code 72 is the first error correction code. Data 71 includes sub-data 711 and 712. Error correction code 72 can be considered to be generated by encoding sub-data 712. Furthermore, generation of error correction code 72 can be considered to not involve encoding sub-data 711.

[0088] In one embodiment, after obtaining the data 71 and the error correction code 72, the memory control circuit 23 may instruct the error correction circuit 25 to decode the sub-data 712 based on the error correction code 72 to correct errors in the sub-data 712. It should be noted that during the decoding operation of the sub-data 712 by the error correction circuit 25 based on the error correction code 72, the error correction code 72 is not used to decode the sub-data 711.

[0089] On the other hand, after determining the encoding rule corresponding to data 71 (i.e., the second encoding rule), the memory control circuit 23 may determine a predetermined data form 73 corresponding to sub-data 711 based on this encoding rule. After determining the predetermined data form 73, the memory control circuit 23 may compare the bit distribution of sub-data 711 with the predetermined data form 73 to obtain a comparison result. This comparison result may indicate a difference between the bit distribution of sub-data 711 and the predetermined data form 73. In particular, this difference may be considered to be caused by a read error (i.e., an erroneous bit) in sub-data 711. Therefore, the memory control circuit 23 may correct the error in sub-data 711 based on this comparison result. For example, based on this comparison result, the memory control circuit 23 may update the bit value distribution of all bits in sub-data 711 to be consistent with (i.e., identical to) the predetermined data form 73.

[0090] It should be noted that compared to using error correction codes to correct a complete data (such as Figure 7 The data in 71) is decoded and Figure 7 In this embodiment, sub-data 712 is decoded based on error correction code 72 and errors in sub-data 711 are corrected by comparing sub-data 711 with predetermined data pattern 73. This can speed up error correction (or error detection) of data 71, thereby speeding up the reading of data 71. Furthermore, by reducing the amount of data that needs to be protected (or checked) by an error correction code from the larger amount of data 71 to sub-data 712 (or 711), the error correction capability of the error correction circuit 25 can be effectively improved.

[0091] Figure 8 FIG is a flow chart of a memory control method according to an embodiment of the present invention. Figure 8In step S801, first data is obtained. In step S802, the type of the first data is detected. In step S803, a first encoding rule corresponding to the first data is determined based on the type. In step S804, first sub-data in the first data is encoded according to the first encoding rule to generate a first error correction code corresponding to the first data, and second sub-data in the first data is not encoded. After obtaining the first error correction code, in step S805, the first data and the first error correction code are stored in at least one first physical unit of the memory module.

[0092] On the other hand, after the first data and the first error correction code are stored in the memory module (i.e., the first physical unit), in step S806, the second data and the first error correction code are read from the first physical unit. In step S807, errors in the second data are corrected based on the first error correction code.

[0093] However, Figure 8 The steps have been described in detail above and will not be repeated here. Figure 8 Each step can be implemented as multiple program codes or circuits, and the present invention is not limited thereto. Figure 8 The method can be used in conjunction with the above exemplary embodiments or can be used alone, and the present invention is not limited thereto.

[0094] In summary, the memory control method and storage device proposed in the embodiments of the present invention can effectively improve the data reading speed for certain special types of data by significantly reducing the amount of data that needs to be decoded to perform error correction, without affecting (or even improving) the data protection capability (and / or error correction capability) of the storage device.

[0095] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the above embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A memory control method, characterized in that: For use in a storage device, wherein the storage device includes a memory module, and the memory control method includes: Obtaining first data; detecting a type of the first data; determining, according to the type, a first encoding rule corresponding to the first data; encoding the first sub-data in the first data according to the first encoding rule to generate a first error correction code corresponding to the first data, and not encoding the second sub-data in the first data; After obtaining the first error correction code, storing the first data and the first error correction code in at least one first physical unit in the memory module; After storing the first data and the first error correction code in the at least one first physical unit, reading second data and the first error correction code from the at least one first physical unit; and Errors in the second data are corrected based on the first error correction code.

2. The memory control method according to claim 1 , wherein the step of determining the first encoding rule corresponding to the first data according to the type comprises: If the type is the first type, determining the first candidate encoding rule as the first encoding rule; as well as If the type is the second type, the second candidate encoding rule is determined to be the first encoding rule, wherein the first candidate encoding rule is different from the second candidate encoding rule.

3. The memory control method according to claim 1 , wherein the step of encoding the first sub-data in the first data according to the first encoding rule comprises: According to the first encoding rule, partial data extraction is performed on the first data to obtain the first sub-data.

4. The memory control method according to claim 3 , wherein the step of performing the partial data extraction on the first data according to the first encoding rule to obtain the first sub-data comprises: Determining a data screening mask according to the first encoding rule; as well as The first sub-data is determined from the first data according to the data screening mask.

5. The memory control method according to claim 4 , wherein the step of determining the data filtering mask according to the first encoding rule comprises: If the first encoding rule is the first candidate encoding rule, determining the first candidate data screening mask as the data screening mask; as well as If the first encoding rule is a second candidate encoding rule, a second candidate data screening mask is determined as the data screening mask, wherein the first candidate data screening mask is different from the second candidate data screening mask.

6. The memory control method according to claim 4 , wherein the step of determining the first sub-data from the first data according to the data screening mask comprises: aligning the data screening mask with the first data according to an alignment rule; as well as After aligning the data screening mask with the first data, at least one first bit is extracted from the first data as the first sub-data according to the length of the data screening mask. 7 . The memory control method according to claim 1 , wherein the second sub-data comprises at least one second bit, and the at least one second bit has a preset data form corresponding to the first encoding rule.

8. The memory control method according to claim 1 , wherein the step of correcting the error in the second data based on the first error correction code comprises: Querying a second encoding rule corresponding to the second data; determining third sub-data from the second data according to the second encoding rule; as well as The third sub-data is decoded based on the first error correction code to correct errors in the third sub-data, and the first error correction code is not used to decode the fourth sub-data in the second data.

9. The memory control method according to claim 8, wherein the step of correcting the error in the second data based on the first error correction code further comprises: determining, according to the second encoding rule, a preset data form corresponding to the fourth sub-data; as well as Based on the preset data form, errors in the fourth sub-data are corrected.

10. The memory control method according to claim 9, wherein the step of determining the preset data form corresponding to the fourth sub-data according to the second encoding rule comprises: If the second encoding rule is the first candidate encoding rule, determining the first candidate data form as the preset data form; as well as If the second encoding rule is the second candidate encoding rule, the second candidate data form is determined as the preset data form, wherein the first candidate data form is different from the second candidate data form.

11. A storage device, characterized in that: include: A connection interface for connecting to a host system; Memory module; as well as a memory controller connected to the connection interface and the memory module, The memory controller is configured to: Obtaining first data; detecting a type of the first data; determining, according to the type, a first encoding rule corresponding to the first data; encoding the first sub-data in the first data according to the first encoding rule to generate a first error correction code corresponding to the first data, and not encoding the second sub-data in the first data; After obtaining the first error correction code, storing the first data and the first error correction code in at least one first physical unit in the memory module; After storing the first data and the first error correction code in the at least one first physical unit, reading second data and the first error correction code from the at least one first physical unit; as well as Errors in the second data are corrected based on the first error correction code.

12. The storage device according to claim 11, wherein the operation of determining the first encoding rule corresponding to the first data according to the type comprises: If the type is the first type, determining the first candidate encoding rule as the first encoding rule; as well as If the type is the second type, the second candidate encoding rule is determined to be the first encoding rule, wherein the first candidate encoding rule is different from the second candidate encoding rule.

13. The storage device according to claim 11 , wherein the operation of encoding the first sub-data in the first data according to the first encoding rule comprises: According to the first encoding rule, partial data extraction is performed on the first data to obtain the first sub-data.

14. The storage device according to claim 13, wherein the operation of performing the partial data extraction on the first data according to the first encoding rule to obtain the first sub-data comprises: Determining a data screening mask according to the first encoding rule; as well as The first sub-data is determined from the first data according to the data screening mask.

15. The storage device according to claim 14, wherein the operation of determining the data screening mask according to the first encoding rule comprises: If the first encoding rule is the first candidate encoding rule, determining the first candidate data screening mask as the data screening mask; as well as If the first encoding rule is a second candidate encoding rule, a second candidate data screening mask is determined as the data screening mask, wherein the first candidate data screening mask is different from the second candidate data screening mask.

16. The storage device according to claim 14, wherein the operation of determining the first sub-data from the first data according to the data screening mask comprises: aligning the data screening mask with the first data according to an alignment rule; as well as After aligning the data screening mask with the first data, at least one first bit is extracted from the first data as the first sub-data according to the length of the data screening mask. 17 . The storage device according to claim 11 , wherein the second sub-data comprises at least one second bit, and the at least one second bit has a preset data form corresponding to the first encoding rule.

18. The storage device of claim 11 , wherein correcting the error in the second data based on the first error correction code comprises: Querying a second encoding rule corresponding to the second data; determining third sub-data from the second data according to the second encoding rule; as well as The third sub-data is decoded based on the first error correction code to correct errors in the third sub-data, and the first error correction code is not used to decode the fourth sub-data in the second data.

19. The storage device according to claim 18, wherein the operation of correcting the error in the second data based on the first error correction code further comprises: determining, according to the second encoding rule, a preset data form corresponding to the fourth sub-data; as well as Based on the preset data form, errors in the fourth sub-data are corrected.

20. The storage device according to claim 19, wherein the operation of determining the preset data form corresponding to the fourth sub-data according to the second encoding rule comprises: If the second encoding rule is the first candidate encoding rule, determining the first candidate data form as the preset data form; as well as If the second encoding rule is the second candidate encoding rule, the second candidate data form is determined as the preset data form, wherein the first candidate data form is different from the second candidate data form.

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