Wafer-level and board-level combined packaging method and packaging structure

Abstract

The invention provides a wafer-level and board-level combined packaging method and packaging structure, and the method comprises the steps: A1, enabling the front surface of a whole wafer to face upwards, and forming a conductive connection layer on the front surface of the wafer; a2, the back face of the wafer is temporarily attached to a supporting carrier plate; a3, performing plastic package on the front surface and the side surface of the wafer to form a first protection layer; step A4, removing the supporting carrier plate; a5, grinding the first protection layer on the front surface of the wafer to expose the top surface of the conductive connection layer; and A6, cutting the wafer to form a single packaging structure. According to the invention, a structure and a process of combining wafer-level packaging and board-level packaging are adopted, a packaging process which is easy to implement and can be standardized is formed, the problem that the side surface of the wafer-level packaging is exposed and the alignment precision of the board-level packaging is low is solved, the packaging efficiency is improved, and the product cost is reduced.

Description

Technical Field

[0001] The present invention relates to the field of wafer packaging technology, and in particular to a wafer-level and board-level combined packaging method and packaging structure. Background Art

[0002] CSP (Chip Scale Package) is an advanced surface-mount integrated circuit packaging technology, with a package size close to the size of the chip itself. Compared to traditional packages, CSP has shorter interconnect distances, reducing parasitic resistance and inductance, improving chip performance and integration. At the same time, the package occupies less space, meeting the demands for lightweight, high-frequency, and high-reliability. It is widely used in mobile devices, consumer electronics, automotive electronics, and other fields.

[0003] CSP typically uses two packaging methods. Wafer-level packaging (WLP) technology completes the entire packaging process directly on the wafer, eliminating the substrate and lead frame required for traditional packaging. Internal and external connections are achieved through redistribution layers (RDLs) and solder bumps. Currently, most packaged units using this technology lack protective layers on their sides, failing to prevent anomalies caused by exposed sides and posing certain reliability risks. Panel-level packaging (PLP) technology uses large-area panels, replacing circular wafers as processing substrates, for large-scale production. While this technology offers high production efficiency and low cost, it involves multiple photolithography, electroplating, and molding processes, and suffers from poor exposure at the edges of large panels, leading to challenges such as substrate warpage, low alignment accuracy, and poor process uniformity. Summary of the Invention

[0004] Based on the above content, the present invention provides a wafer-level and board-level combined packaging method and packaging structure, aiming to solve the technical problems in the prior art such as the exposed side of the wafer-level packaging and the low alignment accuracy of the board-level packaging.

[0005] A wafer-level and board-level combined packaging method, comprising:

[0006] Step A1: Place the entire wafer with its front side facing upwards and form a conductive connection layer on the front side of the wafer;

[0007] Step A2, temporarily attaching the back side of the wafer to the support plate;

[0008] Step A3, performing plastic sealing on the front and side surfaces of the wafer to form a first protective layer;

[0009] Step A4, removing the supporting carrier;

[0010] Step A5, grinding the first protective layer on the front side of the wafer to expose the top surface of the conductive connection layer;

[0011] Step A6: cutting the wafer into individual package structures.

[0012] Furthermore, step A1 includes:

[0013] Step A11, placing the entire wafer with its front side facing upward and exposing the dielectric layer and metal pads on the front side;

[0014] Step A12, forming a third protective layer on the front surface of the wafer, and opening a window in the third protective layer to expose the metal pad;

[0015] Step A13: forming a conductive connection layer on the metal pad, wherein a top surface of the conductive connection layer protrudes from an upper surface of the third protective layer.

[0016] Furthermore, after step A1 and before step A2, the following steps are performed:

[0017] Step B1, thinning the back side of the wafer to a first predetermined thickness.

[0018] Furthermore, in step A12, a window is opened in the third protective layer to expose the cutting street;

[0019] After step A2 and before step A3, also execute:

[0020] Step B2, pre-cutting the cutting path to form a groove;

[0021] In step A6, full cutting is performed along the cutting streets to form individual package structures.

[0022] Furthermore, after step A4 and before step A5, the method further includes:

[0023] Step B3: thinning the back side of the wafer to a second predetermined thickness and exposing the first protective layer in the groove.

[0024] Furthermore, after step A5 and before step A6, the method further includes:

[0025] Step B4: plating a soldering metal layer on the top surface of the conductive connection layer.

[0026] Furthermore, after step A4 and before step A5, the following steps are further included:

[0027] Step B5: Plastic-sealing the back side of the wafer to form a second protective layer.

[0028] Furthermore, the conductive connection layer is a copper pillar or a stacked structure of a lower copper layer and an upper copper layer;

[0029] When the conductive connection layer is a stacked structure of a lower copper layer and an upper copper layer, the lower copper layer is within the window of the third protective layer and the upper surface of the lower copper layer is flush with the upper surface of the third protective layer, the upper copper layer covers the upper surface of the lower copper layer and part of the upper surface of the third protective layer, and the thickness of the lower copper layer is greater than the thickness of the upper copper layer.

[0030] A packaging structure formed using the aforementioned wafer-level and board-level combined packaging method includes a chip, the front surface of the chip includes a dielectric layer and a metal pad, a third protective layer is provided on the dielectric layer, and a conductive connection layer is provided on the metal pad;

[0031] The side and front of the chip are sealed to form a first protective layer;

[0032] The top surface of the conductive connection layer protrudes from the upper surface of the third protection layer, and the top surface of the conductive connection layer exposes the upper surface of the first protection layer.

[0033] Furthermore, the conductive connection layer is a copper pillar or a stacked structure of a lower copper layer and an upper copper layer;

[0034] When the conductive connection layer is a stacked structure of a lower copper layer and an upper copper layer, the lower copper layer is within the window of the third protective layer and the upper surface of the lower copper layer is flush with the upper surface of the third protective layer, the upper copper layer covers the upper surface of the lower copper layer and part of the upper surface of the third protective layer, and the thickness of the lower copper layer is greater than the thickness of the upper copper layer.

[0035] The beneficial technical effect of the present invention is that the present invention adopts a structure and process that combines wafer-level packaging and board-level packaging to form an easy-to-implement and standardized packaging process, solving the problem of exposed sides of wafer-level packaging and low alignment accuracy of board-level packaging, improving packaging efficiency and reducing product costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Figure 1-2 A flowchart of the steps of a wafer-level and board-level combined packaging method of the present invention;

[0037] Figure 3 A flowchart of a specific embodiment of a wafer-level and board-level combined packaging method of the present invention;

[0038] Figure 4 A schematic diagram of a packaging structure with back plastic sealing is provided in a specific embodiment of the present invention;

[0039] Figure 5 This is a schematic structural diagram of forming a third protective layer on the front side of a wafer in a wafer-level and board-level combined packaging method of the present invention;

[0040] Figure 6 This is a schematic structural diagram of forming a conductive connection layer on the front side of a wafer in a wafer-level and board-level combined packaging method of the present invention;

[0041] Figure 7 This is a schematic structural diagram of a wafer-level and board-level combined packaging method of the present invention for one-time thinning on the back side of the wafer;

[0042] Figure 8 This is a schematic structural diagram of a wafer-level and board-level combined packaging method according to the present invention, wherein the back side of the wafer is adhered to a supporting carrier;

[0043] Figure 9 This is a schematic structural diagram of pre-cutting on the front side of a wafer in a wafer-level and panel-level combined packaging method of the present invention;

[0044] Figure 10 This is a schematic structural diagram of plastic sealing on the front side of a wafer in a wafer-level and board-level combined packaging method of the present invention;

[0045] Figure 11 A schematic diagram of the structure of a wafer-level and board-level combined packaging method of the present invention, wherein the supporting carrier is removed from the back side of the wafer and then the wafer is thinned twice;

[0046] Figure 12 This is a schematic structural diagram of plastic sealing on the back side of a wafer in a wafer-level and board-level combined packaging method of the present invention;

[0047] Figure 13 This is a schematic structural diagram of wafer front surface grinding in a wafer-level and board-level combined packaging method of the present invention;

[0048] Figure 14 The present invention provides a wafer-level and board-level combined packaging method, wherein a soldering metal layer is plated on the surface of the conductive layer on the front side of the wafer;

[0049] Figure 15 A schematic structural diagram of full cutting along the cutting lanes in a wafer-level and board-level combined packaging method of the present invention;

[0050] Figure 16 This is a schematic structural diagram of another specific embodiment of a packaging structure of the present invention without back plastic sealing;

[0051] Figure 17 A schematic structural diagram of a double-layer stacked conductive connection layer in another specific embodiment of a packaging structure of the present invention;

[0052] in,

[0053] 1-chip; 2-dielectric layer; 3-metal pad; 4-conductive connection layer; 4a-lower copper layer; 4b-upper copper layer; 5-third protective layer; 5a-first dielectric layer; 5b-second dielectric layer; 6-first protective layer; 7-second protective layer; 8-tin layer or tin-gold layer; 9-cutting line; 10-support carrier board; DETAILED DESCRIPTION

[0054] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making any creative efforts shall fall within the scope of protection of the present invention.

[0055] It should be noted that, in the absence of conflict, the embodiments of the present invention and the features in the embodiments may be combined with each other.

[0056] The present invention will be further described below with reference to the accompanying drawings and specific embodiments, but they are not intended to limit the present invention.

[0057] See also Figure 1 The present invention provides a wafer-level and board-level combined packaging method, comprising:

[0058] Step A1, placing the front side of the entire wafer upward, and forming a conductive connection layer (4) on the front side of the wafer;

[0059] Step A2, temporarily attaching the back side of the wafer to the supporting carrier (10);

[0060] Step A3, performing plastic sealing on the front and side surfaces of the wafer to form a first protective layer (6);

[0061] Step A4, removing the support plate (10);

[0062] Step A5, grinding the first protective layer (6) on the front side of the wafer to expose the top surface of the conductive connection layer (4);

[0063] Step A6: cutting the wafer into individual package structures (DIE).

[0064] The present invention adopts a structure and process that combines wafer-level packaging with board-level packaging to form an easy-to-implement and standardized packaging process, solving the problem of exposed side surfaces of wafer-level packaging and low alignment accuracy of board-level packaging, improving packaging efficiency and reducing product costs.

[0065] like Figure 10 As shown, in step A3, the front and side molding of the wafer is performed by injecting epoxy molding compound (EMC) on the front and side of the wafer through compression molding or lamination film, and the first protective layer is formed after curing.

[0066] like Figure 13As shown, in step A5, frontside grinding is performed to grind the front mold layer and remove part of the conductive connection layer to make the package structure surface smooth. The thickness of the total package structure is controlled to 100-300 μm. A precision grinder is used to avoid damaging the conductive connection layer structure. Preferably, the remaining height of the conductive connection layer is 20-60 μm.

[0067] See also Figure 2 , further, step A1 includes:

[0068] Step A11, placing the entire wafer with its front side facing upward and exposing the dielectric layer (2) and the metal pad (3) on the front side;

[0069] Step A12, forming a third protective layer (5) on the front side of the wafer, and opening a window in the third protective layer (5) to expose the metal pad (3);

[0070] Step A13: forming a conductive connection layer (4) on the metal pad (3), wherein the top surface of the conductive connection layer (4) protrudes from the upper surface of the third protective layer (5).

[0071] like Figure 5 As shown, in step A12, a third protective layer (5) is formed on the front side of the wafer. Furthermore, the third protective layer (5) is a dielectric layer. Specifically, the dielectric layer is made of a polyimide film (Polymide). The Polymide layer serves as a dielectric protective layer to prevent mechanical damage and chemical corrosion in subsequent processes while achieving electrical insulation performance. When the third protective layer (5) is a dielectric layer, the dielectric layer is formed by physical vapor deposition (PVD) or spin coating. Preferably, the thickness is 5-20um. Figure 5 As shown, when the third protective layer (5) is a dielectric layer, after the dielectric layer is formed, the dielectric layer is then opened by photolithography (Lithography) or reactive ion etching (RIE) to expose the metal pad (3) underneath, and when a cutting path exists, the cutting path (9) is also exposed.

[0072] like Figure 6As shown, in step A13, a seed layer is first sputtered on the surface of the third protective layer (5) above the entire wafer, for example, a titanium copper (TiCu) layer or a chromium copper (CrCu) double-layer seed layer, with a thickness of about 0.1 to 0.5 μm. The seed layer enhances the adhesion between the subsequent conductive connection layer (4) and the metal pad (3) material; the conductive connection layer (4) serves as the actual conductive layer, and the seed layer ensures that the current can be evenly distributed over the entire surface when the conductive connection layer (4) is electroplated, thereby ensuring the consistency and uniformity of the growth of the conductive connection layer (4). The seed layer can also enhance the mechanical connection strength between the conductive connection layer (4) and the metal pad (3) material, which is crucial for the long-term reliability and stability of the packaging structure.

[0073] Furthermore, after step A1 and before step A2, the following steps are performed:

[0074] Step B1, thinning the back side of the wafer to a first predetermined thickness.

[0075] like Figure 7 As shown, the back side of the wafer is ground (Back Grinding), and the back side of the wafer is thinned to a first predetermined thickness by mechanical grinding (Mechanical Grinding). Preferably, the first predetermined thickness is 300-500um, so as to reduce the amount of grinding in the subsequent board-level grinding process after the wafer is loaded.

[0076] like Figure 8 As shown, after grinding, a support carrier (10) is attached.

[0077] Furthermore, in step A12, a window is opened in the third protective layer (5) to expose the cutting path (9);

[0078] After step A2 and before step A3, also execute:

[0079] Step B2, pre-cutting the cutting path (9) to form a groove;

[0080] In step A6, full cutting is performed along the cutting streets (9) to form individual package structures (DIE).

[0081] like Figure 5 As shown, when the third protective layer (5) is a dielectric layer, a window is opened in the dielectric layer after the dielectric layer is formed, exposing the metal pad (3) below while also exposing the cutting path (9) through the window.

[0082] like Figure 9As shown, in step B2, the wafer is pre-cut (Partial Dicing) by mechanical cutting on the scribe line. Preferably, the width of the groove is 40-80um, and the depth of the groove is 100-300um (not exceeding the remaining thickness of the wafer) to reduce the mechanical stress during subsequent full cutting and avoid chip edge cracking.

[0083] After the grooves are formed, in step A3, the front and side molding on the wafer only extends to the depth of the grooves.

[0084] like Figure 15 As shown, in step A6, dicing (singulation) uses laser cutting or blade cutting, and full dicing (full dicing) is performed along the pre-cut grooves to separate the individual package structures (DIE). The cutting width is 20-50μm, ensuring that the cut edges are free of burrs. At this point, the package is formed into a single unit, which is then tested, printed, and taped before shipment.

[0085] Furthermore, after step A4 and before step A5, the method further includes:

[0086] Step B3, thinning the back side of the wafer to a second predetermined thickness and exposing the first protective layer (6) in the groove.

[0087] like Figure 11 As shown, after removing the support plate (10), the back side of the wafer is ground and thinned to a second predetermined thickness of 60-260 μm, exposing the first protective layer (6) in the groove, thereby separating adjacent chips. For silicon products with a thickness of less than 100 μm, polishing can be performed after grinding to reduce mechanical grinding damage to the back silicon.

[0088] like Figure 14 As shown, further, after step A5 and before step A6, the method further includes:

[0089] Step B4: plating a soldering metal layer (8) on the top surface of the conductive connection layer (4). The soldering metal layer (8) is, for example, a tin layer or a tin-gold layer.

[0090] In step B4, a soldering metal layer (8) is plated on the front side of the wafer by a chemical plating process, such as electroless Sn plating or electroless NiAu plating. Tin (Sn) or nickel gold (NiAu) is deposited on the top of the conductive connection layer by the chemical plating process. The thickness of the soldering metal layer (8) is 1-10 μm. The soldering metal layer (8) can improve soldering reliability and ensure wettability with the PCB pad.

[0091] Specifically, the dielectric layer (2) is usually removed at the cutting path (9) by photolithography and etching processes, so that the plane at the cutting path (9) is lower than the plane at the non-cutting path (9), and the step formed by the height difference of the plane becomes the cutting path (9).

[0092] See also Figure 12 Furthermore, after step A4 and before step A5, the method further includes:

[0093] Step B5: Plastic-sealing the back side of the wafer to form a second protective layer (7).

[0094] This step is backside molding, where a second protective layer is coated or molded on the back of the wafer. The backside molding and frontside molding can be made of the same or different materials. Specifically, the first and second protective layers are made of the same or different materials, preferably the same material, with a thickness of 50-150 μm. This fully encapsulates the chip, providing comprehensive environmental protection (from moisture and ion contamination) and balancing packaging stress. After forming the second protective layer in step B5, the backside can be ground again to the target thickness.

[0095] Furthermore, the conductive connection layer (4) is a copper pillar or a stacked structure of a lower copper layer (4a) and an upper copper layer (4b);

[0096] When the conductive connection layer is a stacked structure of a lower copper layer (4a) and an upper copper layer (4b), the lower copper layer (4a) is within the window of the third protective layer (5), and the upper surface of the lower copper layer (4a) is flush with the upper surface of the third protective layer (5); the upper copper layer (4b) covers the upper surface of the lower copper layer (4a) and part of the upper surface of the third protective layer (5); and the thickness of the lower copper layer (4a) is greater than the thickness of the upper copper layer (4b).

[0097] When the conductive connection layer (4) is a copper pillar, in step A13, after forming the seed layer, the electroplating mask is defined by photolithography, and copper pillars are formed on the wafer surface by electrochemical deposition. The copper pillars are preferably 50-100 μm in height. After removing the mask, the residual seed layer is etched. The electroplating copper pillar process can accurately control the thickness and shape of the copper pillars, achieving pin requirements of various shapes and sizes, and has high flexibility. The copper pillars formed in this step are the final pin morphology of the product, and their specific size can be defined according to the lead appearance of the target product.

[0098] As an implementation method, Figure 17As shown, when the conductive connection layer (4) is a stacked structure of a lower copper layer (4a) and an upper copper layer (4b), that is, two layers of copper wiring are used on the front of the chip. The first layer, i.e., the lower copper layer, has a certain height, but its area is much smaller than the exposed lead of the target package. This lower copper layer is only located above the metal pad with a window of the third protective layer (5), and serves as an interconnection layer to connect the metal pad to the second upper copper layer. The size of the second upper copper layer is designed according to the pin size of the package. In this case, the third protective layer is thicker. The third protective layer can be formed by a single dielectric layer, or by a second dielectric layer (5b) and a first dielectric layer (5a) stacked together, with the first dielectric layer and the second dielectric layer being formed of different materials. The two-layer copper wiring design effectively reduces the parasitic capacitance between the large-area lead and the wafer surface, making it suitable for product packaging with high capacitance requirements.

[0099] Furthermore, in step A2, the back side of the wafer is temporarily bonded to the support carrier (10) by means of an ultraviolet (UV) adhesive film or a thermal release adhesive film (Thermal Release Tape).

[0100] The back of the wafer is temporarily bonded to a rigid support carrier (10) by means of an ultraviolet (UV) film or a thermal release tape. The support carrier (10) is, for example, a glass or resin substrate. Wafer mounting prevents warping or cracking during subsequent wafer cutting or molding. Depending on the size of the board-level packaging carrier, different numbers of wafers can be mounted. Since the post-process does not require mark alignment, mounting offset has little effect on subsequent processes.

[0101] The present invention provides a packaging structure formed using the aforementioned wafer-level and board-level combined packaging method, comprising a chip (1), the front surface of the chip (1) comprising a dielectric layer (2) and a metal pad (3), a third protective layer (5) being provided on the dielectric layer (2), and a conductive connection layer (4) being provided on the metal pad (3);

[0102] The side surface and the front surface of the chip (1) are plastic-sealed to form a first protective layer (6);

[0103] The top surface of the conductive connection layer (4) protrudes from the upper surface of the third protective layer (5), and the top surface of the conductive connection layer (4) exposes the upper surface of the first protective layer (6).

[0104] See also Figure 3 and Figure 4 As a specific embodiment of the present invention, the steps of the packaging method are as follows: Figure 3 As shown, the intermediate structure of the packaging process is as follows Figure 5-Figure 15 , packaging structure such as Figure 4 shown.

[0105] See also Figure 16 As a second specific embodiment, unlike the first embodiment, there is no backside molding step to form a second protective layer. After the wafer is molded on the front and side surfaces and backside grinding, it is directly ground on the front surface to expose the conductive connection layer. Solder metal plating is then performed, and the individual packages are fully cut. This package has no plastic encapsulant on the backside, and the printing is directly engraved on the silicon material. This solves the problem of wafer-level packaging without side encapsulation and improves the heat dissipation of the individual units.

[0106] Furthermore, the conductive connection layer (4) is a copper pillar or a stacked structure of a lower copper layer (4a) and an upper copper layer (4b);

[0107] When the conductive connection layer (4) is a stacked structure of a lower copper layer (4a) and an upper copper layer (4b), the lower copper layer (4a) is within the window of the third protective layer (5), and the upper surface of the lower copper layer (4a) is flush with the upper surface of the third protective layer (5); the upper copper layer (4b) covers the upper surface of the lower copper layer (4a) and part of the upper surface of the third protective layer (5); and the thickness of the lower copper layer (4a) is greater than the thickness of the upper copper layer (4b).

[0108] See also Figure 17 As a third specific embodiment, the difference from the first embodiment is that two layers of copper wiring are used on the front of the chip. The first layer, i.e., the lower copper layer, has a certain height, but its area is much smaller than the exposed lead of the target package. This lower copper layer is only located above the metal pad with a window of the third protective layer (5). As an interconnection layer, it connects the metal pad to the second upper copper layer. The size of the second upper copper layer is designed according to the pin size of the package. In this case, the third protective layer is formed by stacking a dielectric layer (5b) and a passivation layer (5a). The two-layer copper wiring design effectively reduces the parasitic capacitance between the large-area lead and the wafer surface, making it suitable for product packaging with high capacitance requirements.

[0109] The packaging structure and packaging method described in the present invention are suitable for wafers with surface lead electrodes. It combines wafer-level and board-level packaging processes. At the wafer level, the third protective layer and conductive connection layer process are used to accurately form the target product pin size and shape. At the board level, a single packaging structure is formed through pre-cutting, molding, grinding, plating of welding metal layers (tin plating or nickel-gold plating) and full cutting. It systematically solves the problems of wafer-level packaging not being able to be multi-faceted and the poor alignment accuracy in board-level packaging, providing a mass-producible advanced packaging platform for high-density wafers.

[0110] Compared with traditional packaging, the present invention is beneficial in that:

[0111] The packaging structure of the present invention combines a wafer-level packaging process with a board-level packaging process, has a simple process, uses standardized equipment and parameter templates in each step, and has strong process scalability.

[0112] In the process, the pin morphology of the final product is formed by electroplating a conductive connection layer at the wafer level, which simplifies the subsequent board-level packaging process. There is no need for yellow light electroplating and resist stripping and etching processes, and there is no need to customize exposure machines, electroplating tanks and other equipment for the wafer. It also effectively solves the problem of difficult alignment caused by warping, expansion and contraction or board cracking in traditional board-level packaging.

[0113] According to the packaging method of the present invention, a large substrate can be used to place multiple wafers at the same time in the back-end panel-level packaging, and the wafers do not need to be aligned with the front layer after being mounted. The offset of the wafer mounting and the Notch direction (used to identify the wafer direction) have no obvious effect on subsequent packaging, which effectively improves the packaging efficiency and reduces the product cost.

[0114] The packaging structure of the present invention realizes miniaturized packaging such as conventional DFN0402 / DFN0603 / DFN1006 by controlling the pre-cutting and grinding thickness, especially ultra-thin products with a thickness of 100-150 μm, and five-sided or six-sided encapsulation of a single chip, thereby improving the airtightness and reliability of the product.

[0115] The above are only preferred embodiments of the present invention and do not limit the implementation mode and protection scope of the present invention. For those skilled in the art, it should be aware that all solutions obtained by equivalent substitutions and obvious changes made using the description and illustrations of the present invention should be included in the protection scope of the present invention.

Claims

1. A wafer-level and board-level combined packaging method, characterized in that: include: Step A1, placing the entire wafer with its front side facing upward, and forming a conductive connection layer on the front side of the wafer; Step A2, temporarily attaching the back side of the wafer to a supporting plate; Step A3, performing plastic sealing on the front and side surfaces of the wafer to form a first protective layer; Step A4, removing the support plate; Step A5, grinding the first protective layer on the front surface of the wafer to expose the top surface of the conductive connection layer; Step A6: cutting the wafer into individual package structures.

2. The wafer-level and board-level combined packaging method according to claim 1, wherein: The step A1 comprises: Step A11, placing the entire wafer with its front side facing upward and exposing the dielectric layer and metal pads on the front side; Step A12, forming a third protective layer on the front surface of the wafer, and opening a window in the third protective layer to expose the metal pad; Step A13: forming a conductive connection layer on the metal pad, wherein a top surface of the conductive connection layer protrudes from an upper surface of the third protection layer.

3. The wafer-level and board-level combined packaging method according to claim 2, wherein: After step A1 and before step A2, the following steps are further performed: Step B1, thinning the back side of the wafer to a first predetermined thickness.

4. The wafer-level and board-level combined packaging method according to claim 2, wherein: In the step A12, a window is opened in the third protective layer to expose the cutting street; After step A2 and before step A3, the following steps are further performed: Step B2, pre-cutting the cutting path to form a groove; In step A6, full cutting is performed along the cutting streets to form individual packaging structures.

5. The wafer-level and board-level combined packaging method according to claim 4, wherein: After step A4 and before step A5, the method further includes: Step B3: thinning the back side of the wafer to a second predetermined thickness and exposing the first protective layer in the groove.

6. The wafer-level and board-level combined packaging method according to claim 3, wherein: After step A5 and before step A6, the method further includes: Step B4: plating a soldering metal layer on the top surface of the conductive connection layer.

7. The wafer-level and board-level combined packaging method according to claim 2, wherein: After step A4 and before step A5, the following steps are further included: Step B5: plastic-sealing the back side of the wafer to form a second protective layer.

8. The wafer-level and board-level combined packaging method according to claim 2, wherein: The conductive connection layer is a copper pillar or a stacked structure of a lower copper layer and an upper copper layer; When the conductive connection layer is a stacked structure of a lower copper layer and an upper copper layer, the lower copper layer is within the window of the third protective layer and the upper surface of the lower copper layer is flush with the upper surface of the third protective layer, the upper copper layer covers the upper surface of the lower copper layer and part of the upper surface of the third protective layer, and the thickness of the lower copper layer is greater than the thickness of the upper copper layer.

9. A packaging structure, characterized in that: Formed using a wafer-level and board-level combined packaging method according to any one of claims 1 to 8, comprising a chip, wherein the front surface of the chip comprises a dielectric layer and a metal pad, a third protective layer is provided on the dielectric layer, and a conductive connection layer is provided on the metal pad; The side and front sides of the chip are sealed to form a first protective layer; A top surface of the conductive connection layer protrudes from an upper surface of the third protection layer and a top surface of the conductive connection layer exposes an upper surface of the first protection layer.

10. The packaging structure according to claim 9, wherein: The conductive connection layer is a copper pillar or a stacked structure of a lower copper layer and an upper copper layer; When the conductive connection layer is a stacked structure of a lower copper layer and an upper copper layer, the lower copper layer is within the window of the third protective layer and the upper surface of the lower copper layer is flush with the upper surface of the third protective layer, the upper copper layer covers the upper surface of the lower copper layer and part of the upper surface of the third protective layer, and the thickness of the lower copper layer is greater than the thickness of the upper copper layer.

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