Process method for reducing packaging parasitic parameters

Abstract

The invention discloses a process method for reducing packaging parasitic parameters, which comprises the following steps of: S1, additionally arranging a plurality of salient points in a chip placing area of a packaging substrate for bonding a chip and the packaging substrate; s2, gluing the chip placing area, and placing the chip in the chip placing area; s3, after the chip is placed, continuously filling the insulating medium underfill among the plurality of salient points; and packaging by using a plastic packaging material to finish packaging processing. According to the invention, the plurality of salient points are additionally arranged for bonding, so that the distance between the chip and the packaging substrate is effectively reduced, and the influence of parasitic parameters is reduced; meanwhile, aiming at material selection, size control and structural limitation of insulating medium underfill, parasitic parameters are further reduced, and mechanical strength, thermal management and stability are considered; in addition, the method is controllable in cost and convenient to popularize and use.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor packaging, and in particular to a process method for reducing packaging parasitic parameters. Background Art

[0002] In the field of high-performance chip packaging, wire bonding technology has traditionally been used to achieve electrical interconnection between the chip and the packaging substrate. This process uses thin metal wires, such as gold and copper, to connect the pads on the chip to the corresponding solder joints on the substrate. However, with the continuous increase in chip operating frequencies and the increasing demand for signal integrity, this traditional interconnection method has gradually exposed significant limitations. The long wire lengths significantly increase the parasitic inductance and capacitance generated by the interconnects, causing problems such as signal delay, crosstalk, and high-frequency loss, seriously affecting the overall performance and stability of the chip.

[0003] Even more challenging is the difficulty in effectively shortening the distance between the chip solder joints and the substrate solder joints, hindering further optimization of lead lengths. This bottleneck has become a key factor hindering the development of high-performance computing, RF communications, and high-speed interface chips.

[0004] Currently, the traditional method for packaging high-performance chips is to use wire bonding, also known as wire bonding. This process is highly flexible, low-cost, and easy to design. However, due to the difficulty in optimizing wire length, it is also difficult to minimize the impact of parasitic parameters. This can lead to significant signal loss, causing signal delays, crosstalk, and other issues, seriously impacting overall performance. In addition, some companies are also using multi-layer wafer stacking and trapezoidal groove flip-chip interconnects for packaging. However, multi-layer stacking requires complex process steps, high equipment precision, and high costs, making it difficult to popularize. Summary of the Invention

[0005] In response to the above problems, the purpose of the present invention is to propose a process method for reducing the parasitic parameters of the package. By adding multiple bumps for bonding, the distance between the chip and the package substrate is effectively reduced, thereby reducing the impact of the parasitic parameters; at the same time, based on the structural limitations of material selection, size control and insulating dielectric underfill, the parasitic parameters are further reduced while taking into account mechanical strength, thermal management and stability; in addition, this method does not require multi-layer chip stacking, the cost is controllable, and it is easy to promote and use.

[0006] This is achieved through the following technical solutions: A process method for reducing package parasitic parameters includes the following steps: S1, adding multiple bumps in a core release area of a package substrate for bonding a chip to the package substrate; S2, applying glue to the core release area in step S1 and placing the chip in the core release area; S3, after the chip is placed in step S2, continuing to fill the gaps between the multiple bumps with an insulating dielectric underfill; and using a plastic encapsulation compound for encapsulation to complete the packaging process.

[0007] Preferably, in step S1, each bump includes a tin cap, a plated support, and a lower metal layer. The tin cap is used to connect the chip, and the lower metal layer is disposed between the plated support and the package substrate. The lower metal layer is secured to the package substrate via a solder pad. The tin cap provides good solderability and mechanical strength, enabling reliable bonding between the chip and the substrate. The lower metal layer is secured via the solder pad to avoid the risk of delamination.

[0008] Preferably, each bump further includes a barrier layer disposed between the tin cap and the electroplated pillar. The barrier layer can prevent the tin cap and the electroplated pillar from forming an intermetallic compound, thereby improving long-term reliability.

[0009] Preferably, the tin cap is made of tin-silver alloy, the barrier layer is nickel barrier layer, and the electroplated pillars are copper pillars. Tin-silver alloy is suitable for high-temperature applications and has a higher melting point than pure tin. The nickel barrier layer has high chemical stability and can inhibit electromigration.

[0010] Preferably, the diameter of each bump is between 60um and 130um, and the height is between 65um and 100um. Controlling the size of each bump also shortens the distance between the package substrate and the chip, thereby effectively reducing parasitic parameters.

[0011] Preferably, the distances between any two adjacent protrusions are the same.

[0012] Preferably, the core placement area in step S2 includes a central area and a peripheral area. When adding multiple bumps, the number of bumps in the central area is controlled to be greater than the number of bumps in the peripheral area. During actual operation of the chip, the center often expands and displaces significantly. The high density of bumps can disperse the stress during expansion and prevent cracking at the solder joint.

[0013] Preferably, when filling the insulating dielectric underfill in step S3 , the package substrate is at the bottom, the insulating dielectric underfill is in a trapezoidal structure, and two oblique sides of the trapezoidal structure are connected to the chip.

[0014] Preferably, the insulating dielectric bottom filler is made of epoxy resin material.

[0015] Compared with the prior art, the present invention has the following beneficial effects: The technical solution of the present invention effectively reduces the distance between the chip and the packaging substrate by adding multiple bumps for bonding, thereby reducing the influence of parasitic parameters; at the same time, based on the structural limitations of material selection, size control and insulating dielectric underfill, the parasitic parameters are further reduced while taking into account mechanical strength, thermal management and stability; in addition, the method does not require multi-layer chip stacking, the cost is controllable, and it is easy to promote and use. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 A flow chart of a process method for reducing package parasitic parameters; Figure 2 A schematic diagram of the structure of the connection between a bump and a packaging substrate; Figure 3 A schematic diagram of a structure in which a chip is connected to a package substrate via multiple bumps; Figure 4 A schematic diagram of a chip structure in which a chip is connected to a package substrate via multiple bumps and then packaged using a plastic encapsulation compound; Figure 5 This is a structural diagram of a chip connected to a packaging substrate through multiple bumps and then filled with an insulating dielectric bottom filler. DETAILED DESCRIPTION

[0017] The following is a combination of the embodiments of the present invention Figures 1 to 4 , the technical solutions in the embodiments of the present invention are described in detail.

[0018] like Figure 1 The figure shows a flow chart of a process method for reducing package parasitic parameters. This method uses multiple bumps to replace traditional bonding wires or multi-layer wafers to connect the chip and the package substrate, greatly shortening the path between the two and effectively reducing the impact of parasitic parameters. At the same time, there is no need to use high-precision equipment and perform complex multi-layer process steps, the cost is controllable, and it is easier to promote.

[0019] The method mainly includes the following steps: S1. Add multiple bumps in the core area of the package substrate for bonding the chip and the package substrate. The core area is the preset position on the package substrate for placing the chip.

[0020] like Figure 3 The figure shows a schematic diagram of a structure in which a chip is connected to a package substrate through multiple bumps. In the figure, 1 represents a bump, 2 represents a package substrate, and 4 represents a chip. Multiple bumps can effectively achieve bonding between the chip and the package substrate.

[0021] In this embodiment, each bump comprises at least a solder cap, a plated support, and a lower metal layer. The solder cap is used to connect the chip, providing good solderability and mechanical strength, enabling reliable bonding between the chip and the substrate. The lower metal layer is positioned between the plated support and the package substrate and is secured to the package substrate via a solder pad. This securement of the lower metal layer via the solder pad prevents the risk of delamination.

[0022] like Figure 2 The figure shows a schematic diagram of the structure of the connection between the bump and the package substrate. In the figure, 10 is the pad, 20 is the lower metal layer, 30 is the electroplated pillar, 40 is the barrier layer, and 50 is the tin cap. In each bump, a barrier layer can also be set between the tin cap and the electroplated pillar to prevent the tin cap and the electroplated pillar from forming intermetallic compounds, thereby improving the reliability of long-term use.

[0023] In this embodiment, the tin cap is made of a tin-silver alloy, the barrier layer is a nickel barrier layer, and the electroplated pillars are copper pillars. Tin-silver alloy is suitable for high-temperature applications and has a higher melting point than pure tin. The nickel barrier layer has high chemical stability and can inhibit electromigration. Copper pillars were chosen due to their wide application and low cost.

[0024] In this embodiment, each bump has a diameter between 60um and 130um, and a height between 65um and 100um. Controlling the size of each bump effectively shortens the distance between the package substrate and the chip, effectively reducing parasitic parameters. Controlling the height ensures a stable connection while shortening the distance between the chip and the package substrate. Controlling the diameter controls impedance, optimizing electrical performance, and enabling faster transmission of high-speed signals.

[0025] In this embodiment, the spacing between any two adjacent bumps is the same. The uniform spacing can avoid differences in local capacitance or local inductance, thereby reducing signal crosstalk.

[0026] S2. Apply glue to the core-releasing area in step S1. For example, apply glue of the U8410 series, which has a fast curing speed and can be used to fix and protect the chip. Then, place the chip in the core-releasing area.

[0027] In this embodiment, the core placement area in step S2 includes a central area and a peripheral area. When adding multiple bumps, the number of bumps in the central area is controlled to be greater than that in the peripheral area. During actual operation, the chip often generates heat, resulting in large expansion displacement at the center. The high density of bumps can disperse the stress during expansion and prevent cracking at the solder joint.

[0028] S3. After the chip placement in step S2 is completed, the insulating dielectric underfill is continued to be filled between the plurality of bumps to fill the gaps between the plurality of bumps, further strengthen the connection between the chip and the packaging substrate, and provide insulation protection.

[0029] like Figure 5 The figure shows a schematic diagram of a structure in which a chip is connected to a package substrate through multiple bumps and then filled with an insulating dielectric bottom filler. When filling the insulating dielectric bottom filler, the package substrate is regarded as the bottom, and the insulating dielectric bottom filler forms a trapezoidal structure with the two oblique sides of the trapezoidal structure connected to the chip, thereby filling the gaps between the multiple bumps and further helping to stabilize the connection between the chip and the package substrate.

[0030] like Figure 4 The figure shows a schematic diagram of a structure in which a chip is connected to a packaging substrate through multiple bumps and then encapsulated with a plastic encapsulation compound. 3 in the figure represents the plastic encapsulation compound, and 5 in the figure represents the insulating dielectric bottom filler. After the insulating dielectric bottom filler is filled, the plastic encapsulation compound is used to encapsulate the entire chip to complete the packaging process.

[0031] In this embodiment, the insulating dielectric underfill material is made of epoxy resin material, which has strong adhesion and excellent electrical insulation performance and is suitable for use in this package.

[0032] In summary, the present invention effectively reduces the distance between the chip and the packaging substrate by adding multiple bumps for bonding, thereby reducing the impact of parasitic parameters; at the same time, by targeting material selection, size control and structural limitations of insulating dielectric underfill, the parasitic parameters are further reduced while taking into account mechanical strength, thermal management and stability; in addition, this method does not require multi-layer chip stacking, the cost is controllable, and it is easy to promote and use, which is significantly progressive.

[0033] The above embodiments are only for illustrating the technical idea of the present invention and cannot be used to limit the protection scope of the present invention. Any changes made on the basis of the technical solution in accordance with the technical idea proposed by the present invention shall fall within the protection scope of the present invention.

Claims

1. A process method for reducing package parasitic parameters, characterized in that: The steps include: S1. Add multiple bumps in the core area of the package substrate to bond the chip to the package substrate; S2, applying glue to the core placement area in step S1, and placing the chip in the core placement area; S3, after the chip placement in step S2 is completed, continue to fill the insulating dielectric underfill between the plurality of bumps; Use plastic packaging material to complete the packaging process.

2. A process for reducing package parasitic parameters according to claim 1, characterized in that: In step S1, each bump includes a tin cap, an electroplated pillar and a lower metal layer. The tin cap is used to connect the chip. The lower metal layer is arranged between the electroplated pillar and the packaging substrate. The lower metal layer is fixed to the packaging substrate through a solder pad.

3. A process for reducing package parasitic parameters according to claim 2, characterized in that: Each bump further includes a barrier layer disposed between the tin cap and the electroplating pillar.

4. A process for reducing package parasitic parameters according to claim 3, characterized in that: The tin cap is made of tin-silver alloy, the barrier layer is made of nickel barrier layer, and the electroplating pillar is made of copper pillar.

5. The process for reducing package parasitic parameters according to claim 1, characterized in that: The diameter of each bump is between 60um and 130um, and the height is between 65um and 100um.

6. The process for reducing package parasitic parameters according to claim 1, characterized in that: The distance between any two adjacent bumps is the same.

7. The process for reducing package parasitic parameters according to claim 1, characterized in that: The core-laying area in step S2 includes a central area and a peripheral area. When adding multiple convex points, the number of convex points in the central area is controlled to be greater than the number of convex points in the peripheral area.

8. The process for reducing package parasitic parameters according to claim 1, characterized in that: When filling the insulating dielectric underfill in step S3 , the package substrate is at the bottom, and the insulating dielectric underfill is in a trapezoidal structure with two oblique sides connected to the chip.

9. The process for reducing package parasitic parameters according to claim 1, characterized in that: The insulating dielectric bottom filler is made of epoxy resin material.

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