Semiconductor laser chip and preparation method thereof

Abstract

The invention relates to the technical field of lasers, and discloses a semiconductor laser chip and a preparation method thereof. The semiconductor laser chip comprises a chip substrate and a groove structure, wherein the chip substrate comprises a first cavity surface and a second cavity surface which are opposite to each other along a first direction; the groove structure comprises a first groove and a second groove which are arranged at an interval along a second direction forming a preset included angle with the first direction and extend along the second direction; a first spacing distance is formed between one end, close to the first cavity surface, of the groove structure in the first direction and the first cavity surface, and a second spacing distance is formed between one end, close to the second cavity surface, in the first direction and the second cavity surface. According to the semiconductor laser chip and the manufacturing method thereof, when the chip base body is subjected to cleavage cutting in the second direction to form the first cavity surface and the second cavity surface, the actual fracture surface formed by cleavage cutting does not make contact with the first groove and the second groove, the probability that serious cleavage cavity lines appear on the first cavity surface and the second cavity surface is reduced, and the yield and reliability of the semiconductor laser chip are improved.

Description

Technical Field

[0001] The present invention relates to the technical field of lasers, and in particular to a semiconductor laser chip and a preparation method thereof. Background Art

[0002] Semiconductor lasers, due to their compact structure, long life, high reliability, high electro-optical conversion efficiency, fast modulation rate, wide wavelength range, and ease of integration, are widely used in many fields, including industrial production, LiDAR, military attack and defense, optical communications, optical information storage, and medical aesthetics. With the development and progress of society, many application fields have placed higher demands on the power, efficiency, and reliability of semiconductor lasers.

[0003] To achieve higher power output, single-tube semiconductor lasers usually need to operate at a drive current of 20A to 100A. At this time, the lateral mode gain increases with the increase of the drive current, resulting in resonance between the lateral end faces of the chip on the non-light-emitting surface, causing power jitter on the current-power curve, and ultimately reducing the output power and reliability of the semiconductor laser.

[0004] The commonly used approach currently is to etch two deep grooves in the area away from the chip edge, extending deep into the lower waveguide layer, lower confinement layer, and even the substrate. The deep grooves extend from the front cavity surface to the back cavity surface, thereby destroying lateral mode lasing. However, these deep grooves that penetrate the front and back cavity surfaces will introduce severe cleavage cavity lines during the subsequent cleavage process, thereby reducing the yield and reliability of semiconductor laser chips. Summary of the Invention

[0005] In view of this, the present invention provides a semiconductor laser chip and a method for preparing the same, in order to solve the problem that the cavity surface of the existing semiconductor laser chip has severe cleavage cavity marks, which affects the chip yield and reliability.

[0006] In a first aspect, the present invention provides a semiconductor laser chip, comprising: a chip substrate and a groove structure, the chip substrate comprising a first cavity surface and a second cavity surface opposite to each other along a first direction; the groove structure comprising a first groove and a second groove spaced apart along a second direction on the chip substrate, the first groove and the second groove extending along the first direction, the second direction forming a preset angle with the first direction; a first spacing distance being provided between an end of the groove structure in the first direction close to the first cavity surface and the first cavity surface, and a second spacing distance being provided between an end of the groove structure in the first direction close to the second cavity surface and the second cavity surface.

[0007] Beneficial effects: The present invention arranges that one end of the first groove and the second groove are spaced from the first cavity surface, and the other end is spaced from the second cavity surface. When the chip substrate is cleaved and cut along the second direction to form the first cavity surface and the second cavity surface, the actual fracture surface formed by the cleavage and cutting will not contact the first groove and the second groove, thereby reducing the probability of serious cleavage cavity lines on the first cavity surface and the second cavity surface; it can also monitor the process alignment accuracy during the chip substrate preparation process and the stability of the cleavage process, thereby improving the yield and reliability of the semiconductor laser chip.

[0008] In an optional embodiment, the first spacing distance ranges from 1 μm to 10 μm, and / or the second spacing distance ranges from 1 μm to 10 μm.

[0009] Beneficial effects: The range of the first spacing distance and the second spacing distance are both set to 1μm to 10μm, avoiding the situation where the distance is too small, which causes most semiconductor laser chips to form cleavage cavity lines when cleaving to form laser bars, thereby reducing product yield; and avoiding the situation where the distance is too large, which reduces the restriction on lateral mode lasing, thereby affecting the power of the semiconductor laser.

[0010] In an optional embodiment, the chip substrate further includes a first sidewall and a second sidewall opposite to each other along the second direction, the first groove is arranged close to the first sidewall, and the second groove is arranged close to the second sidewall;

[0011] There is a third spacing distance between the first trench and the first sidewall of the chip substrate, and / or there is a fourth spacing distance between the second trench and the second sidewall of the chip substrate.

[0012] Beneficial effect: A third spacing distance is set between the side of the first groove relatively far away from the second groove and the first side wall of the chip substrate, and a fourth spacing distance is set between the side of the second groove relatively far away from the first groove and the second side wall of the chip substrate, so that when the laser bar is cleaved into a single-tube chip along the first direction, the first groove and the second groove can shield the microcracks caused by cleavage from extending toward the current injection area, and release stress, thereby improving the chip yield and chip performance.

[0013] In an optional embodiment, the third spacing distance is equal to the fourth spacing distance.

[0014] Beneficial effect: Setting the third spacing distance equal to the fourth spacing distance helps to balance the force in the second direction, reduce the impact of stress imbalance on chip performance, facilitate the efficient preparation of the first groove and the second groove, and improve the preparation efficiency of semiconductor laser chips.

[0015] In an optional embodiment, the third spacing distance ranges from 5 μm to 20 μm.

[0016] Beneficial effect: The range of the third spacing distance is set to 5μm to 20μm, which, on the one hand, avoids the influence of a too small distance on the stability of the semiconductor laser chip, and on the other hand, avoids the reduction of the chip yield due to an excessively large distance.

[0017] In an optional embodiment, the chip base includes: a substrate layer and an epitaxial structure, the epitaxial structure includes a buffer layer, a lower confinement layer, a lower waveguide layer, an active layer, an upper waveguide layer, an upper confinement layer and an ohmic contact layer arranged in sequence on the surface of one side of the substrate layer; a groove structure extends from the ohmic contact layer into the lower waveguide layer.

[0018] Beneficial effects: The substrate layer provides physical support for the epitaxial structure and is the basis for the growth of subsequent layers. It helps the epitaxial layer to better maintain the integrity and consistency of the crystal during the growth process and reduce the generation of defects. The buffer layer is used to relieve the lattice mismatch stress between the substrate layer and the subsequent growth layer. The confinement layer (upper confinement layer and lower confinement layer) is used to confine the light field to the waveguide layer to prevent the light field from extending to the highly doped confinement layer, causing free carrier absorption loss and reducing the efficiency of the semiconductor laser chip. At the same time, the highly doped confinement layer can reduce the series resistance of the semiconductor laser and improve the electro-optical conversion efficiency. The active layer is the core area of the semiconductor laser chip that generates laser light. It adopts a quantum well structure. Electrons and holes are confined in a very thin space to form a discrete energy level structure. When current is injected, electrons and holes recombine in the quantum well and release photons, realizing the stimulated radiation process and generating laser light. The waveguide layer forms an optical waveguide structure through differences in refractive index, confining the light field generated by the active layer to a specific area. This reduces light scattering and loss, improves light propagation efficiency, ensures that the laser can be transmitted along a specific direction, and maintains good beam quality during propagation. The ohmic contact layer is used to provide a low-resistance ohmic contact between the semiconductor laser chip and the external circuit, ensuring that current can be smoothly injected into the device while enabling the device to effectively connect electrically to the external circuit.

[0019] In an optional embodiment, the chip base further includes: an insulating layer, a first electrode and a second electrode, the insulating layer being arranged on a surface of the side of the epitaxial structure facing away from the substrate layer, the insulating layer exposing a portion of the ohmic contact layer opening in the area between the first groove and the second groove to form a current injection window; the first electrode being arranged on a surface of the side of the insulating layer facing away from the substrate layer, and connected to the ohmic contact layer through the current injection window; the second electrode being arranged on a surface of the side of the substrate layer facing away from the epitaxial structure.

[0020] Beneficial Effects: An insulating layer is disposed on the ohmic contact layer, covering the surface of the ohmic contact layer and the inner wall surfaces of the grooves. An etching process is then used to remove at least a portion of the insulating layer protruding between the first and second grooves, forming a current injection window to enable current injection into the ridge structure between the first and second grooves. The first electrode fully covers the upper surface and directly contacts the ohmic contact layer through the current injection window, enabling efficient and precise current injection. The first and second electrodes serve as the front and back electrodes of the semiconductor laser product, respectively, to enable current injection.

[0021] In a second aspect, the present invention further provides a method for preparing a semiconductor laser chip, comprising:

[0022] Cleaving the laser array substrate to obtain a plurality of laser bars, each laser bar comprising a plurality of the aforementioned semiconductor laser chips arranged along the second direction;

[0023] Acquire a first surface image of the laser bar on a first surface side and / or a second surface image on a second surface side, wherein the first surface and the second surface are arranged opposite to each other along a first direction;

[0024] Acquire a first cavity surface image and / or a second cavity surface image of each semiconductor laser chip based on the first surface image and / or the second surface image;

[0025] It is determined whether the first cavity surface image and / or the second cavity surface image have a groove structure pattern. Under the condition that the first cavity surface image and / or the second cavity surface image do not have a groove structure pattern, a semiconductor laser chip that passes the preliminary screening is obtained.

[0026] Beneficial Effects: The spacing between the first and second grooves and the first and second cavity facets of the present invention significantly reduces the impact of the aforementioned offset on the cavity facet morphology of the semiconductor laser chip. By detecting the surface image of the laser bar along the actual fracture path, a semiconductor laser chip with qualified reliability along that path can be identified. Based on whether the groove structure pattern is exposed on the obtained cavity surface image, the semiconductor laser chips on the laser bar are preliminarily screened. The semiconductor laser chips without the groove structure pattern on the cavity surface image are considered to have passed the preliminary screening. The semiconductor laser chips that have passed the preliminary screening will then continue with the subsequent process, and the products that fail the preliminary screening will be scrapped. This method can avoid the increase in manufacturing costs caused by the flow of defective products to packaging, testing and aging sites, facilitate rapid screening and judgment and make corresponding disposal, reduce production costs and improve preparation efficiency; moreover, while ensuring that the groove structure itself plays a role in suppressing the power jitter on the current-power curve of the semiconductor laser chip and ultimately improving the output power and reliability of the semiconductor laser, the chips that have passed the preliminary screening do not have deep groove structures on the cleavage cavity surface, and the risk of forming cleavage cavity lines is low, which helps to further improve product yield and reliability.

[0027] In an optional embodiment, after the laser array substrate is cleaved to obtain a plurality of laser bars, and before obtaining a first surface image of the laser bar on the first surface side and / or a second surface image of the laser bar on the second surface side, the method further includes: setting a first cavity mask on the first surface of the laser bar and setting a second cavity mask on the second surface of the laser bar; one of the first cavity mask and the second cavity mask is an anti-reflection film, and the other is a high-reflection film.

[0028] Beneficial Effects: After the entire laser array substrate is divided into multiple laser bars, a film is applied to the first and second surfaces of the laser bars, both facing each other along a first direction. This allows for simultaneous coating of the cavity surfaces of multiple semiconductor laser chips in batches, improving production efficiency. More importantly, images of the first and second surfaces of the coated laser bars are more distinct and clear when captured under a microscope, improving surface image accuracy.

[0029] In an optional embodiment, after obtaining the semiconductor laser chip that passes the initial screening, the process further includes:

[0030] Performing cavity pattern detection on the first cavity surface and the second cavity surface of the semiconductor laser chip that has passed the preliminary screening to obtain a qualified semiconductor laser chip;

[0031] The qualified semiconductor laser chips are packaged and tested.

[0032] Beneficial Effects: The first and second cavity surface images of semiconductor laser chips that have passed the initial screening are compared with the cavity pattern control standard. If the tiny cavity patterns in the first and second cavity surface images of the semiconductor laser chip are within the cavity pattern control standard, the semiconductor laser chip is considered to meet the good product standard and is stored for subsequent processes, further improving the product yield level. If it does not meet the cavity pattern control standard, the semiconductor laser chip is scrapped. The qualified semiconductor laser chip is then bonded to complete the packaging. The packaged semiconductor laser chip is then powered on for testing, and a qualified semiconductor laser product is obtained. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] In order to more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the specific embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0034] Figure 1 is a schematic top view of a semiconductor laser chip according to an embodiment of the present invention;

[0035] Figure 2 yes Figure 1 The enlarged schematic diagram shown in part A;

[0036] Figure 3 It is along Figure 1 Schematic diagram of the cross section of the semiconductor laser chip taken along the ee line;

[0037] Figure 4 1 is a schematic flow chart of a method for preparing a semiconductor laser chip according to an embodiment of the present invention;

[0038] Figure 5 is a schematic top view of a laser bar according to an embodiment of the present invention;

[0039] Figure 6 is a partial top view of the first chip in the laser bar according to an embodiment of the present invention;

[0040] Figure 7 is a partial top view of the last chip in a laser bar according to an embodiment of the present invention;

[0041] Figure 8 It is along Figure 6 Schematic cross-sectional view of the semiconductor laser chip taken along line d1;

[0042] Figure 91 is another flow chart of a method for preparing a semiconductor laser chip according to an embodiment of the present invention.

[0043] Description of reference numerals:

[0044] 1. Chip substrate; 11. First cavity surface; 12. Second cavity surface; 13. First sidewall; 14. Second sidewall; 101. Substrate layer; 102. Buffer layer; 103. Lower confinement layer; 104. Lower waveguide layer; 105. Active layer; 106. Upper waveguide layer; 107. Upper confinement layer; 108. Ohmic contact layer; 109. Insulation layer; 1091. Current injection window; 1010. First electrode; 1011. Second electrode;

[0045] 21, first groove; 211, first end; 212, second end; 22, second groove; 221, third end; 222, fourth end;

[0046] 100 , semiconductor laser chip; 200 , laser bar; 201 , first surface; 202 , second surface. DETAILED DESCRIPTION

[0047] The present invention will be further described in detail below with reference to the accompanying drawings and examples. It should be understood that the specific examples described herein are intended only to illustrate the present invention and are not intended to limit it. It should also be noted that, for ease of description, the drawings only illustrate some, but not all, structures relevant to the present invention. In the following description, descriptions of known structures and technologies are omitted to avoid unnecessary confusion about the present invention. The accompanying drawings illustrate various schematic diagrams of structures according to embodiments of the present invention. These figures are not drawn to scale; certain details may be exaggerated or omitted for clarity. The shapes, relative sizes, and positional relationships of various regions and layers shown in the figures are merely illustrative and may vary in practice due to manufacturing tolerances or technical limitations. Those skilled in the art may design regions / layers with different shapes, sizes, and relative positions based on actual needs. In the context of the present invention, when a layer / element is referred to as being "on" another layer / element, the layer / element may be directly on the other layer / element, or an intervening layer / element may exist between them. In addition, if a layer / element is "on" another layer / element in one orientation, then when the orientation is reversed, the layer / element would be "below" the other layer / element.

[0048] With the development and progress of society, many fields have placed higher demands on the power, efficiency, and reliability of semiconductor lasers. For example, in the industrial application of 10,000-watt fiber lasers, the 915nm / 976nm semiconductor lasers used for optical pumping require higher power and better reliability.

[0049] In the related art, the lateral mode gain of single-tube semiconductor lasers increases when operating at high drive current, which reduces the output power and reliability of the semiconductor laser. The currently commonly used solution is to etch two deep etched grooves extending from the front cavity surface to the rear cavity surface in the area away from the edge of the laser chip to destroy the lasing of the lateral mode. However, such deep etched grooves running through the front and rear cavity surfaces will introduce severe cleavage cavity lines during the subsequent cleavage process, reducing the yield and reliability of the semiconductor laser chip. In addition, it will affect the identification of good chips and reduce the production efficiency of semiconductor laser products.

[0050] Based on this, Figures 1 to 3 As shown, this embodiment provides a semiconductor laser chip 100, including: a chip substrate 1 and a groove structure, the chip substrate 1 including a first cavity surface 11 and a second cavity surface 12 opposite to each other along a first direction; the groove structure including a first groove 21 and a second groove 22 spaced apart along a second direction on the chip substrate 1, the first groove 21 and the second groove 22 extending along the first direction, and the second direction forming a preset angle with the first direction; a first spacing distance is formed between an end of the groove structure close to the first cavity surface 11 in the first direction and the first cavity surface 11, and a second spacing distance is formed between an end of the groove structure close to the second cavity surface 12 in the first direction and the second cavity surface 12.

[0051] Illustratively, the chip substrate 1 may include a substrate layer 101 and an epitaxial structure formed by sequentially epitaxially growing various structural layers on the substrate layer 101 . Figure 1It is a top view schematic diagram of the chip substrate 1, the first direction is the front-back direction of the laser chip, the second direction is the left-right direction, and the first direction is perpendicular to the second direction. For example, in this embodiment, the front cavity surface of the chip substrate 1 is the first cavity surface 11 for laser emission, and the back cavity surface is the second cavity surface 12 for reflecting laser. A groove structure is etched on the epitaxial structure of the chip substrate 1, and the groove structure includes a first groove 21 and a second groove 22 spaced apart in the second direction. The first groove 21 and the second groove 22 both extend along the first direction. The front ends of the first groove 21 and the second groove 22 do not extend to the first cavity surface 11 of the chip substrate 1, that is, they have a certain distance from the first cavity surface 11. At the same time, the rear ends of the first groove 21 and the second groove 22 do not extend to the second cavity surface 12 of the chip substrate 1, that is, they have a certain distance from the second cavity surface 12. In this way, when the chip substrate 1 is cleaved and cut along the second direction, the first cavity surface 1 1 and the second cavity surface 12, since the front ends of the first grooves 21 and the second grooves 22 are spaced apart from the first cavity surface 11 and the rear ends are spaced apart from the second cavity surface 12, the actual fracture surface formed by the cleavage cutting will not contact the first grooves 21 and the second grooves 22, thereby reducing the probability of serious cleavage cavity lines on the first cavity surface 11 and the second cavity surface 12; and setting a certain distance between the first grooves 21 and the second grooves 22 and the front and rear cavity surfaces of the chip substrate 1 can also monitor the process alignment accuracy during the preparation process of the chip substrate 1 and the stability of the cleavage process, thereby improving the yield and reliability of the semiconductor laser chip 100.

[0052] The semiconductor laser chip 100 may be an edge-emitting laser chip or a quantum cascade laser chip, or other semiconductor lasers with sidewall emission. In this embodiment, the semiconductor laser chip 100 is an edge-emitting laser chip.

[0053] In one embodiment, a single-tube semiconductor laser product is typically prepared by first forming an epitaxial structure on a substrate layer 101, such as a wafer, to form a monolithic laser array substrate comprising multiple semiconductor laser chips 100. This laser array substrate may further comprise multiple laser bars 200 (bars), each laser bar 200 comprising a row of semiconductor laser chips 100. The laser array substrate is then diced to form multiple individual laser bars 200, which are then diced to form multiple individual semiconductor laser chips 100. Finally, subsequent packaging and other steps are performed to obtain the semiconductor laser product. Therefore, the specific values of the first and second spacing distances described above in this embodiment are determined with reference to the number of semiconductor laser chips 100 in a single laser bar 200.

[0054] It is known that reference Figure 1 and Figure 2In this embodiment, the front ends of the first groove 21 and the second groove 22 are preferably equidistant from the first cavity surface 11, and the rear ends of the first groove 21 and the second cavity surface 12 are equidistant from the second cavity surface 12. In other words, the spacing W1 between the first end 211 of the first groove 21 and the first cavity surface 11 is equal to the spacing W3 between the third end 221 of the second groove 22 and the first cavity surface 11; and the spacing W2 between the second end 212 of the first groove 21 and the second cavity surface 12 is equal to the spacing W4 between the fourth end 222 of the second groove 22 and the second cavity surface 12. This helps to improve the preparation efficiency of the first groove 21 and the second groove 22, and also facilitates improving the consistency of cavity surface detection on the first cavity surface 11 side and the second cavity surface 12 side during the preparation process of the semiconductor laser chip 100. When the cavity surface quality of the semiconductor laser chips 100 in a laser bar 200 is sequentially inspected, when the first semiconductor laser chip 100 with a cavity surface defect is detected, the subsequent semiconductor laser chips 100 can be clearly identified as unqualified without the need for inspection, thereby quickly screening out qualified semiconductor laser chips 100.

[0055] Specifically in this embodiment, the first spacing distance between the first trench 21 and the second trench 22 and the first cavity facet 11 is preferably equal to the second spacing distance between the first trench 21 and the second trench 22 and the second cavity facet 12. The first spacing distance and the second spacing distance are both set in the range of 1 μm to 10 μm. If the distance is too small, most semiconductor laser chips 100 will form cleavage cavity lines when cleaving to form laser bars 200, thereby reducing product yield; while if the distance is too large, the restriction on lateral mode lasing will be reduced, thereby affecting the power of the semiconductor laser.

[0056] Of course, it is not ruled out that the first spacing distance and the second spacing distance have different ranges. For example, if the first cavity surface 11 is more likely to have cleavage cavity lines than the second cavity surface 12, the first spacing distance can be set slightly larger than the second spacing distance; similarly, if the second cavity surface 12 is more likely to have cleavage cavity lines than the first cavity surface 11, the second spacing distance can be set slightly larger.

[0057] For example, this embodiment uses a 45W single-tube semiconductor laser chip 100 with a width of 500μm in the second direction as an example. Assuming the number of semiconductor laser chips 100 arranged along the second direction in the laser bar 200 is 25, W1 = 5μm is the preferred value based on the reliability standards of previous large-scale data. During a cleavage run along the second direction from the starting point to the end point, deep groove patterns were found on the first cavity facet 11 of chips 21 to 25, resulting in them being deemed defective. Among the chips 1 to 20 that did not show deep grooves, these chips were then subjected to cavity pattern inspection and compared to the control standard. If the first cavity facet 11 of two chips exceeded the control standard during the cavity pattern inspection and were determined to be defective, the laser bar 200 ultimately produced 18 qualified chips, all without groove structures or severe cleavage cavity patterns. These 18 chips do not have serious cleavage cavity lines because there is no deep etched groove structure on the cleavage path. The reasonable W1 value can ensure that the first groove 21 and the second groove 22 effectively limit the lateral mode lasing, and at the same time obtain qualified semiconductor laser chips 100 to the greatest extent.

[0058] refer to Figure 2 In the semiconductor laser chip 100 of this embodiment, the chip substrate 1 further includes a first sidewall 13 and a second sidewall 14 opposite to each other along the second direction, the first groove 21 is arranged close to the first sidewall 13, and the second groove 22 is arranged close to the second sidewall 14; a third spacing distance exists between a side of the first groove 21 relatively away from the second groove 22 and the first sidewall 13 of the chip substrate 1, and a fourth spacing distance exists between a side of the second groove 22 relatively away from the first groove 21 and the second sidewall 14 of the chip substrate 1.

[0059] It can be seen that the first trench 21 and the second trench 22 are parallel to each other and to the first sidewall 13 and the second sidewall 14 of the chip substrate 1. In the second direction, a third spacing distance H1 is provided between the side of the first trench 21 relatively remote from the second trench 22 and the first sidewall 13 of the chip substrate 1, while a fourth spacing distance H2 is provided between the side of the second trench 22 relatively remote from the first trench 21 and the second sidewall 14 of the chip substrate 1. This allows the first trench 21 and the second trench 22 to shield microcracks caused by cleavage from extending toward the current injection region when the laser bar 200 is cleaved into single-element chips along the first direction, thereby relieving stress and improving chip yield and performance.

[0060] As a preferred embodiment, the third spacing distance H1 and the fourth spacing distance H2 are set to be equal to each other, so as to balance the force in the second direction, reduce the influence of stress imbalance on chip performance, facilitate efficient preparation of the first groove 21 and the second groove 22, and improve the preparation efficiency of the semiconductor laser chip 100.

[0061] Furthermore, the third spacing distance H1 is in the range of 5 μm to 20 μm. If the distance is too small, it will be detrimental to the stability of the semiconductor laser chip 100 , while if the distance is too large, the chip yield will be reduced.

[0062] In one embodiment, reference Figure 3 The chip substrate 1 includes: a substrate layer 101 and an epitaxial structure. The epitaxial structure includes a buffer layer 102, a lower confinement layer 103, a lower waveguide layer 104, an active layer 105, an upper waveguide layer 106, an upper confinement layer 107 and an ohmic contact layer 108 arranged in sequence on one side of the substrate layer 101; a trench structure extends from the ohmic contact layer 108 into the lower waveguide layer 104.

[0063] The substrate layer 101 provides physical support for the epitaxial structure and is the basis for the growth of subsequent layers. It helps the epitaxial layer to better maintain the integrity and consistency of the crystal during the growth process and reduce the generation of defects. For example, the material of the substrate layer 101 can be gallium arsenide (GaAs) or indium phosphide (InP). A buffer layer 102, a lower confinement layer 103, a lower waveguide layer 104, an active layer 105, an upper waveguide layer 106, an upper confinement layer 107 and an ohmic contact layer 108 can be grown in sequence on one side of the substrate layer 101 through a molecular beam epitaxy process or a chemical vapor deposition process to form a structure such as Figure 3 The epitaxial structure shown.

[0064] Specifically, the buffer layer 102 is used to alleviate the lattice mismatch stress between the substrate layer 101 and the subsequent growth layer, and the confinement layer (upper confinement layer 107 and lower confinement layer 103) is used to confine the light field to the waveguide layer, preventing the light field from extending to the highly doped confinement layer, causing free carrier absorption loss, and reducing the efficiency of the semiconductor laser chip 100. At the same time, the highly doped confinement layer can reduce the series resistance of the semiconductor laser and improve the electro-optical conversion efficiency. The active layer 105 is the core area of the semiconductor laser chip 100 where laser light is generated. It adopts a quantum well structure, and electrons and holes are confined in a very thin space to form a discrete energy level structure. When current is injected, electrons and holes recombine in the quantum well, releasing photons, realizing the stimulated emission process, and generating laser light. The refractive index of the waveguide layer (upper waveguide layer 106 and lower waveguide layer 104) is between that of the confinement layer and the active layer 105. This difference in refractive index forms an optical waveguide structure, confining the light field generated by the active layer 105 to a specific area. This reduces light scattering and loss, improves light propagation efficiency, ensures that the laser can be transmitted along a specific direction, and maintains good beam quality during propagation. The ohmic contact layer 108 is used to provide a low-resistance ohmic contact between the semiconductor laser chip 100 and the external circuit, ensuring that current can be smoothly injected into the device and enabling the device to be effectively electrically connected to the external circuit.

[0065] Furthermore, if Figure 3 As shown, the above-mentioned chip substrate 1 also includes: an insulating layer 109, a first electrode 1010 and a second electrode 1011. The insulating layer 109 is arranged on the side surface of the epitaxial structure away from the substrate layer 101, and the insulating layer 109 exposes a portion of the opening of the ohmic contact layer 108 in the area between the first groove 21 and the second groove 22 to form a current injection window 1091; the first electrode 1010 is arranged on the side surface of the insulating layer 109 away from the substrate layer 101, and is connected to the ohmic contact layer 108 through the current injection window 1091; the second electrode 1011 is arranged on the side surface of the substrate layer 101 away from the epitaxial structure.

[0066] Specifically, an insulating layer 109 is provided on the ohmic contact layer 108. The insulating layer 109 covers the surface of the ohmic contact layer 108 and the inner wall surface of the groove. Then, an etching process is used to remove at least a portion of the insulating layer 109 located on the protrusion between the first groove 21 and the second groove 22 to form a current injection window 1091 to enable current injection into the ridge structure between the first groove 21 and the second groove 22. The first electrode 1010, also known as the front electrode, is provided on a side of the insulating layer 109 relatively far from the substrate layer 101. The first electrode 1010 fully covers the upper surface, including filling the first groove 21 and the second groove 22. The first electrode 1010 is in direct contact with the ohmic contact layer 108 through the current injection window 1091, achieving efficient and accurate current injection. Exemplarily, the first electrode 1010 can be titanium (Ti), platinum (Pt), gold (Au) and alloys thereof. The second electrode 1011 , ie, the back electrode, is disposed on a side of the substrate layer 101 away from the epitaxial structure. The second electrode 1011 may be made of gold (Au), germanium (Ge), nickel (Ni), or alloys thereof.

[0067] refer to Figures 1 to 8 This embodiment also provides a method for preparing a semiconductor laser chip. Figure 4 Schematic diagram of the preparation method, the preparation method comprises the following steps:

[0068] In step S401 , the laser array substrate is cleaved to obtain a plurality of laser bars 200 . Each laser bar 200 includes a plurality of the aforementioned semiconductor laser chips 100 arranged along a second direction.

[0069] For example, a laser array substrate is formed by epitaxially growing various structural layers, forming an insulating layer 109, and growing electrode materials on a monolithic gallium arsenide substrate layer 101. The laser array substrate includes multiple laser bars 200 arranged sequentially in a first direction. Each laser bar 200 includes multiple semiconductor laser chips 100 arranged sequentially in a second direction. The first and second directions are perpendicular to each other. The laser array substrate can be cleaved into multiple laser bars 200 by scribing along cleavage grooves in the second direction.

[0070] Step S402 : acquiring a first surface image of the laser bar 200 on the first surface 201 side and / or a second surface image on the second surface 202 side, wherein the first surface 201 and the second surface 202 are arranged opposite to each other along a first direction.

[0071] Since in the process of forming the laser array matrix, it is necessary to realize the positioning and etching of each semiconductor laser chip 100 in multiple different steps through processes such as yellow light process (that is, a process of forming a specific structure by yellow light lithography after setting a mask template), if there is an alignment error in the first yellow light process, all subsequent yellow light processes will have alignment errors based on the first yellow light process, resulting in the position of the semiconductor laser chip 100 arranged in the laser array matrix having an error with the pre-set position of the semiconductor laser chip 100.

[0072] refer to Figure 5When cleaving, the cleavage knife lightly presses down at the cleavage starting point a to form a notch, and the dicing machine roller gradually reaches the cleavage end point b along the preset cleavage path c from the cleavage starting point a, but in fact the chip will form a smooth cross-section along the actual fracture path d; for the gallium arsenide substrate layer 101, the actual fracture path d is parallel to the natural cleavage path. The natural cleavage path is the area on the substrate layer 101 where the interatomic bonding force is the lowest. The natural cleavage path has nothing to do with the process and technology, and is the natural characteristic of the crystal itself. Due to factors such as alignment errors in the front-end yellowing process, the actual fracture path d, which is consistent with the natural cleavage path, deviates from the preset cleavage path c, i.e., the path traversed by the roller. This deviation (i.e., the misalignment between the preset cleavage path c and the actual fracture path d) is related to the cleavage accuracy of the substrate layer 101, the linearity of the large flat edge of the substrate layer 101 when it is received, the alignment accuracy of the front-end process, and fluctuations in the cleavage process parameters. This deviation between the roller's downward pressure point and the natural cleavage path can form cleavage cavity lines on the cavity surface formed by cleavage, which can become the starting point for subsequent cavity surface failure and reduce the reliability of the semiconductor laser chip 100. However, in this embodiment, the spacing between the first and second grooves 21, 22 and the first and second cavity surfaces 11, 12 can greatly reduce the impact of this deviation on the cavity surface morphology of the semiconductor laser chip 100. Furthermore, by detecting the surface image of the laser bar 200 along the actual fracture path d, a semiconductor laser chip 100 with qualified reliability for this path can be obtained.

[0073] In one embodiment, the acquired surface image may include a first surface image on the first surface 201 of the laser bar 200 and a second surface image on the second surface 202 opposite to each other in the first direction. Of course, only one of the first surface image or the second surface image may be acquired. For example, in this embodiment, it is preferred to acquire only the first surface image of the side of the first surface 201 that is additionally cut by the laser bar 200 due to the offset. Figure 5 As shown, it is possible to obtain the cavity surface morphology and improve the detection efficiency.

[0074] Step S403 : acquiring a first cavity surface image and / or a second cavity surface image of each semiconductor laser chip 100 based on the first surface image and / or the second surface image.

[0075] Because the first surface 201 of the laser bar 200 includes the first cavity facets 11 of multiple semiconductor laser chips 100, the first cavity facet image of each semiconductor laser chip 100 can be obtained by acquiring the first surface image. Similarly, because the second surface 202 of the laser bar 200 includes the second cavity facets 12 of multiple semiconductor laser chips 100, the second cavity facet image of each semiconductor laser chip 100 can be obtained by acquiring the second surface image. If the first surface image is acquired in step S402, the cavity facet image acquired in this step is the first cavity facet image; if the second surface image is acquired in step S402, the cavity facet image acquired in this step is the second cavity facet image; or if both the first and second surface images are acquired in step S402, the cavity facet images acquired in this step are the first and second cavity facet images. In other words, the acquired cavity facet image of the semiconductor laser chip 100 corresponds to the acquired surface image of the laser bar 200.

[0076] Step S404 , determining whether the first cavity surface image and / or the second cavity surface image have a groove structure pattern. Under the condition that the first cavity surface image and / or the second cavity surface image do not have a groove structure pattern, a semiconductor laser chip 100 that passes the preliminary screening is obtained.

[0077] Since the two ends of the groove structure of each semiconductor laser chip 100 in the first direction are spaced apart from the front and rear cavity surfaces of the chip substrate 1, when the actual fracture path d deviates from the preset cleavage path c, i.e., the path passed by the roller, a portion of the groove structure of the semiconductor laser chip 100 may be exposed on the actual fracture path d. Therefore, in this embodiment, the semiconductor laser chips 100 on the laser bar 200 are preliminarily screened based on whether the first cavity surface image or the second cavity surface image, or whether the first cavity surface image and the second cavity surface image have exposed groove structure patterns. The semiconductor laser chips 100 without groove structure patterns on the cavity surface image are preliminarily screened. The semiconductor laser chips 100 that pass the initial screening will then continue with the subsequent process, and the products that fail the initial screening will be scrapped. This method can avoid the increase in manufacturing costs caused by the flow of defective products to the packaging, testing and aging sites, facilitates rapid screening and judgment and makes corresponding disposal, reduces production costs, and improves preparation efficiency; moreover, while ensuring that the groove structure itself plays a role in suppressing the power jitter on the current-power curve and ultimately improving the output power and reliability of the semiconductor laser for the semiconductor laser chip 100, the chips that pass the initial screening do not have a deep groove structure on the cleavage cavity surface, and the risk of forming cleavage cavity lines is low, which helps to further improve product yield and reliability.

[0078] For example, refer to Figure 3 、 Figures 5 to 8In this embodiment, a 45W single-tube semiconductor laser chip 100 with a width of 500 μm in the second direction is taken as an example. Figure 5 As shown, assuming that the number of dies n of the semiconductor laser chips 100 arranged in the laser bar 200 is 25, then based on the previous production big data reliability standards, a W1 value of 5μm is preferred. During a cleavage along the second direction from the starting point to the end point, deep etched groove patterns, namely the first groove pattern and / or the second groove pattern, were found on the first cavity surface 11 of the 21st to 25th chips, and they were determined to be unqualified products. For example, Figure 7 The actual fracture path d2 of the last chip is shown. The corresponding schematic diagram of the first cavity surface image of the last chip with the groove structure pattern can be seen in FIG. Figure 3 As shown. In the 1st to 20th chips where no deep etch grooves were found, the first cavity surface image did not show a groove structure pattern, and there was no serious cleavage cavity pattern caused by offset. For example, Figure 6 The actual fracture path d1 of the first chip is shown, and the corresponding schematic diagram of the first cavity surface image of the first chip without the groove structure pattern is shown as follows Figure 8 As shown; these chips are then subjected to cavity pattern inspection, comparing them to the control standard. If the first cavity surface 11 of two chips exceeds the control standard during the cavity pattern inspection and is judged as defective, the laser bar 200 ultimately produces 18 qualified chips, none of which have groove structures or severe cleavage cavity patterns. Therefore, it can be seen that in the manufacturing process of the semiconductor laser chip 100, under the premise that the groove structure is separated from the chip cleavage cavity surface, that is, a reasonable W1 value is selected, the cavity surface image formed after cleavage can be used as a reference to preliminarily screen and determine whether the semiconductor laser chips 100 on the laser bar 200 are qualified. While ensuring that the first groove 21 and the second groove 22 effectively limit lateral mode lasing, more qualified semiconductor laser chips 100 can be obtained, thereby improving product yield. In addition, it can effectively avoid the cost increase caused by defective products, facilitate rapid screening and judgment, and make corresponding treatment, and improve production efficiency.

[0079] Based on the above solution, after step S401 of cleaving the laser array substrate to obtain a plurality of laser bars 200, and before step S402 of acquiring a first surface image of the laser bar 200 on the first surface 201 side and / or a second surface image of the laser bar 200 on the second surface 202 side, the method further includes: disposing a first cavity mask on the first surface 201 of the laser bar 200, and disposing a second cavity mask on the second surface 202 of the laser bar 200; one of the first cavity mask and the second cavity mask is an anti-reflection film, and the other is a high-reflection film.

[0080] After the entire laser array substrate is divided into multiple laser bars 200, a film is applied to the first and second surfaces 201, 202, of the laser bars 200, which are opposite each other along a first direction. This allows for simultaneous coating of the cavity surfaces of multiple semiconductor laser chips 100 in batches, improving manufacturing efficiency. More importantly, images of the first and second surfaces of the coated laser bars 200 are more distinct and clear when captured under a microscope. After coating, the laser bars 200 are cleaved along the first direction through the cleavage grooves, separating the multiple semiconductor laser chips 100 within the laser bar 200 for subsequent packaging, aging, and testing. An anti-reflection coating is applied to the cavity surface of the semiconductor laser chip 100, which emits laser light, while a high-reflection coating is applied to the cavity surface on the opposite side, which reflects laser light. For example, the first cavity surface 11 of the semiconductor laser chip 100 in this embodiment is used for laser emission, so the first cavity surface film is an anti-reflection film to improve the laser emission rate; the second cavity surface 12 opposite to the first cavity surface 11 is used to reflect the laser so that the laser can be emitted from the first cavity surface 11 as much as possible, so the second cavity surface film is a high-reflection film to improve the laser reflection efficiency.

[0081] See also Figure 9 In one embodiment, after the above-mentioned step S404 of obtaining the semiconductor laser chip 100 that has passed the preliminary screening, the following steps are further included:

[0082] Step S405 : performing cavity pattern detection on the first cavity facet 11 and the second cavity facet 12 of the semiconductor laser chip 100 that has passed the preliminary screening to obtain a qualified semiconductor laser chip 100 .

[0083] The first cavity surface image and the second cavity surface image of the semiconductor laser chip 100 that have passed the initial screening are compared with the cavity pattern card control standard. If the tiny cavity patterns in the first cavity surface image and the second cavity surface image of the semiconductor laser chip 100 are within the cavity pattern card control standard, the semiconductor laser chip 100 is considered to meet the good product standard and is determined to be qualified and put into storage for subsequent processes; if it does not meet the cavity pattern card control standard, the semiconductor laser chip 100 is scrapped.

[0084] Step S406 : performing packaging processing and packaging testing on the qualified semiconductor laser chip 100 .

[0085] The qualified semiconductor laser chip 100 is subjected to chip bonding to complete the packaging; then the packaged semiconductor laser chip 100 is powered on for packaging testing, and an excellent semiconductor laser product is obtained after passing the test.

[0086] The further functional description of each of the above structures is the same as that of the above corresponding embodiments and will not be repeated here.

[0087] While the above description does not provide detailed technical details regarding patterning and etching of each layer, those skilled in the art will appreciate that various technical means can be employed to form layers, regions, and the like in desired shapes. Furthermore, those skilled in the art may devise methods that differ from those described above to form the same structure. Furthermore, while each embodiment has been described separately, this does not mean that the measures in each embodiment cannot be advantageously combined.

[0088] Although the embodiments of the present invention have been described with reference to the accompanying drawings, those skilled in the art may make various modifications and variations without departing from the spirit and scope of the present invention. Such modifications and variations are all within the scope defined by the appended claims.

Claims

1. A semiconductor laser chip, characterized in that: include: A chip substrate, the chip substrate comprising a substrate layer and an epitaxial structure, the epitaxial structure comprising a buffer layer, a lower confinement layer, a lower waveguide layer, an active layer, an upper waveguide layer, an upper confinement layer, and an ohmic contact layer sequentially arranged on a surface of one side of the substrate layer, and a first cavity facet and a second cavity facet opposite to each other along a first direction; A groove structure extends from the ohmic contact layer into the lower waveguide layer, including a first groove and a second groove spaced apart along a second direction on the chip substrate, the first groove and the second groove extending along the first direction, the second direction forming a preset angle with the first direction; a first spacing distance is formed between an end of the groove structure close to the first cavity surface in the first direction and the first cavity surface, and a second spacing distance is formed between an end of the groove structure close to the second cavity surface in the first direction and the second cavity surface.

2. The semiconductor laser chip according to claim 1, wherein The first spacing distance ranges from 1 μm to 10 μm, and / or the second spacing distance ranges from 1 μm to 10 μm.

3. The semiconductor laser chip according to claim 1, wherein The chip substrate further includes a first sidewall and a second sidewall opposite to each other along the second direction, the first groove is arranged close to the first sidewall, and the second groove is arranged close to the second sidewall; There is a third spacing distance between the side of the first trench relatively far from the second trench and the first sidewall of the chip base, and / or there is a fourth spacing distance between the side of the second trench relatively far from the first trench and the second sidewall of the chip base.

4. The semiconductor laser chip according to claim 3, characterized in that The third spacing distance is equal to the fourth spacing distance.

5. The semiconductor laser chip according to claim 4, characterized in that The third spacing distance ranges from 5 μm to 20 μm.

6. The semiconductor laser chip according to claim 1, wherein The chip substrate further includes: an insulating layer, disposed on a surface of the epitaxial structure facing away from the substrate layer; the insulating layer exposing a portion of the ohmic contact layer in a region between the first trench and the second trench to form a current injection window; a first electrode, disposed on a surface of the insulating layer facing away from the substrate layer and connected to the ohmic contact layer through the current injection window; The second electrode is arranged on a surface of the substrate layer facing away from the epitaxial structure.

7. A method for preparing a semiconductor laser chip, characterized in that: include: Cleaving the laser array substrate to obtain a plurality of laser bars, wherein any of the laser bars comprises a plurality of semiconductor laser chips according to any one of claims 1 to 6 arranged along a second direction; Acquire a first surface image of the laser bar on a first surface side and / or a second surface image of the laser bar on a second surface side, wherein the first surface and the second surface are arranged opposite to each other along a first direction; Acquire a first cavity surface image and / or a second cavity surface image of each semiconductor laser chip based on the first surface image and / or the second surface image; It is determined whether the first cavity surface image and / or the second cavity surface image have a groove structure pattern. Under the condition that the first cavity surface image and / or the second cavity surface image do not have the groove structure pattern, a semiconductor laser chip that passes the preliminary screening is obtained.

8. The method for preparing a semiconductor laser chip according to claim 7, wherein: After cleaving the laser array substrate to obtain a plurality of laser bars and before acquiring a first surface image of the laser bar on the first surface side and / or a second surface image of the laser bar on the second surface side, the method further includes: A first cavity mask is provided on the first surface of the laser bar, and a second cavity mask is provided on the second surface of the laser bar; one of the first cavity mask and the second cavity mask is an anti-reflection film, and the other is a high-reflection film.

9. The method for preparing a semiconductor laser chip according to claim 8, wherein: After obtaining the semiconductor laser chip that has passed the initial screening, the method further includes: Performing cavity pattern detection on the first cavity surface and the second cavity surface of the semiconductor laser chip that has passed the preliminary screening to obtain a qualified semiconductor laser chip; The qualified semiconductor laser chips are packaged and tested.

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