Backflow-prevention boost control circuit and switching power supply

Abstract

The invention relates to an anti-reverse-flow boost control circuit and a switching power supply, and the control circuit is connected with a Buck circuit through a first comparison module, and samples and compares the input voltage and the output voltage of the Buck circuit to obtain a first comparison signal; the time delay module is connected with the first comparison module and the mistaken touch control module and is used for delaying the first comparison signal to obtain a time delay signal; and the mistaken touch control module is connected with the first comparison module and the Buck circuit, and outputs a forced closing signal based on the first comparison signal and the delay signal under the condition that backward flowing occurs in the Buck circuit so as to control a switching tube of the Buck circuit to be closed, so that the problem of overvoltage breakdown of the Buck circuit caused by backward flowing of the output energy to the input is solved, and the safety and reliability of the circuit are ensured.

Description

Technical Field

[0001] The present application relates to the technical field of switching power supplies, and in particular to a control circuit for preventing backfeed and boosting voltage, and a switching power supply. Background Art

[0002] As demand for power supply efficiency increases, synchronous rectifier power MOSFETs are gradually replacing traditional freewheeling diodes to improve conversion efficiency and reduce losses. At the same time, some applications require low output ripple, continuous output without bursts, and low electromagnetic interference (EMI) at all loads (from no load to full load). Power supplies combining synchronous rectification with forced continuous conduction mode (FCCM) have emerged.

[0003] Many low-voltage products use a low-voltage Buck solution with synchronous rectification + FCCM mode. However, in actual use, there is a problem where the output energy flows back to the input, causing the Buck chip to overvoltage and breakdown. Figure 1 As shown, when there is no voltage applied to the input Vin, a voltage applied to the output Vo, and M1 and M2 are not turned on, the output energy will flow back into the SW, flowing through the body diode of M1 to the input, causing the input voltage to rise, ultimately resulting in Vo - VF = Vin. If the applied output voltage is high enough, causing the voltage on Vin to rise above the UVLO (undervoltage lockout) point / EN enable point, the buck circuit will activate, generating PWM and operating in a reverse boost mode. This increases the voltages on the SW and Vin terminals, potentially causing overvoltage breakdown and burnout. For example, in the following typical real-world scenarios, output energy will flow back into the input, causing the buck circuit to operate in reverse boost mode: 1. The downstream load of the buck circuit is light and the capacitor is heavily discharged. After the input is powered off, there is still residual voltage at the output, causing output energy to flow back into the input. 2. The downstream load of the buck circuit is a motor. When the input is not powered, the motor's rotation generates back EMF at the buck output, causing the buck output energy to flow back into the input.

[0004] There is currently no effective solution to the problem in related technologies where output energy flows back to the input, causing overvoltage breakdown of the Buck chip. Summary of the Invention

[0005] In this embodiment, a control circuit and a switching power supply with anti-backflow boost are provided to solve the problem in related technologies that output energy flows back to the input, causing overvoltage breakdown of the Buck chip.

[0006] In a first aspect, a control circuit for preventing backflow and boosting voltage is provided in this embodiment. The control circuit for preventing backflow and boosting voltage includes: a first comparison module, a delay module, and a false touch control module;

[0007] The first comparison module is connected to the Buck circuit and is used to sample and compare the input voltage and output voltage of the Buck circuit to obtain a first comparison signal;

[0008] The delay module is connected to the first comparison module and the false touch control module, and is used to delay the first comparison signal to obtain a delay signal;

[0009] The false touch control module is connected to the first comparison module and the Buck circuit, and is used to output a forced shutdown signal based on the first comparison signal and the delay signal to control the switching tube of the Buck circuit to turn off when backflow occurs in the Buck circuit.

[0010] In some of the embodiments, the anti-backflow boost control circuit further includes: a second comparison module;

[0011] The second comparison module is connected to the Buck circuit and the false touch control module, and is configured to output a verification signal to the false touch control module when the input voltage of the Buck circuit is less than the output voltage;

[0012] The false touch control module outputs a forced shutdown signal based on the first comparison signal, the delay signal, and the verification signal to control the switch tube of the Buck circuit to be turned off.

[0013] In some embodiments, the first comparison module includes: a first comparator and an inverter;

[0014] The positive input terminal of the first comparator is connected to the input voltage terminal of the Buck circuit, and the negative input terminal of the first comparator is connected to the output voltage terminal of the Buck circuit;

[0015] The output end of the first comparator is connected to the inverter and the delay module;

[0016] The inverter is also connected to the delay module and the second comparison module respectively.

[0017] In some embodiments, the delay module includes at least two D flip-flops and an OR gate;

[0018] The D flip-flops are connected in series in sequence, and the input end of the first D flip-flop is connected to the output end of the first comparator;

[0019] The output end of each of the D flip-flops is connected to the OR gate;

[0020] An enable terminal of each of the D flip-flops is connected to the inverter.

[0021] In some of the embodiments, the second comparison module includes: a second comparator and a latch;

[0022] The positive input terminal of the second comparator is connected to the output voltage terminal of the Buck circuit, and the negative input terminal of the second comparator is connected to the input voltage terminal of the Buck circuit; the enable terminal of the second comparator is connected to the inverter; and the output terminal of the second comparator is connected to the reset terminal of the latch;

[0023] The set end of the latch is connected to the delay module; the output end of the latch is connected to the false touch control module.

[0024] In some of the embodiments, the false touch control module includes: a NOR gate and a transistor;

[0025] The first input terminal of the NOR gate is connected to the first comparison module;

[0026] The second input end of the NOR gate is connected to the delay module;

[0027] The third input terminal of the NOR gate is connected to the second comparison module;

[0028] The output terminal of the NOR gate is connected to the first terminal of the transistor;

[0029] The second end of the transistor is connected to the Buck circuit;

[0030] The third terminal of the transistor is grounded.

[0031] In a second aspect, a switching power supply is provided in this embodiment, including: a Buck circuit and the anti-backfeed boost control circuit in the first aspect.

[0032] In some embodiments, the Buck circuit includes: a synchronous rectification module, a step-down control module, and a pulse modulation module;

[0033] The synchronous rectification module is used to convert the input voltage into a lower output voltage;

[0034] The pulse modulation module is connected to the step-down control module and is used to generate a PWM wave according to the output voltage and the reference voltage;

[0035] The step-down control module is connected to the synchronous rectification module and is used to generate a drive signal based on the PWM wave to control the switch tube in the synchronous rectification module;

[0036] The false touch control module of the anti-backfeed boost control circuit is also connected to the pulse modulation module, and is used to control the generation of the PWM wave based on the forced shutdown signal.

[0037] In some embodiments, the pulse modulation module includes: an error amplifier and a third comparator;

[0038] The first input terminal of the error amplifier is connected to the output voltage; the second input terminal of the error amplifier is connected to the reference voltage; the output terminal of the error amplifier is connected to the first input terminal of the third comparator;

[0039] The first input end of the third comparator is also connected to the output end of the false touch control module; the second input end of the third comparator is connected to the sampling current; and the output end of the third comparator is connected to the voltage reduction control module.

[0040] In some embodiments, the Buck circuit operates in a forced continuous conduction mode, and the forced continuous conduction mode is used to control the lower tube in the synchronous rectification module to be turned on under preset conditions.

[0041] Compared with related technologies, the anti-backfeed boost control circuit and switching power supply provided in this embodiment are connected to the Buck circuit through a first comparison module, which is used to sample and compare the input voltage and output voltage of the Buck circuit to obtain a first comparison signal; the delay module is connected to the first comparison module and the false touch control module, which is used to delay the first comparison signal to obtain a delayed signal; the false touch control module is connected to the first comparison module and the Buck circuit, which is used to output a forced shutdown signal based on the first comparison signal and the delay signal in the event of backfeed in the Buck circuit, so as to control the switching tube of the Buck circuit to turn off. This solves the problem of output energy flowing back to the input, causing overvoltage breakdown of the Buck circuit, and ensures the safety and reliability of the circuit.

[0042] The details of one or more embodiments of the present application are set forth in the following drawings and description to make other features, objects, and advantages of the present application more readily apparent. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0044] Figure 1A schematic diagram of the energy backflow path from output to input in the prior art;

[0045] Figure 2 This is a structural block diagram of a switching power supply in one embodiment of the present application;

[0046] Figure 3 This is a structural block diagram of a control circuit for preventing backflow and boosting voltage in one embodiment of the present application;

[0047] Figure 4 This is a circuit diagram of a control circuit for preventing backflow and boosting voltage in one embodiment of the present application;

[0048] Figure 5 This is a structural block diagram of a Buck circuit in one embodiment of the present application;

[0049] Figure 6 This is a circuit diagram of a Buck circuit in one embodiment of the present application;

[0050] Figure 7 This is a control logic diagram of the anti-backflow boost control circuit in the preferred embodiment of the present application.

[0051] Figure numerals: 100, Buck circuit; 110, synchronous rectification module; 120, step-down control module; 130, pulse modulation module; 200, anti-backflow boost control circuit; 210, first comparison module; 220, delay module; 230, false touch control module; 240, second comparison module. DETAILED DESCRIPTION

[0052] In order to more clearly understand the purpose, technical solutions and advantages of the present application, the present application is described and illustrated below in conjunction with the accompanying drawings and embodiments.

[0053] Unless otherwise defined, technical or scientific terms used in this application shall have the ordinary meanings as understood by persons of ordinary skill in the art to which this application belongs. The terms "a," "an," "the," "these," and similar expressions in this application do not denote limitations on quantity and may be singular or plural. The terms "comprise," "include," "have," and any variations thereof, as used in this application, are intended to cover non-exclusive inclusions. For example, a process, method, system, product, or device comprising a series of steps or modules (units) is not limited to the listed steps or modules (units) but may include unlisted steps or modules (units) or other steps or modules (units) inherent to the process, method, product, or device. The terms "connected," "connected," "coupled," and similar expressions used in this application are not limited to physical or mechanical connections but may include electrical connections, whether direct or indirect. As used in this application, "plurality" means two or more. "And / or" describes an association between associated objects, indicating that three possible relationships exist. For example, "A and / or B" can mean: A exists alone; A and B exist simultaneously; or B exists alone. Generally, the character " / " indicates that the objects in the preceding and following relationship are in an "or" relationship. The terms "first", "second", "third", etc. involved in this application are only used to distinguish similar objects and do not represent a specific ordering of the objects.

[0054] In this embodiment, a control circuit 200 for preventing backflow and boosting voltage is provided. Figure 2 The anti-backflow boost control circuit 200 is applied to a switching power supply and connected to the Buck circuit of the switching power supply. When the Buck circuit has backflow, the switch tube of the Buck circuit can be controlled to turn off in time, thereby avoiding the problem of false triggering of the Buck circuit and causing circuit damage. Figure 1 As shown, the Buck circuit in synchronous rectification + FCCM mode usually has Figure 1 In the structure shown in Figure 1, when no voltage is applied to the input terminal Vin and a voltage is applied to the output terminal Vo, with M1 and M2 closed, the output energy flows back into SW and then to the input through M1's body diode, causing the input voltage to rise, ultimately resulting in Vo - VF = Vin. If the applied output voltage is high enough, the voltage on Vin will rise above the UVLO undervoltage lockout point / EN enable point, causing the buck to activate and generate PWM, operating in a reverse boost state. The voltages on SW and Vin will rise synchronously, eventually exceeding the pin's withstand voltage and causing breakdown.

[0055] To address the above issues, the present embodiment provides an anti-backfeed boost control circuit 200. Without changing the original circuit architecture and control, it uses a simpler, more economical, and smaller supplementary control circuit to solve the problem of false triggering of the Buck circuit 100 due to backfeed, causing the Buck to operate in reverse boost mode.

[0056] In this embodiment, a control circuit 200 for preventing backflow and boosting voltage is provided. Figure 3 The anti-backflow boost control circuit 200 includes: a first comparison module 210, a delay module 220 and a false touch control module 230.

[0057] The first comparison module 210 is connected to the Buck circuit 100 and is used to sample and compare the input voltage and output voltage of the Buck circuit 100 to obtain a first comparison signal.

[0058] The delay module 220 is connected to the first comparison module 210 and the false touch control module 230 , and is configured to delay the first comparison signal to obtain a delayed signal.

[0059] The false touch control module 230 is connected to the first comparison module 210 and the Buck circuit 100, and is used to output a forced shutdown signal based on the first comparison signal and the delay signal to control the switch tube of the Buck circuit 100 to turn off when backflow occurs in the Buck circuit 100.

[0060] Specifically, when the output energy flows back to the input and the input voltage Vin is less than the output voltage Vo, the first comparison signal output by the first comparison module 210 is a low level; the first comparison signal outputs a low level after passing through the delay module 220; the false touch control module 230 outputs a forced shutdown signal to the Buck circuit 100 based on the two low-level signals, locking the PWM output, thereby turning off the switch tube. When the input voltage Vin>output voltage Vo, or the input voltage Vin≥output voltage Vo, the first comparison module 210 outputs a high level, which can control the subsequent modules to not work, thereby ensuring normal PWM output, that is, the anti-backflow boost control circuit 200 does not participate in the control. In other embodiments, the first comparison module 210 outputs a high level, and after passing through the delay module 220, the two high levels are input together to the false touch control module 230, and the false touch control module 230 decides not to generate a forced shutdown signal, thereby ensuring normal PWM output. The specific implementation method is not limited in this embodiment.

[0061] In this embodiment, a first comparison module 210 is connected to the Buck circuit 100 to sample and compare the input voltage and output voltage of the Buck circuit 100 to obtain a first comparison signal. A delay module 220 is connected to the first comparison module 210 and the false touch control module 230 to delay the first comparison signal to obtain a delayed signal. The false touch control module 230 is connected to the first comparison module 210 and the Buck circuit 100 to output a forced shutdown signal based on the first comparison signal and the delay signal in the event of backflow in the Buck circuit 100 to control the switching tube of the Buck circuit 100 to turn off, thereby solving the problem of output energy backflowing to the input, causing overvoltage breakdown of the Buck circuit 100, and ensuring the safety and reliability of the circuit.

[0062] In some of these embodiments, see Figure 3 The anti-backflow boost control circuit 200 further includes: a second comparison module 240.

[0063] The second comparison module 240 is connected to the Buck circuit 100 and the false touch control module 230 , and is configured to output a verification signal to the false touch control module 230 when the input voltage of the Buck circuit 100 is lower than the output voltage.

[0064] The false touch control module 230 outputs a forced shutdown signal based on the first comparison signal, the delay signal, and the verification signal to control the switch of the Buck circuit 100 to be turned off.

[0065] Specifically, when the output energy flows back to the input, and the input voltage Vin is less than the output voltage Vo, based on the first comparison signal, the delay signal and the verification signal, a forced shutdown signal is output, the PWM is locked and not output, thereby turning off the switch tube. When the input voltage Vin is greater than the output voltage Vo, or the input voltage Vin ≥ the output voltage Vo, the first comparison module 210 outputs a high level, which can control other modules not to work, thereby ensuring normal PWM output, that is, the anti-backflow boost control circuit 200 does not participate in the control. In other embodiments, when the input voltage Vin is greater than the output voltage Vo, or the input voltage Vin ≥ the output voltage Vo, the false touch control module 230 decides not to generate a forced shutdown signal based on the first comparison signal, the delay signal and the verification signal, thereby ensuring normal PWM output. The specific implementation method is not limited in this embodiment.

[0066] In this embodiment, the first comparison module 210 and the second comparison module 240 form a dual voltage monitoring system, thereby improving the circuit's recognition accuracy and response reliability for abnormal voltages.

[0067] In some of these embodiments, see Figure 4The first comparison module 210 includes: a first comparator U1 and an inverter U6.

[0068] The positive input terminal of the first comparator U1 is connected to the input voltage terminal of the Buck circuit 100 , and the negative input terminal of the first comparator U1 is connected to the output voltage terminal of the Buck circuit 100 . The output terminal of the first comparator U1 is connected to the inverter U6 and the delay module 220 .

[0069] The inverter U6 is further connected to the delay module 220 and the second comparison module 240 respectively.

[0070] Specifically, when Buck circuit 100 is operating normally, Vin > Vo, first comparator U1 outputs a high level (H). This level is then inverted, disabling second comparison module 240 and other subsequent modules. This effectively disables all modules except first comparator U1, reducing the static power consumption of the entire circuit. At this point, false-touch control module 230 does not generate a forced shutdown signal.

[0071] When the output energy flows back to the input and Vin<Vo, the first comparator U1 outputs a low level L, which is inverted to control the second comparison module 240 and other subsequent modules to start working (Enable).

[0072] When the Buck circuit 100 is powered on again and Vin > Vo, the first comparator U1 outputs a high level (H). After a level inversion, the second comparison module 240 and other subsequent modules are immediately disabled. This disables the anti-backfeed boost control circuit 200, disabling the circuit and returning the Buck circuit to normal operation. This allows for rapid and timely recovery from fault lockout, preventing the auxiliary control circuit from interfering with Buck operation.

[0073] In this embodiment, when the Buck circuit 100 is working normally, only the first comparison module 210 at the front stage is working, and the other modules are not working, which reduces the power consumption burden. After the fault is eliminated, it quickly returns to the normal state, and has high reliability.

[0074] In some of these embodiments, see Figure 4 The delay module 220 includes at least two D flip-flops and an OR gate U3.

[0075] The D flip-flops are connected in series, with the input of the first D flip-flop connected to the output of the first comparator U1. The output of each D flip-flop is connected to the OR gate U3. The enable terminal of each D flip-flop is connected to the inverter U6.

[0076] Specifically, the shift register (D1, D2, ..., DN) composed of D flip-flops ensures that the forced shutdown signal is generated only after the set clock delay time, effectively preventing false signal detection. The enable terminal of each flip-flop is connected to inverter U6, which can timely control its operating state and improve response speed.

[0077] In some of these embodiments, see Figure 4 The second comparison module 240 includes: a second comparator U2 and a latch U4.

[0078] The positive input of the second comparator U2 is connected to the output voltage of the Buck circuit 100, and the negative input of the second comparator U2 is connected to the input voltage of the Buck circuit 100. The enable terminal of the second comparator U2 is connected to the inverter U6. The output of the second comparator U2 is connected to the reset terminal of the latch U4. The set terminal of the latch U4 is connected to the delay module 220. The output of the latch U4 is connected to the false touch control module 230.

[0079] Specifically, when Vin is less than Vo, the first comparator U1 outputs a low level L, which enables the second comparator U2 and the delay module 220 after passing through the inverter U6; the delay module 220 then outputs a low level L, and the second comparator U2 outputs a high level H, then the reset terminal R of the latch U4 inputs 1, the set terminal S inputs 0, and the output terminal =0, at this time The signal controls the false touch control module 230 to output a forced shutdown signal.

[0080] In addition, this circuit can ensure that the forced shutdown signal is output after the required Clock delay time is set, which can effectively avoid false detection of the signal. Specifically, when Vin is detected to be less than Vo, but during the Clock delay time, the output of the delay module 220 remains at a high level H; after the second comparator U2 is enabled, the R terminal of the latch U4 changes from L to H. According to the latch truth table, Keep it at 1 (H); after the clock delay time is reached, the output of the OR gate is low level L, the S end of the latch U4 is L, and the R end is H. =0, the forced shutdown signal is output.

[0081] In this embodiment, the anti-interference function is implemented by the second comparator U2 and the latch U4, thereby increasing the robustness of the circuit.

[0082] In some of these embodiments, see Figure 4 The false touch control module 230 includes: a NOR gate U5 and a transistor M3.

[0083] A first input of NOR gate U5 is connected to first comparison module 210; a second input of NOR gate U5 is connected to delay module 220; and a third input of NOR gate U5 is connected to second comparison module 240. Specifically, a first input of NOR gate U5 is connected to the output of first comparator U1; a second input of NOR gate U5 is connected to OR gate U3; and a third input of NOR gate U5 is connected to latch U4.

[0084] The output terminal of the NOR gate U5 is connected to the first terminal of the transistor M3; the second terminal of the transistor M3 is connected to the Buck circuit 100; and the third terminal of the transistor M3 is grounded. The transistor M3 can be a field effect transistor or a bipolar junction transistor.

[0085] When multiple inputs of the NOR gate U5 (the first comparison signal, the delay signal, and the verification signal) are all at a low level L, the NOR gate U5 outputs a high level H, the control level of the transistor M3 is at a high level H, M3 is turned on, and the output terminal VCOMP is forced to be pulled low, that is, a forced shutdown signal is output.

[0086] In this embodiment, the output of the forced shutdown signal is implemented with a simple circuit structure through the NOR gate U5 and the transistor M3, thereby ensuring the reliability and fast response of the circuit.

[0087] This embodiment provides a switching power supply, comprising a Buck circuit 100 and a backfeed-proof boost control circuit 200 according to any of the above embodiments. The backfeed-proof boost control circuit 200 solves the overvoltage breakdown problem that can occur when energy backfeeds from the Buck circuit 100, thereby ensuring the safety and reliability of the switching power supply.

[0088] In some of these embodiments, see Figure 5 The Buck circuit 100 includes a synchronous rectification module 110 , a step-down control module 120 and a pulse modulation module 130 .

[0089] The synchronous rectifier module 110 is configured to convert the input voltage into a lower output voltage. The pulse modulation module 130 is connected to the step-down control module 120 and is configured to generate a PWM wave based on the output voltage and a reference voltage. The step-down control module 120 is also connected to the synchronous rectifier module 110 and is configured to generate a drive signal based on the PWM wave to control the switch in the synchronous rectifier module 110. The false-touch control module 230 of the anti-backfeed boost control circuit 200 is also connected to the pulse modulation module 130 and is configured to control the generation of the PWM wave based on a forced shutdown signal.

[0090] In some of these embodiments, see Figure 6The pulse modulation module 130 includes an error amplifier EA1 and a third comparator COM1. The first input of the error amplifier EA1 is connected to the output sampling voltage Vfb; the second input of the error amplifier EA1 is connected to the reference voltage Vref; the output of the error amplifier EA1 is connected to the first input of the third comparator COM1. The first input of the third comparator COM1 is also connected to the output VCOMP of the false touch control module 230; the second input of the third comparator COM1 is connected to the sampling current; and the output of the third comparator COM1 is connected to the step-down control module 120. Specifically,

[0091] In some embodiments, the synchronous rectifier module 110 includes an upper tube M1, a lower tube M2, an output capacitor Cout, an external inductor L1, and a feedback resistor unit. The first terminal of the upper tube M1 is connected to the drive unit of the buck control module 120, and the second terminal of the upper tube M1 is connected to the input voltage. The third terminal of the upper tube M1 is connected to the output voltage via the external inductor L1. The first terminal of the lower tube M2 is connected to the drive unit of the buck control module 120, and the second terminal of the lower tube M2 is connected to the third terminal of the upper tube M1. The third terminal of the lower tube M2 is grounded. One terminal of the output capacitor Cout is connected to the output voltage, and the other terminal of the output capacitor Cout is grounded. The feedback resistor unit is connected in parallel across the output capacitor Cout. The feedback resistor unit includes a first resistor R1 and a second resistor R2 connected in series. The first input terminal of the error amplifier EA1 is connected between the first resistor R1 and the second resistor R2 to obtain the output sample voltage Vfb. The upper tube M1 is a PMOS transistor, which is generally used in low-voltage applications for its low cost and simple driving. The lower tube M2 is an NMOS transistor (synchronous rectifier).

[0092] In some embodiments, the pulse modulation module 130 further includes: a current sampling module and a ramp compensation module; the compensation signal provided by the ramp compensation module acts on the output current of the current sampling module to obtain a sampling current, and the compensated sampling current is input into the second input terminal of the third comparator.

[0093] In some embodiments, the Buck circuit 100 operates in a forced continuous conduction mode, which is used to control the lower transistor in the synchronous rectifier module 110 to conduct under predetermined conditions. Specifically, in the FCCM mode, M2 can be turned on even after the inductor current crosses zero under light load conditions, allowing the inductor current to flow in a negative direction, i.e., forming a Vo-L1-M2-GND loop.

[0094] The present embodiment is described and illustrated below through preferred embodiments.

[0095] The circuit structure diagram of the Buck solution used in the switching power supply is as follows Figure 6As shown, M1 is the top-side PMOS transistor, which is generally used in low-voltage applications for its low cost and simple driving. M2 is the bottom-side NMOS transistor (synchronous rectifier). L1 is the external inductor; Cout is the output capacitor; R1 and R2 are output feedback resistors. EA1 is the error amplifier, which samples and amplifies the difference between the output voltage and the reference voltage. COM1 is the PWM comparator, which generates the PWM signal and, after logic control, outputs the drive signals for M1 and M2. Furthermore, in FCCM mode, M2 can be turned on even after the inductor current crosses zero at light loads, allowing the inductor current to flow in the negative direction, forming the Vo-L1-M2-GND loop.

[0096] As mentioned above, the synchronous rectification + FCCM mode buck has a flaw. Specifically, when there is no voltage applied to the input terminal Vin, voltage is applied to the output terminal Vo, and M1 and M2 are not turned on, the output energy will flow back into the SW and flow through the body diode of M1 to the input, causing the input voltage to rise, and ultimately Vo - VF = Vin. If the output voltage is high enough, the voltage on Vin will rise above the UVLO undervoltage point / EN enable point, and the buck will start to operate, issuing PWM, causing the buck to operate in a reverse boost state. The voltage on the SW and Vin will increase, which may cause the pin to overvoltage, break down, and burn out.

[0097] This preferred embodiment discloses a control circuit for solving the problem of output energy flowing back to the input in a low-voltage Buck converter in synchronous rectification + FCCM mode, thereby avoiding false triggering of the chip to operate in reverse Boost mode. Figure 4 Detailed circuit diagram of the anti-backflow boost control circuit 200. Figure 7 This is the implementation logic of the control circuit 200 for preventing backflow and boosting.

[0098] See also Figure 4 and Figure 7 The anti-backflow boost control circuit 200 includes a comparator 1 (U1), a comparator 2 (U2), a shift register (D1, D2...DN) composed of a D flip-flop, an OR gate (U3), an SR latch (U4), a NOR gate (U5), a switch tube (M3), and an inverter (U6).

[0099] The positive terminal of comparator 1 (U1) samples the input voltage Vin, and the negative terminal samples the output voltage Vo; the positive terminal of comparator 2 (U2) samples the output voltage Vo, and the negative terminal samples the input voltage Vin; the output terminal of comparator 1 is connected to the 1D terminal of the first D flip-flop (D1), and the output terminal of comparator 1 is also connected to the enable EN terminal of comparator 2 and the enable EN terminal of other modules through an inverter; multiple D flip-flops are connected in series, and the output Q1 of each D flip-flop is connected to the logic OR gate (U3) of the next level to achieve time delay; the output of comparator 2 (U2) is connected to the R terminal of the RS latch (U4), and the output of the logic OR gate (U3) is connected to the S terminal of the RS latch (U4) and the input of the NOR gate (U5); the RS latch output It is also connected to the input of the NOR gate (U5); the other input of the NOR gate (U5) is directly connected to the output of comparator 1 (U1); the NOR gate output signal controls the switch tube M3; the switch tube M3 is connected to the internally controlled VCOMP terminal.

[0100] During normal operation of the buck circuit, Vin > Vo, and comparator 1 (U1) outputs a high level (H). After inversion, this level controls comparator 2 (U2) and disables all subsequent modules. This effectively disables all modules except comparator 1 (U1), reducing the overall circuit's static power consumption. U5 outputs a low level (L), pulling M3's control level low, and this control circuit is not involved in the control.

[0101] When the output energy flows back to the input and Vin < Vo, comparator 1 (U1) outputs a low level L, which controls comparator 2 (U2), the subsequent shift register and other modules to enable after the level is inverted. After multiple internal clock cycles, the OR gate U3 outputs a low level L (U3). The specific number of clock cycles required for delay can be achieved by the number of series D flip-flops (you can also use a shift register directly to achieve the same function). Since Vin < Vo, comparator 2 (U2) outputs a high level H, then the S terminal of the RS latch U4 inputs 0 and the R terminal inputs 1, and the output =0, then the NOR gate (U5) outputs a high level, the control level of M3 is high level H, M3 is turned on, forcibly pulling down VCOMP, locking the PWM output, and the Buck power tube does not work, thus avoiding the reverse Boost misoperation. In addition, this circuit can ensure that the VCOMP signal is pulled low after the required Clock delay time is set, which can effectively avoid the misdetection of the signal, as follows: When Vin < Vo is detected, but during the Clock delay time, the output of the OR gate (U3) remains high level H, and the control level of M3 remains low; the R terminal of the RS latch changes from L to H after Enable. According to the latch truth table, Keep it at 1 (H); after the clock delay time is reached, the output of the OR gate is low level L, the S end of the RS latch is L, and the R end is H. =0, the VCOMP signal is pulled low.

[0102] When Vin > Vo (e.g., when the input is powered on), comparator 1 (U1) outputs a high level (H), immediately shutting down M3. Comparator 2 (U2), the shift register, and other modules are disabled. This control circuit disengages control, and the Buck converter enters normal operation. This allows for rapid and timely recovery from fault lockout to normal operation, preventing the auxiliary control circuit from interfering with Buck operation.

[0103] In this preferred embodiment, the Buck input Vin and output Vo voltages are detected. When the output energy feeds back to the input (Vo > Vin), the PWM is forcibly shut down, locking the upper and lower transistors off. This prevents the Buck from accidentally triggering the reverse Boost state. Once the fault is resolved, the system can quickly resume normal operation. This preferred embodiment uses the first-level comparator 1 to control the enable / disable of other modules. During normal operation, only comparator 1 operates, while other modules do not, reducing overall circuit power consumption. Furthermore, comparator 2 and the SR latch are combined to lock the PWM off, preventing interference and increasing circuit robustness.

[0104] It should be understood that the specific embodiments described herein are only used to explain this application and are not used to limit it. Based on the embodiments provided in this application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0105] Obviously, the accompanying drawings are merely examples or embodiments of the present application. A person skilled in the art can also apply the present application to other similar situations based on these drawings without inventive effort. Furthermore, it is understandable that, although the work involved in this development process may be complex and lengthy, certain design, manufacturing, or production changes based on the technical content disclosed in this application are merely routine technical means for a person skilled in the art and should not be considered to constitute a deficiency in the disclosure of the present application.

[0106] The term "embodiment" as used in this application refers to specific features, structures, or characteristics described in conjunction with the embodiment that can be included in at least one embodiment of this application. The appearance of this phrase in various places in the specification does not necessarily mean that the embodiment is the same, nor does it mean that it is mutually exclusive with other embodiments and is independent or optional. It is understood, either explicitly or implicitly, by those skilled in the art that the embodiments described in this application can be combined with other embodiments when there is no conflict.

[0107] The above-described embodiments merely represent several implementation methods of the present application. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of patent protection. It should be noted that a person of ordinary skill in the art may make various modifications and improvements without departing from the spirit of the present application, and these modifications and improvements fall within the scope of protection of the present application. Therefore, the scope of protection of the present application shall be determined by the appended claims.

Claims

1. A control circuit for preventing backflow and boosting voltage, characterized in that: The anti-backflow boost control circuit includes: a first comparison module, a delay module and a false touch control module; The first comparison module is connected to the Buck circuit and is used to sample and compare the input voltage and output voltage of the Buck circuit to obtain a first comparison signal; The delay module is connected to the first comparison module and the false touch control module, and is used to delay the first comparison signal to obtain a delay signal; The false touch control module is connected to the first comparison module and the Buck circuit, and is used to output a forced shutdown signal based on the first comparison signal and the delay signal to control the switching tube of the Buck circuit to turn off when backflow occurs in the Buck circuit.

2. The anti-backflow boost control circuit according to claim 1, characterized in that: The anti-backflow boost control circuit further includes: a second comparison module; The second comparison module is connected to the Buck circuit and the false touch control module, and is configured to output a verification signal to the false touch control module when the input voltage of the Buck circuit is less than the output voltage; The false touch control module outputs a forced shutdown signal based on the first comparison signal, the delay signal, and the verification signal to control the switch tube of the Buck circuit to be turned off.

3. The anti-backflow boost control circuit according to claim 2, characterized in that: The first comparison module includes: a first comparator and an inverter; The positive input terminal of the first comparator is connected to the input voltage terminal of the Buck circuit, and the negative input terminal of the first comparator is connected to the output voltage terminal of the Buck circuit; The output end of the first comparator is connected to the inverter and the delay module; The inverter is also connected to the delay module and the second comparison module respectively.

4. The anti-backflow boost control circuit according to claim 3, characterized in that: The delay module includes at least two D flip-flops and an OR gate; The D flip-flops are connected in series in sequence, and the input end of the first D flip-flop is connected to the output end of the first comparator; The output terminal of each D flip-flop is connected to the OR gate; An enable terminal of each of the D flip-flops is connected to the inverter.

5. The anti-backflow boost control circuit according to claim 3, characterized in that: The second comparison module includes: a second comparator and a latch; The positive input terminal of the second comparator is connected to the output voltage terminal of the Buck circuit, and the negative input terminal of the second comparator is connected to the input voltage terminal of the Buck circuit; the enable terminal of the second comparator is connected to the inverter; and the output terminal of the second comparator is connected to the reset terminal of the latch; The set end of the latch is connected to the delay module; the output end of the latch is connected to the false touch control module.

6. The anti-backflow boost control circuit according to claim 2, characterized in that: The false touch control module includes: a NOR gate and a transistor; The first input terminal of the NOR gate is connected to the first comparison module; The second input end of the NOR gate is connected to the delay module; The third input terminal of the NOR gate is connected to the second comparison module; The output terminal of the NOR gate is connected to the first terminal of the transistor; The second end of the transistor is connected to the Buck circuit; The third terminal of the transistor is grounded.

7. A switching power supply, characterized in that: include: A Buck circuit and a backfeed-proof boost control circuit according to any one of claims 1 to 6.

8. The switching power supply according to claim 7, characterized in that: The Buck circuit includes: a synchronous rectification module, a step-down control module and a pulse modulation module; The synchronous rectification module is used to convert the input voltage into a lower output voltage; The pulse modulation module is connected to the step-down control module and is used to generate a PWM wave according to the output voltage and the reference voltage; The step-down control module is connected to the synchronous rectification module and is used to generate a drive signal based on the PWM wave to control the switch tube in the synchronous rectification module; The false touch control module of the anti-backfeed boost control circuit is also connected to the pulse modulation module, and is used to control the generation of the PWM wave based on the forced shutdown signal.

9. The switching power supply according to claim 8, characterized in that: The pulse modulation module includes: an error amplifier and a third comparator; The first input terminal of the error amplifier is connected to the output voltage; the second input terminal of the error amplifier is connected to the reference voltage; the output terminal of the error amplifier is connected to the first input terminal of the third comparator; The first input end of the third comparator is also connected to the output end of the false touch control module; the second input end of the third comparator is connected to the sampling current; and the output end of the third comparator is connected to the voltage reduction control module.

10. The switching power supply according to claim 7, characterized in that: The Buck circuit operates in a forced continuous conduction mode, which is used to control the lower tube in the synchronous rectification module to be turned on under preset conditions.

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