Protection circuit and chip

Abstract

The embodiment of the invention provides a protection circuit and a chip, and the circuit comprises a first transistor which is used for switching off when a surge occurs at a power input end, and discharging a surge current to a first overvoltage protection module; the second transistor is used for being turned off when the power supply output end generates surge and discharging surge current to the first overvoltage protection module; and the first overvoltage protection module is used for discharging surge current passing through the first transistor or the second transistor. By arranging the second transistor, the surge current can be discharged to the first overvoltage protection module when the surge is generated at the power supply output end, so that the discharge of the surge generated at the power supply output end is supported.

Description

Technical Field

[0001] The present application relates to the field of circuit technology, and in particular to a protection circuit and chip. Background Art

[0002] In the integrated circuit field, there is a class of devices called overvoltage protection load switches. These devices manage input voltage by controlling the switch. When an inrush current appears at the input, and the input voltage is too high, the switch turns off, dissipating the inrush current.

[0003] The current protection method mainly involves placing a surge relief circuit or device at the input port to provide overvoltage protection and surge relief for the input port.

[0004] However, in the current protection method, when the output port encounters high voltage or surge impact, overvoltage protection or surge current discharge cannot be performed. Summary of the Invention

[0005] In view of this, embodiments of the present application provide a protection circuit and chip to at least partially solve the above-mentioned problems.

[0006] According to a first aspect of an embodiment of the present application, a protection circuit is provided, including: a first transistor, configured to shut down when a surge is generated at a power input terminal and discharge the surge current to a first overvoltage protection module; a second transistor, configured to shut down when a surge is generated at a power output terminal and discharge the surge current to the first overvoltage protection module; and the first overvoltage protection module, configured to discharge the surge current passing through the first transistor or the second transistor.

[0007] In one possible implementation, the first overvoltage protection module includes: a first surge voltage suppressor; the output end of the first surge voltage suppressor is connected to the drain of the first transistor and the drain of the second transistor, and the input end of the first surge voltage suppressor is grounded; the first surge voltage suppressor is used to discharge the surge current after being broken down by the surge current.

[0008] In one possible implementation, the first overvoltage protection module includes: a second surge voltage suppressor, a first resistor, and at least one first switch; the output end of the second surge voltage suppressor is connected to the drain of the first transistor and the drain of the second transistor, the input end of the second surge voltage suppressor is connected to the control end of the at least one first switch and the first end of the first resistor, the second end of the first resistor is grounded, the first end of the at least one first switch is connected to the drain of the first transistor and the drain of the second transistor, and the second end of the at least one first switch is grounded; the second surge voltage suppressor is used to discharge the surge current to the at least one first switch after being broken down by the surge current, so as to close the at least one first switch; the at least one first switch is used to discharge the surge current after being closed.

[0009] In a possible implementation, the first switch is a transistor, the control end of the first switch is a gate, the first end of the first switch is a drain, and the second end of the first switch is a source.

[0010] In a possible implementation, a breakdown voltage of the first surge voltage suppressor is smaller than a breakdown voltage of the first transistor and a breakdown voltage of the second transistor.

[0011] In a possible implementation, the first transistor and the second transistor are transistors of the same type.

[0012] In a possible implementation, the first switch is a transistor; and at least two of the first transistor, the second transistor, and the first switch are transistors of the same type.

[0013] According to a second aspect of an embodiment of the present application, a protection circuit is provided, comprising: a third transistor and a second overvoltage protection module; the third transistor is configured to be turned off when a surge is generated at the power input end or the power output end, and to discharge the surge current to the second overvoltage protection module; the second overvoltage protection module comprises: a third surge voltage suppressor, a second resistor and at least one second switch; the output end of the third surge voltage suppressor is connected to the drain of the third transistor, the input end of the third surge voltage suppressor is connected to the control end of the at least one second switch and the first end of the second resistor, the second end of the second resistor is grounded, the first end of the at least one second switch is connected to the drain of the third transistor, and the second end of the at least one second switch is grounded; the third surge voltage suppressor is configured to discharge the surge current to the at least one second switch after being broken down by the surge current, so as to close the at least one second switch; the at least one second switch is configured to discharge the surge current after being closed.

[0014] In one possible implementation, the second switch is a transistor, the control end of the second switch is a gate, the first end of the second switch is a drain, and the second end of the second switch is a source.

[0015] According to a third aspect of an embodiment of the present application, a chip is provided, comprising the protection circuit described in any one of the first aspect of the embodiment.

[0016] In one possible implementation, the protection circuit includes a first overvoltage protection module comprising: a second surge voltage suppressor, a first resistor, and at least one first switch; an output end of the second surge voltage suppressor is connected to the drain of the first transistor and the drain of the second transistor, an input end of the second surge voltage suppressor is connected to the control end of the at least one first switch and the first end of the first resistor, a second end of the first resistor is grounded, a first end of the at least one first switch is connected to the drain of the first transistor and the drain of the second transistor, and a second end of the at least one first switch is grounded; the second surge voltage suppressor is configured to discharge surge current to the at least one first switch after being broken down by surge current, so as to close the at least one first switch; the at least one first switch is configured to discharge surge current after being closed; at least two of the first transistor, the second transistor, and the at least one first switch in the chip are located on a first die, and the drain of the first transistor, the drain of the second transistor, and the first end of the at least one first switch located on the first die share a package pin included in the first die.

[0017] According to a fourth aspect of an embodiment of the present application, a chip is provided, comprising the protection circuit described in the second aspect of the embodiment.

[0018] In one possible implementation, the third transistor and at least one second switch in the chip are located on a second die, and the drain of the third transistor and the first end of the at least one second switch located on the second die share a package pin included in the die.

[0019] It can be seen from the above technical solution that by providing the second transistor, when a surge occurs at the power output end, the surge current can be discharged to the first overvoltage protection module, thereby supporting the discharge of the surge generated at the power output end. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments recorded in the embodiments of the present application. For ordinary technicians in this field, other drawings can also be obtained based on these drawings.

[0021] Figure 1 It is a schematic diagram of a protection circuit;

[0022] Figure 2 It is a schematic diagram of input voltage and output voltage during surge discharge;

[0023] Figure 3 is a schematic diagram of a protection circuit provided in an embodiment of the present application;

[0024] Figure 4 is a schematic diagram of a protection circuit including a first surge voltage suppressor provided by an embodiment of the present application;

[0025] Figure 5 is a schematic diagram of a protection circuit including a second surge voltage suppressor provided in an embodiment of the present application;

[0026] Figure 6 is a schematic diagram of another protection circuit provided in an embodiment of the present application;

[0027] Figure 7 This is a schematic diagram of another protection circuit provided in an embodiment of the present application. DETAILED DESCRIPTION

[0028] In order to enable those skilled in the art to better understand the technical solutions in the embodiments of the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the embodiments of the present application, all other embodiments obtained by ordinary technicians in this field should fall within the scope of protection of the embodiments of the present application.

[0029] The terms used in this application are for the purpose of describing specific embodiments only and are not intended to limit this application. As used in this application and the appended claims, the singular forms "a," "an," "the," and "the" are intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the term "and / or" as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items.

[0030] It should be understood that although the terms first, second, third, etc. may be used in this application to describe various information, such information should not be limited to these terms. These terms are only used to distinguish information of the same type from each other. For example, without departing from the scope of this application, first information may also be referred to as second information, and similarly, second information may also be referred to as first information. Depending on the context, the word "if" as used herein may be interpreted as "at the time of" or "when" or "in response to determining".

[0031] The following is an explanation of the terms that appear in this article: TVS: Transient Voltage Suppressor.

[0032] Figure 1 It is a schematic diagram of a protection circuit, such as Figure 1 As shown in the figure, in order to protect the chip, a protection circuit is installed at the power input end. The protection circuit consists of a TVS and a MOS tube. The output end of the TVS is connected to the drain of the MOS tube, and the input end of the TVS is grounded. When a surge current appears at the input end IN and the input voltage is too high, the MOS tube is turned off. At this time, the surge current breaks through the TVS and discharges the surge current through the TVS. During this process, the input voltage at the input end IN and the output voltage at the output end OUT are as follows: Figure 2 As shown in the figure, it can be seen that the output voltage will not be too high, thereby protecting the back-end chip. However, inrush current may also be generated at the output terminal OUT. If inrush current is generated at the output terminal OUT, even if the MOS tube is turned off, there is no discharge branch when the inrush current is input from the source of the MOS tube. In addition, the MOS tube has poor voltage resistance when input from the source, which can easily cause damage.

[0033] Therefore, the present application provides a protection circuit and chip to at least partially solve the above problems.

[0034] Figure 3 is a schematic diagram of a protection circuit provided in an embodiment of the present application, such as Figure 3 As shown, the protection circuit 100 includes: a first transistor 101, which is used to shut down when a surge occurs at the power input terminal and discharge the surge current to a first overvoltage protection module 103. A second transistor 102, which is used to discharge the surge current to the first overvoltage protection module 103 when a surge occurs at the power output terminal. The first overvoltage protection module 103 is used to discharge the surge current passing through the first transistor or the second transistor.

[0035] When an inrush current occurs at the input terminal IN and the input voltage is too high, the first transistor 101 is turned off, and the inrush current breaks down the first overvoltage protection module 103, and the inrush current is discharged through the first overvoltage protection module 103. When an inrush current occurs at the output terminal OUT and the output voltage is too high, the second transistor 102 is turned off, and the inrush current is discharged through the first overvoltage protection module 103.

[0036] Specifically, the first transistor 101 and the second transistor 102 may be transistors of the same type. When the first transistor 101 and the second transistor 102 have the same voltage withstand capability and discharge capability, it is convenient to describe the parameters of a product including the protection circuit 100 .

[0037] The present application provides the second transistor 102 so that when a surge occurs at the power output end, the surge current can be discharged to the first overvoltage protection module 103 , thereby supporting the discharge of the surge generated at the power output end.

[0038] Figure 4 is a schematic diagram of a protection circuit including a first surge voltage suppressor provided by an embodiment of the present application, such as Figure 4 As shown, the first overvoltage protection module 103 includes: a first surge voltage suppressor 1031 .

[0039] The output terminal of the first surge voltage suppressor 1031 is connected to the drain of the first transistor 101 and the drain of the second transistor 102, and the input terminal of the first surge voltage suppressor 1031 is grounded. The first surge voltage suppressor 1031 is used to discharge the surge current after being broken down by the surge current.

[0040] The first overvoltage protection module 103 may only include a first surge voltage suppressor 1031. When a surge current occurs at the input terminal IN and the input voltage is too high, or a surge current occurs at the output terminal OUT and the output voltage is too high, the first surge voltage suppressor 1031 will be broken down to discharge the surge current.

[0041] Specifically, the breakdown voltage of the first surge voltage suppressor 1031 is smaller than the breakdown voltage of the first transistor 101 and the breakdown voltage of the second transistor 102 .

[0042] After the first transistor 101 and the second transistor 102 are turned off, they need to have sufficient voltage resistance, otherwise the first transistor 101 and the second transistor 102 will discharge surge current to the power input end or the power output end after being broken down. Therefore, the voltage resistance of the first transistor 101 and the voltage resistance of the second transistor 102 should be greater than the voltage resistance of the first surge voltage suppressor 1031 to ensure that when a surge occurs at the power input end or the power output end, the first transistor 101 or the second transistor 102 can normally isolate the surge, and the surge current is discharged by breaking down the first surge voltage suppressor 1031.

[0043] Figure 5 is a schematic diagram of a protection circuit including a second surge voltage suppressor provided by an embodiment of the present application, such as Figure 5As shown, the first overvoltage protection module 103 includes: a second surge voltage suppressor 1032, a first resistor 1033, and at least one first switch 1034. The output end of the second surge voltage suppressor 1032 is connected to the drain of the first transistor 101 and the drain of the second transistor 102, the input end of the second surge voltage suppressor 1032 is connected to the control end of the at least one first switch 1034 and the first end of the first resistor 1033, the second end of the first resistor 1033 is grounded, the first end of the at least one first switch 1034 is connected to the drain of the first transistor 101 and the drain of the second transistor 101, and the second end of the at least one first switch 1034 is grounded.

[0044] The second surge voltage suppressor 1032 is configured to discharge the surge current to the at least one first switch 1034 after being broken down by the surge current, so as to close the at least one first switch 1034. The at least one first switch 1034 is configured to discharge the surge current after being closed.

[0045] The first overvoltage protection module 103 may include a second surge voltage suppressor 1032, a first resistor 1033 and at least one first switch 1034. When a surge current occurs at the input terminal IN and the input voltage is too high, or when a surge current occurs at the output terminal OUT and the output voltage is too high, the second surge voltage suppressor 1032 is broken down, thereby turning on the first switch 1034 and discharging the surge current through the first switch 1034. After the second surge voltage suppressor 1032 is broken down, the first resistor 1033 can also discharge a small portion of the surge current.

[0046] Specifically, the first switch 1034 is a transistor, the control end of the first switch 1034 is the gate, the first end of the first switch 1034 is the drain, and the second end of the first switch 1034 is the source. The first switch 1034 can be a device with switching capability such as a MOS tube or a transistor.

[0047] In addition, from Figure 2 It can be seen from the figure that after the TVS is broken down, its clamping ability is unstable, causing VOUT to fluctuate during the process of discharging the surge current. However, the first switch 1034 has strong discharge ability and voltage resistance, and clamping through the first switch 1034 can be more stable.

[0048] Specifically, the first switch 1034 is a transistor.

[0049] At least two of the first transistor 101, the second transistor 102, and the first switch 1034 are transistors of the same type. For example, the first transistor 101 and the first switch 1034 are transistors of the same type, or the second transistor 102 and the first switch 1034 are transistors of the same type, or the first transistor 101, the second transistor 102, and the first switch 1034 are transistors of the same type.

[0050] The present application can improve the surge current discharge capability and the accuracy of the clamping voltage by providing the first switch 1034 .

[0051] Figure 6 is a schematic diagram of another protection circuit provided in an embodiment of the present application, Figure 7 This is a schematic diagram of another protection circuit provided in an embodiment of the present application, such as Figure 6-7 As shown, the protection circuit 200 includes: a third transistor 201 and a second overvoltage protection module 202 .

[0052] The third transistor 201 is configured to shut down when a surge occurs at the power input or output, and discharge the surge current to the second overvoltage protection module 202. The second overvoltage protection module 202 includes a third surge voltage suppressor 2021, a second resistor 2022, and at least one second switch 2023. The output of the third surge voltage suppressor 2021 is connected to the drain of the third transistor 201. The input of the third surge voltage suppressor 2021 is connected to the control terminal of the at least one second switch 2023 and the first terminal of the second resistor 2022. The second terminal of the second resistor 2022 is grounded. The first terminal of the at least one second switch 2023 is connected to the drain of the third transistor 201, and the second terminal of the at least one second switch 2023 is grounded. After being broken down by the surge current, the third surge voltage suppressor 2021 is configured to discharge the surge current to the at least one second switch 2023, thereby closing the at least one second switch 2023. The at least one second switch 2023 is configured to discharge the surge current after closing.

[0053] The third transistor 201 can be positioned as required. For example, if it is used to prevent surges at the power input, the third transistor 201 can be positioned as follows: Figure 6 As shown, it is arranged between the power input terminal and the second overvoltage protection module 202. When a surge current appears at the input terminal IN and the input voltage is too high, the third surge voltage suppressor 2021 is broken down, thereby turning on the second switch 2023 and discharging the surge current through the second switch 2023. After the third surge voltage suppressor 2021 is broken down, the second resistor 2022 can also discharge a small part of the surge current. If used to prevent surges at the power output terminal, the third transistor 201 can also be as shown. Figure 7As shown, it is arranged between the power supply output end and the second overvoltage protection module 202. When a surge current appears at the output end OUT, the third surge voltage suppressor 2021 is broken down, thereby turning on the second switch 2023 and discharging the surge current through the second switch 2023. After the third surge voltage suppressor 2021 is broken down, the second resistor 2022 can also discharge a small part of the surge current.

[0054] Specifically, the second switch 2023 is a transistor, the control end of the second switch 2023 is the gate, the first end of the second switch 2023 is the drain, and the second end of the second switch 2023 is the source. The second switch 2023 can be a device with switching capability such as a MOS tube or a transistor.

[0055] The present application can improve the surge current discharge capability and the accuracy of the clamping voltage by providing at least one second switch 2023 in the second overvoltage protection module 202 .

[0056] A third aspect of the present application provides a chip, comprising the protection circuit 100 in the aforementioned embodiment.

[0057] Specifically, the first overvoltage protection module included in the protection circuit 100 includes: a second surge voltage suppressor, a first resistor and at least one first switch; the output end of the second surge voltage suppressor is connected to the drain of the first transistor and the drain of the second transistor, the input end of the second surge voltage suppressor is connected to the control end of at least one first switch and the first end of the first resistor, the second end of the first resistor is grounded, the first end of at least one first switch is connected to the drain of the first transistor and the drain of the second transistor, and the second end of at least one first switch is grounded.

[0058] The second surge voltage suppressor is used to discharge the surge current to the at least one first switch after being broken down by the surge current, so as to close the at least one first switch. The at least one first switch is used to discharge the surge current after being closed. At least two of the first transistor, the second transistor and the at least one first switch in the chip are located on the first bare die. The drain of the first transistor, the drain of the second transistor and the first end of the at least one first switch located on the first bare die share a package pin included in the first bare die.

[0059] According to the relevant description of the protection circuit 100, it can be understood that the drains of the first transistor and the second transistor are connected. When the first switch is a transistor, the drain of the first switch is also connected to the drains of the first transistor and the second transistor. Therefore, at least two of the first transistor, the second transistor, and the at least one first switch can be arranged on the same die, which is more convenient when the chip is packaged. For example, when the first transistor and the second transistor are arranged on the first die, the drain of the first transistor and the drain of the second transistor share a package pin included in the first die. When the first transistor and the at least one first switch are arranged on the first die, the drain of the first transistor and the first end of the at least one first switch share a package pin included in the first die. When the second transistor and the at least one first switch are arranged on the first die, the drain of the second transistor and the first end of the at least one first switch share a package pin included in the first die. When the first transistor, the second transistor, and the at least one first switch are all arranged on the first die, the drain of the first transistor, the drain of the second transistor, and the first end of the at least one first switch share a package pin included in the first die.

[0060] The specific implementation of the protection circuit 100 in the chip can be found in the corresponding descriptions of the corresponding components and connections in the aforementioned embodiment of the protection circuit 100, and will not be repeated here. Those skilled in the art will clearly understand that for the sake of convenience and brevity, the specific operating processes of the various components described above can refer to the corresponding process descriptions in the aforementioned embodiment of the protection circuit 100, and will not be repeated here.

[0061] A fourth aspect of the present application provides a chip, comprising the protection circuit 200 in the aforementioned embodiment.

[0062] Specifically, the third transistor and the at least one second switch in the chip are located on the second die, and the drain of the third transistor and the first end of the at least one second switch located on the second die share a package pin included in the second die.

[0063] According to the relevant description of the aforementioned protection circuit 200, it can be understood that when the second switch is a transistor, the drain of the second switch is connected to the first end of the third transistor. Therefore, the third transistor and at least one second switch can be arranged on the same die, and the drain of the second switch and the first end of the third transistor share a package pin included in the die, which is more convenient when packaging the chip.

[0064] The specific implementation of the protection circuit 200 in the chip can be found in the corresponding descriptions of the corresponding components and connections in the aforementioned embodiment of the protection circuit 200, and will not be repeated here. Those skilled in the art will clearly understand that for the sake of convenience and brevity, the specific operating processes of the various components described above can refer to the corresponding process descriptions in the aforementioned embodiment of the protection circuit 200, and will not be repeated here.

[0065] It should be noted that, under the premise of no conflict, the various embodiments and / or the technical features in each embodiment described in this application can be arbitrarily combined with each other, and the technical solution obtained after the combination should also fall within the scope of protection of this application.

[0066] It should be understood that the specific examples in the embodiments of the present application are only to help those skilled in the art to better understand the embodiments of the present application, rather than to limit the scope of the embodiments of the present application. Those skilled in the art can make various improvements and modifications based on the above embodiments, and these improvements or modifications all fall within the scope of protection of the present application.

[0067] The above description is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this application should be included in the scope of protection of this application. Therefore, the scope of protection of this application should be based on the scope of protection of the claims.

Claims

1. A protection circuit, characterized in that: include: A first transistor is configured to be turned off when a surge occurs at the power input terminal, and to discharge the surge current to the first overvoltage protection module; a second transistor, configured to shut down when a surge occurs at the power output terminal and discharge the surge current to the first overvoltage protection module; The first overvoltage protection module is configured to discharge a surge current passing through the first transistor or the second transistor.

2. The protection circuit according to claim 1, wherein: The first overvoltage protection module includes: a first surge voltage suppressor; The output terminal of the first surge voltage suppressor is connected to the drain of the first transistor and the drain of the second transistor, and the input terminal of the first surge voltage suppressor is grounded; The first surge voltage suppressor is used to discharge the surge current after being broken down by the surge current.

3. The protection circuit according to claim 1, wherein: The first overvoltage protection module includes: a second surge voltage suppressor, a first resistor and at least one first switch; an output terminal of the second surge voltage suppressor connected to the drain of the first transistor and the drain of the second transistor, an input terminal of the second surge voltage suppressor connected to the control terminal of the at least one first switch and the first terminal of the first resistor, a second terminal of the first resistor being grounded, a first terminal of the at least one first switch being connected to the drain of the first transistor and the drain of the second transistor, and a second terminal of the at least one first switch being grounded; The second surge voltage suppressor is configured to discharge the surge current to the at least one first switch after being broken down by the surge current, so as to close the at least one first switch; The at least one first switch is configured to discharge surge current after being closed.

4. The protection circuit according to claim 3, wherein: The first switch is a transistor, the control end of the first switch is a gate, the first end of the first switch is a drain, and the second end of the first switch is a source.

5. The protection circuit according to claim 2, wherein: A breakdown voltage of the first surge voltage suppressor is smaller than a breakdown voltage of the first transistor and a breakdown voltage of the second transistor.

6. The protection circuit according to claim 1, wherein: The first transistor and the second transistor are transistors of the same type.

7. The protection circuit according to claim 3, wherein: The first switch is a transistor; At least two of the first transistor, the second transistor, and the first switch are transistors of the same type.

8. A protection circuit, characterized in that: include: a third transistor and a second overvoltage protection module; The third transistor is configured to be turned off when a surge occurs at the power input terminal or the power output terminal, and to discharge the surge current to the second overvoltage protection module; The second overvoltage protection module includes: a third surge voltage suppressor, a second resistor and at least one second switch; The output terminal of the third surge voltage suppressor is connected to the drain of the third transistor, the input terminal of the third surge voltage suppressor is connected to the control terminal of the at least one second switch and the first terminal of the second resistor, the second terminal of the second resistor is grounded, the first terminal of the at least one second switch is connected to the drain of the third transistor, and the second terminal of the at least one second switch is grounded; The third surge voltage suppressor is configured to discharge the surge current to the at least one second switch after being broken down by the surge current, so as to close the at least one second switch; The at least one second switch is used to discharge surge current after being closed.

9. The protection circuit according to claim 8, wherein: The second switch is a transistor, the control end of the second switch is a gate, the first end of the second switch is a drain, and the second end of the second switch is a source.

10. A chip, characterized in that: The protective circuit comprises the protection circuit according to any one of claims 1 to 7.

11. The chip according to claim 10, wherein: The protection circuit includes a first overvoltage protection module including: a second surge voltage suppressor, a first resistor, and at least one first switch; an output end of the second surge voltage suppressor is connected to the drain of the first transistor and the drain of the second transistor, an input end of the second surge voltage suppressor is connected to the control end of the at least one first switch and the first end of the first resistor, a second end of the first resistor is grounded, a first end of the at least one first switch is connected to the drain of the first transistor and the drain of the second transistor, and a second end of the at least one first switch is grounded; The second surge voltage suppressor is configured to discharge the surge current to the at least one first switch after being broken down by the surge current, so as to close the at least one first switch; The at least one first switch is configured to discharge surge current after closing; At least two of the first transistor, the second transistor and the at least one first switch in the chip are located on a first die, and the drain of the first transistor, the drain of the second transistor and the first end of the at least one first switch located on the first die share a package pin included in the first die.

12. A chip, characterized in that: The invention comprises the protection circuit described in claims 8-9.

13. The chip according to claim 12, wherein: The third transistor and at least one second switch in the chip are located on a second die, and a drain of the third transistor and a first end of the at least one second switch located on the second die share a package pin included in the die.

Images