Control method for eliminating phase shift noise of FOC single resistor

Abstract

The invention discloses a control method for eliminating phase shift noise of an FOC single resistor. The method comprises the steps that a PWM module is provided with a comparison register A and a comparison register B according to the duty ratio, and the value CMPA of the comparison register A and the value CMPB of the comparison register B are arranged at any position of a PWM period. When the vector is low, the three-phase PWM is translated to the leftmost side or the right side, one side of the three-phase PWM forms a step type, and the other side of the three-phase PWM is a modulation area, so when the vector is high, the PWM control mode needs to be switched, the PWM is translated to the leftmost side or the right side, one side of the three-phase PWM is aligned and is not changed, and the other side of the three-phase PWM is the modulation area. According to the invention, different PWM control modes are respectively adopted in two different stages of a low vector and a high vector, so that the problem of electromagnetic noise caused by phase shift in the starting and operation processes is effectively solved, and the purpose of reducing the product cost is achieved.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of motor control technology, and in particular to a control method for eliminating FOC single resistor phase shift noise. Background Art

[0002] Field-Oriented Control (FOC) operation requires obtaining three-phase operating currents, typically using a three- or two-resistor approach. To reduce cost and circuit size, a single-resistor circuit is often used. To obtain phase currents, a single resistor must sample the currents twice within a single PWM cycle to obtain the two-phase currents. The third-phase current can be calculated using the current law for the energized node: Ia + Ib + Ic = 0.

[0003] The drawback of single-resistor sampling is that when the vector is small or two-phase currents intersect, the corresponding three-phase PWM duty cycles may be slightly different or even the same, making it impossible to obtain phase currents. To address this issue, PWM phase shifting is commonly used. This involves shifting the two-phase PWM waveforms left and right, respectively, to provide sufficient sampling space for current acquisition.

[0004] However, the addition of phase shifting introduces some distorted signals and harmonics into the current, which can introduce noise after sampling. Phase shifting also disrupts the symmetry of the PWM waveform, causing uneven distribution of the voltage vector in the time domain. This can cause harmonic distortion in the motor's air gap magnetic field, resulting in audible electromagnetic noise such as high-frequency whistling. Summary of the Invention

[0005] In order to solve the problems in the prior art, the present invention provides a control method for eliminating FOC single-resistor phase-shift noise. Different PWM control methods are adopted in the two different stages of low vector and high vector, which effectively solves the electromagnetic noise problem caused by phase shift during startup and operation, and achieves the purpose of reducing product costs.

[0006] An embodiment of the present invention provides a control method for eliminating FOC single resistor phase shift noise. The PWM module duty cycle is set with a comparison register A and a comparison register B. The value CMPA of the comparison register A and the value CMPB of the comparison register B are set at any position of the PWM cycle.

[0007] Optionally, the PWM operates in an up-counting or down-counting mode, and the three-phase PWM is set to be center- or edge-unaligned.

[0008] Optionally, when the vector is low, the three-phase PWM waveform is shifted to the far left or right, with one side of the three-phase PWM waveform being in a step-like shape and remaining unchanged, and the other side being a modulation area.

[0009] Optionally, the duty ratios of the U phase, V phase, and W phase in the three-phase PWM are set to: Stepped CMPA value: U phase: U_CMPA = 0 V phase: V_CMPA = U_CMPA + Ts W phase: W_CMPA = V_CMPA + Ts Modulation area CMPB value: U phase: U_CMPB = U_CMPA + (U_DUTY*2) V phase: V_CMPB = V_CMPA + (V_DUTY*2) W phase: W_CMPB = W_CMPA + (W_DUTY*2) Where Ts is the sampling window time.

[0010] Optionally, when the vector is high, the three-phase PWM waveform is shifted to the far left or far right, where one side of the three-phase PWM is edge-aligned and the other side is a modulation area.

[0011] Optionally, the duty ratios of the U phase, V phase, and W phase in the three-phase PWM are set to: Alignment area CMPA value: U phase: U_CMPA = 0 V phase: V_CMPA = 0 W phase: W_CMPA = 0 Modulation area CMPB value: U phase: U_CMPB = U_CMPA + (U_DUTY*2) V phase: V_CMPB = V_CMPA + (V_DUTY*2) W phase: W_CMPB = W_CMPA + (W_DUTY*2).

[0012] The present invention discloses a novel FOC single-resistor phase-shift control method. By adopting different PWM control modes in the low-vector and high-vector stages, the electromagnetic noise problem caused by phase shifting during startup and operation is effectively solved. The control method is comparable to the dual-resistor or triple-resistor solutions, achieving the goal of reducing product costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 This is the control logic waveform corresponding to the low vector stage; Figure 2 This is the control logic waveform corresponding to the high vector stage. DETAILED DESCRIPTION

[0014] The present invention will be further described in detail below with reference to the accompanying drawings and examples. It will be understood that the specific embodiments described herein are intended only to illustrate the present invention and are not intended to limit the present invention. It should also be noted that, for ease of description, the accompanying drawings only illustrate portions relevant to the present invention, not all structures. Example

[0015] An embodiment of the present invention provides a control method for eliminating phase-shift noise in a single-resistor FOC circuit. The PWM module duty cycle is configured with compare registers A and B. The values of compare register A (CMPA) and compare register B (CMPB) can be set at any position in the PWM cycle. The PWM operates in up-count or down-count mode, and the three-phase PWM is configured for center or edge misalignment.

[0016] This embodiment adopts different PWM control methods in the two different stages of low vector and high vector, specifically: At low vector, the three-phase PWM waveform is shifted to the far left or right, one side of the three-phase PWM is formed into a step shape and remains unchanged, and the other side is the modulation area, that is, the side of the step forms a fixed current sampling window and remains unchanged.

[0017] The sampling window time is Ts, and the duty cycle of the U phase, V phase, and W phase in the three-phase PWM is set to: Stepped CMPA value: U phase: U_CMPA = 0 V phase: V_CMPA = U_CMPA + Ts W phase: W_CMPA = V_CMPA + Ts Modulation area CMPB value: U phase: U_CMPB = U_CMPA + (U_DUTY*2) V phase: V_CMPB = V_CMPA + (V_DUTY*2) W phase: W_CMPB = W_CMPA + (W_DUTY*2).

[0018] The staircase position reserves a fixed Ts sampling window, where the current of the two phases can be obtained. This method does not have frequent PWM phase shifts, eliminating the electromagnetic noise caused by phase shifts. However, the duty of this method is limited and cannot be maximum or minimum. Otherwise, the waveform will be distorted or the staircase sampling will not be formed. It is only suitable for use in low vector or low speed conditions, such as when starting a motor. For further reference, see Figure 1 , Figure 1 This is the control logic waveform corresponding to the low vector stage.

[0019] At high vector, the three-phase PWM waveform is shifted to the far left or right, with one side of the three-phase PWM being edge-aligned and the other side being the modulation area. The duty ratios of the U-phase, V-phase, and W-phase in the three-phase PWM are set to: Alignment area CMPA value: U phase: U_CMPA = 0 V phase: V_CMPA = 0 W phase: W_CMPA = 0 Modulation area CMPB value: U phase: U_CMPB = U_CMPA + (U_DUTY*2) V phase: V_CMPB = V_CMPA + (V_DUTY*2) W phase: W_CMPB = W_CMPA + (W_DUTY*2).

[0020] The sampling window is the modulation area, and the modulation amplitude is twice that of the center alignment mode. This can reduce the problem of sampling failure due to insufficient sampling space. When sampling is impossible, the position observation algorithm of angle integration can be used, and the angle difference is added by default. This method is not suitable for low vector or low speed. The duty values of the three phases are not much different, and there is not enough current sampling window. Therefore, this embodiment needs to use different PWM control methods in the two different stages of low vector and high vector. For further reference, Figure 2 , Figure 2 This is the control logic waveform corresponding to the high vector stage.

[0021] Note that the above are only preferred embodiments of the present invention and the technical principles employed. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and that various obvious changes, readjustments, and substitutions can be made by those skilled in the art without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in detail through the above embodiments, the present invention is not limited to the above embodiments and may include many other equivalent embodiments without departing from the concept of the present invention. The scope of the present invention is determined by the scope of the appended claims.

Claims

1. A control method for eliminating FOC single resistor phase shift noise, characterized in that: The duty cycle of the PWM module is set with comparison register A and comparison register B. The value CMPA of comparison register A and the value CMPB of comparison register B are set at any position of the PWM cycle.

2. The control method according to claim 1, characterized in that: The PWM operates in up-counting or down-counting mode, and the three-phase PWM is set to be center- or edge-unaligned.

3. The control method according to claim 1, wherein: When the vector is low, the three-phase PWM waveform is shifted to the far left or right, with one side of the three-phase PWM waveform remaining unchanged in a step-like manner and the other side being a modulation area.

4. The control method according to claim 3, characterized in that: The duty ratios of the U-phase, V-phase, and W-phase in the three-phase PWM are set as follows: Stepped CMPA value: U phase: U_CMPA = 0 V phase: V_CMPA = U_CMPA + Ts W phase: W_CMPA = V_CMPA + Ts Modulation area CMPB value: U phase: U_CMPB = U_CMPA + (U_DUTY*2) V phase: V_CMPB = V_CMPA + (V_DUTY*2) W phase: W_CMPB = W_CMPA + (W_DUTY*2) Where Ts is the sampling window time.

5. The control method according to claim 1, characterized in that: When the vector is high, the three-phase PWM waveform is shifted to the far left or far right, where one side of the three-phase PWM is edge-aligned and the other side is a modulation area.

6. The control method according to claim 5, characterized in that: The duty ratios of the U phase, V phase, and W phase in the three-phase PWM are set to: Alignment area CMPA value: U phase: U_CMPA = 0 V phase: V_CMPA = 0 W phase: W_CMPA = 0 Modulation area CMPB value: U phase: U_CMPB = U_CMPA + (U_DUTY*2) V phase: V_CMPB = V_CMPA + (V_DUTY*2) W phase: W_CMPB = W_CMPA + (W_DUTY*2).

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