Dynamic ripple elimination circuit for linear Hall signal amplifier

Abstract

The invention relates to a dynamic ripple elimination circuit for a linear Hall signal amplifier, and belongs to the technical field of circuits. The dynamic ripple elimination circuit for the linear Hall signal amplifier comprises a ripple extraction network, a fully differential integrator, a chopper and a disappearance tone buffer which are connected in sequence, and the ripple extraction network extracts ripple signals in output signals of the amplifier; and through integration, chopping and buffering, a compensation signal for eliminating ripples is generated and injected into a main loop of the amplifier, and the ripples in an output signal of the linear Hall signal amplifier are eliminated. Therefore, a low-pass filter does not need to be adopted at the rear stage, adverse effects on the bandwidth are avoided, and the circuit is simple in structure and quite wide in application range.

Description

Technical Field

[0001] The present invention relates to the field of circuit technology, in particular to the field of Hall amplifier circuit technology, and specifically refers to a dynamic ripple elimination circuit for a linear Hall signal amplifier. Background Art

[0002] Traditional linear Hall effect amplifiers use chopper amplification technology. To filter the output ripple caused by the chopping, a low-pass filter is usually required in the subsequent stage. This low-pass filter significantly reduces the system bandwidth, which ultimately has a negative impact on signal fidelity, system response, and noise suppression.

[0003] Therefore, how to provide a ripple elimination circuit that can eliminate the ripple at the output end of the amplifier without affecting the system bandwidth has become an urgent problem to be solved in this field. Summary of the Invention

[0004] The purpose of the present invention is to overcome the shortcomings of the above-mentioned prior art and provide a dynamic ripple elimination circuit for a linear Hall signal amplifier, which extracts the clock-related output ripple at the output end of the amplifier and generates a signal for eliminating the ripple and injects it into the main circuit of the amplifier, thereby eliminating the ripple and ensuring the system bandwidth.

[0005] In order to achieve the above-mentioned purpose, the dynamic ripple elimination circuit for a linear Hall signal amplifier of the present invention has the following structure:

[0006] The dynamic ripple elimination circuit for a linear Hall signal amplifier comprises a ripple extraction network, a fully differential integrator, a chopper and a vanishing modulation buffer connected in sequence.

[0007] The input end of the ripple extraction network is connected to the output signal of the linear Hall signal amplifier to extract the ripple signal from the output signal of the linear Hall signal amplifier;

[0008] a fully differential integrator for integrating the ripple signal;

[0009] a chopper for chopping the ripple signal after the integration process;

[0010] The detuning buffer buffers the ripple signal after the chopping process, generates the output signal of the dynamic ripple elimination circuit as a compensation signal, and feeds the compensation signal back to the input end of the linear Hall signal amplifier to eliminate the ripple in the output signal of the linear Hall signal amplifier.

[0011] In the dynamic ripple elimination circuit for a linear Hall signal amplifier, the ripple extraction network is a switched capacitor ripple extraction network, which includes eight capacitors C1 to C8 and multiple switches. The ripple extraction network operates in four phases A, B, C, and D. The multiple switches have different conduction states corresponding to different phases, thereby:

[0012] In phase A, capacitor C1 is connected between the common-mode voltage Vcm and the positive input signal IP; capacitor C2 is connected between the common-mode voltage Vcm and the negative input signal IN;

[0013] In phase B, capacitor C3 is connected between the common-mode voltage Vcm and the positive input signal IP; capacitor C4 is connected between the common-mode voltage Vcm and the negative input signal IN;

[0014] In phase A or phase B, capacitors C6 and C7 are connected in parallel between the common-mode voltage Vcm and the positive output signal O1P, and capacitors C5 and C8 are connected in parallel between the common-mode voltage Vcm and the negative output signal O1N.

[0015] In phase C, capacitor C5 is connected between the common-mode voltage Vcm and the positive input signal IP; capacitor C6 is connected between the common-mode voltage Vcm and the negative input signal IN;

[0016] In the D phase, the capacitor C7 is connected between the common mode voltage Vcm and the positive input signal IP; the capacitor C8 is connected between the common mode voltage Vcm and the negative input signal IN;

[0017] In phase C or phase D, capacitors C2 and C3 are connected in parallel between the common-mode voltage Vcm and the positive output signal O1P, and capacitors C1 and C4 are connected in parallel between the common-mode voltage Vcm and the negative output signal O1N.

[0018]

[0019] Where: V_O1P(CD) is the positive output signal of CD phase; V_IP(B) is the positive input signal of B phase; V_IN(A) is the negative input signal of A phase;

[0020] V_O1N(CD) is the CD phase negative output signal; V_IP(A) is the A phase positive input signal; V_IN(B) is the B phase negative input signal;

[0021] V_O1(CD) is the CD phase output signal; V_I(A) is the A phase output; V_I(B) is the B phase output; the difference between the A phase output and the B phase output is used as the ripple signal.

[0022] In the dynamic ripple elimination circuit for a linear Hall signal amplifier, the fully differential integrator is a fully differential operational amplifier with a common-mode feedback unit. The positive output signal O1P of the ripple extraction network is connected to the positive input terminal of the fully differential operational amplifier, and the negative output signal O1N of the ripple extraction network is connected to the negative input terminal of the fully differential operational amplifier. The positive output terminal OP and the negative output terminal ON of the fully differential operational amplifier are both connected to the input terminal of the chopper.

[0023] In the dynamic ripple elimination circuit for a linear Hall signal amplifier, the fully differential integrator includes a differential pair of transistors consisting of multiple sets of matched NMOS and PMOS pairs, and the differential pair of transistors adopts a common source and common gate connection mode.

[0024] The input reference terminal VBI and the output adjustment terminal VBO of the common-mode feedback unit are connected to the common gate connection of the PMOS tubes of the differential pair tubes, and the positive output terminal OP and the negative output terminal ON of the fully differential operational amplifier and the common-mode voltage Vcom are all connected to the common-mode feedback unit;

[0025] The common-mode feedback unit includes a capacitor network of multiple capacitors and multiple switches, each switch is controlled by two non-overlapping clocks Φ1 and Φ2.

[0026] In the clock Φ1 phase, the input reference terminal VBI and the common mode voltage Vcom are connected to both ends of the first group of capacitors, and the positive output terminal OP and the output adjustment terminal VBO as well as the negative output terminal ON and the output adjustment terminal VBO are connected to both ends of the second group of capacitors;

[0027] In the clock Φ2 phase, the input reference terminal VBI and the common mode voltage Vcom are connected to the second group of capacitors, and the positive output terminal OP and the output adjustment terminal VBO as well as the negative output terminal ON and the output adjustment terminal VBO are connected to the first group of capacitors.

[0028] In the dynamic ripple elimination circuit for a linear Hall signal amplifier, the chopper includes an input terminal IA and an input terminal IB, which are respectively the positive output terminal OP and the negative output terminal ON of a fully differential operational amplifier. The input terminal IA and the input terminal IB are connected to the output terminals OA and OB of the chopper via a set of chopper control switches ΦAB and ΦCD.

[0029] In phase A or phase B, the chopping control switch ΦAB is turned on, the chopping control switch ΦCD is turned off, the input terminal IA is connected to the output terminal OA, and the input terminal IB is connected to the output terminal OB;

[0030] In the C phase or the D phase, the chopping control switch ΦCD is turned on, the chopping control switch ΦAB is turned off, the input terminal IA is connected to the output terminal OB, and the input terminal IB is connected to the output terminal OA.

[0031] In the dynamic ripple elimination circuit for a linear Hall signal amplifier, the vanishing modulation buffer includes two operational amplifiers OP1 and OP2 and two MOS transistors N1 and N2;

[0032] In the B phase or the D phase, the output terminal OA of the chopper is connected to the negative input terminal of the operational amplifier OP1, the output terminal of the operational amplifier OP1 is connected to the gate of the MOS transistor N1, the source thereof is grounded, and the drain is the positive output terminal OUTP of the zero-modulation buffer, and the positive output terminal OUTP is also connected to the positive input terminal of the operational amplifier OP1; the output terminal OB of the chopper is connected to the negative input terminal of the operational amplifier OP2, the output terminal of the operational amplifier OP2 is connected to the gate of the MOS transistor N2, the source thereof is grounded, and the drain is the negative output terminal OUTN of the zero-modulation buffer, and the negative output terminal OUTN is also connected to the positive input terminal of the operational amplifier OP2;

[0033] In phase A or phase C, the output end OA of the chopper is connected to the negative input end of the operational amplifier OP2, the output end of the operational amplifier OP2 is connected to the gate of the MOS tube N1, the source thereof is grounded, and the drain is the positive output end OUTP of the detuning buffer, and the positive output end OUTP is also connected to the positive input end of the operational amplifier OP2; the output end OB of the chopper is connected to the negative input end of the operational amplifier OP1, the output end of the operational amplifier OP1 is connected to the gate of the MOS tube N2, the source thereof is grounded, and the drain is the negative output end OUTN of the detuning buffer, and the negative output end OUTN is also connected to the positive input end of the operational amplifier OP1.

[0034] The dynamic ripple cancellation circuit for a linear Hall signal amplifier employing this invention comprises a ripple extraction network, a fully differential integrator, a chopper, and a detuning buffer connected in sequence. The ripple extraction network extracts ripple from the amplifier's output signal. After integration, chopping, and buffering, it generates a ripple-cancelling compensation signal that is injected into the amplifier's main circuit, eliminating ripple in the linear Hall signal amplifier's output signal. This eliminates the need for a low-pass filter in the subsequent stage, thus reducing the adverse effects on bandwidth. Furthermore, the circuit structure of this invention is simple and has a wide range of applications. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1 Schematic diagram of the connection mode of the dynamic ripple elimination circuit for the linear Hall signal amplifier of the present invention;

[0036] Figure 2 Schematic diagram of the structure of a dynamic ripple elimination circuit for a linear Hall signal amplifier of the present invention;

[0037] Figure 3Schematic diagram of the structure of the switch capacitor ripple extraction network in the dynamic ripple elimination circuit of the present invention;

[0038] Figure 4 for Figure 3 The diagram shows the phase switching sequence relationship of the switched capacitor ripple extraction network;

[0039] Figure 5 for Figure 3 The simplified connection diagram of each phase of the switched capacitor ripple extraction network shown in FIG.

[0040] Figure 6 Schematic diagram of the structure of a fully differential operational amplifier with a common-mode feedback unit in the dynamic ripple elimination circuit of the present invention;

[0041] Figure 7 for Figure 6 Schematic diagram of the structure of the common mode feedback unit;

[0042] Figure 8 A schematic diagram of the structure of a chopper in a dynamic ripple elimination circuit of the present invention;

[0043] Figure 9 A schematic structural diagram of a vanishing modulation buffer in a dynamic ripple elimination circuit of the present invention. DETAILED DESCRIPTION

[0044] In order to more clearly understand the technical content of the present invention, the following embodiments are given to illustrate in detail.

[0045] In one embodiment, Figure 1 As shown, the dynamic ripple elimination circuit for the linear Hall signal amplifier is connected to the linear Hall main channel chopper amplifier to eliminate the ripple generated by the Hall amplifier.

[0046] The dynamic ripple elimination circuit is as follows Figure 2 As shown, the circuit includes a ripple extraction network, a fully differential integrator, a chopper, and a vanishing modulation buffer connected in sequence.

[0047] The input end of the ripple extraction network is connected to the output signal of the linear Hall signal amplifier to extract the ripple signal from the output signal of the linear Hall signal amplifier;

[0048] a fully differential integrator for integrating the ripple signal;

[0049] A chopper performs chopping processing on the ripple signal after the integration processing;

[0050] The detuning buffer buffers the ripple signal after the chopping process, generates the output signal of the dynamic ripple elimination circuit as a compensation signal, and feeds the compensation signal back to the input end of the linear Hall signal amplifier to eliminate the ripple in the output signal of the linear Hall signal amplifier.

[0051] In a more preferred embodiment, the ripple extraction network is as follows Figure 3 The switching capacitor ripple extraction network shown in FIG. 1 includes eight capacitors C1 to C8 and multiple switches. The ripple extraction network operates in four phases: A, B, C, and D. The order of the switches in each phase is as follows: Figure 4 As shown, the AB phase indicates that the switches are all turned on in the A or B phase, and the CD phase indicates that the switches are all turned on in the C or D phase.

[0052] The multiple switches have different conduction states corresponding to different phases, and the simplified connection relationship of each phase is as follows: Figure 5 As shown:

[0053] In phase A, capacitor C1 is connected between the common-mode voltage Vcm and the positive input signal IP; capacitor C2 is connected between the common-mode voltage Vcm and the negative input signal IN;

[0054] In phase B, capacitor C3 is connected between the common-mode voltage Vcm and the positive input signal IP; capacitor C4 is connected between the common-mode voltage Vcm and the negative input signal IN;

[0055] In phase A or phase B, capacitors C6 and C7 are connected in parallel between the common-mode voltage Vcm and the positive output signal O1P, and capacitors C5 and C8 are connected in parallel between the common-mode voltage Vcm and the negative output signal O1N.

[0056] In phase C, capacitor C5 is connected between the common-mode voltage Vcm and the positive input signal IP; capacitor C6 is connected between the common-mode voltage Vcm and the negative input signal IN;

[0057] In the D phase, the capacitor C7 is connected between the common mode voltage Vcm and the positive input signal IP; the capacitor C8 is connected between the common mode voltage Vcm and the negative input signal IN;

[0058] In phase C or phase D, capacitors C2 and C3 are connected in parallel between the common mode voltage Vcm and the positive output signal O1P, and capacitors C1 and C4 are connected in parallel between the common mode voltage Vcm and the negative output signal O1N.

[0059] According to the above connection relationship, we can conclude that:

[0060]

[0061] Where: V_O1P(CD) is the positive output signal of CD phase; V_IP(B) is the positive input signal of B phase; V_IN(A) is the negative input signal of A phase;

[0062] V_O1N(CD) is the CD phase negative output signal; V_IP(A) is the A phase positive input signal; V_IN(B) is the B phase negative input signal;

[0063] V_O1(CD) is the CD phase output signal; V_I(A) is the A phase output; V_I(B) is the B phase output; the difference between the A and B phase outputs is used as the ripple signal. This shows that the ripple extraction network extracts the difference between the A and B phase outputs. This difference is converted into an AC compensation signal through the subsequent fully differential integrator, chopper, and detuning buffer.

[0064] In a further preferred embodiment, the fully differential integrator is a fully differential operational amplifier with a common mode feedback unit, and its structure is as follows: Figure 6 The positive output signal O1P of the ripple extraction network is connected to the positive input terminal of the fully differential operational amplifier, and the negative output signal O1N of the ripple extraction network is connected to the negative input terminal of the fully differential operational amplifier. The positive output terminal OP and the negative output terminal ON of the fully differential operational amplifier are both connected to the input terminal of the chopper.

[0065] The fully differential integrator is as follows Figure 6 As shown, it includes a differential pair of transistors composed of multiple sets of matched NMOS and PMOS pairs, and the differential pair of transistors adopts a common source and common gate connection mode.

[0066] The input reference terminal VBI and the output adjustment terminal VBO of the common-mode feedback unit are connected to the common gate connection of the PMOS tubes of the differential pair tubes, and the positive output terminal OP and the negative output terminal ON of the fully differential operational amplifier and the common-mode voltage Vcom are all connected to the common-mode feedback unit;

[0067] The common mode feedback unit is as follows Figure 7 As shown, the capacitor network includes multiple capacitors and multiple switches, each switch is controlled by two non-overlapping clocks Φ1 and Φ2.

[0068] In the clock Φ1 phase, the input reference terminal VBI and the common mode voltage Vcom are connected to both ends of the first group of capacitors, and the positive output terminal OP and the output adjustment terminal VBO as well as the negative output terminal ON and the output adjustment terminal VBO are connected to both ends of the second group of capacitors;

[0069] In the clock Φ2 phase, the input reference terminal VBI and the common mode voltage Vcom are connected to the second group of capacitors, and the positive output terminal OP and the output adjustment terminal VBO as well as the negative output terminal ON and the output adjustment terminal VBO are connected to the first group of capacitors.

[0070] In a further preferred embodiment, the chopper is as follows Figure 8 As shown, it is used to modulate the integrated signal into a compensation signal related to the main amplifier clock. It includes input terminals IA and IB, which are respectively the positive output terminal OP and the negative output terminal ON of the fully differential operational amplifier. The input terminals IA and IB are connected to the output terminals OA and OB of the chopper through a set of chopper control switches ΦAB and ΦCD.

[0071] In phase A or phase B, the chopping control switch ΦAB is turned on, the chopping control switch ΦCD is turned off, the input terminal IA is connected to the output terminal OA, and the input terminal IB is connected to the output terminal OB;

[0072] In the C phase or the D phase, the chopping control switch ΦCD is turned on, the chopping control switch ΦAB is turned off, the input terminal IA is connected to the output terminal OB, and the input terminal IB is connected to the output terminal OA.

[0073] The chopper in the ripple cancellation circuit remodulates the integrated, amplified ripple signal back to the switching frequency. Because this switching frequency is the same as the chopping frequency of the main channel amplifier, the chopping signal is correlated with the ripple introduced by the chopping circuit, but with opposite polarity, thus achieving ripple cancellation.

[0074] In a more preferred embodiment, the disappearance modulation buffer is as follows Figure 9 As shown, it includes two operational amplifiers OP1 and OP2 and two MOS transistors N1 and N2.

[0075] In the B phase or the D phase, the output terminal OA of the chopper (marked as the positive input terminal IP of the zero-demodulation buffer in the figure) is connected to the negative input terminal of the operational amplifier OP1, the output terminal of the operational amplifier OP1 is connected to the gate of the MOS transistor N1, the source thereof is grounded, and the drain is the positive output terminal OUTP of the zero-demodulation buffer, and the positive output terminal OUTP is also connected to the positive input terminal of the operational amplifier OP1; the output terminal OB of the chopper (marked as the negative input terminal IN of the zero-demodulation buffer in the figure) is connected to the negative input terminal of the operational amplifier OP2, the output terminal of the operational amplifier OP2 is connected to the gate of the MOS transistor N2, the source thereof is grounded, and the drain is the negative output terminal OUTN of the zero-demodulation buffer, and the negative output terminal OUTN is also connected to the positive input terminal of the operational amplifier OP2;

[0076] In phase A or phase C, the output terminal OA (IP) of the chopper is connected to the negative input terminal of the operational amplifier OP2, the output terminal of the operational amplifier OP2 is connected to the gate of the MOS tube N1, the source thereof is grounded, and the drain is the positive output terminal OUTP of the detuning buffer, and the positive output terminal OUTP is also connected to the positive input terminal of the operational amplifier OP2; the output terminal OB (IN) of the chopper is connected to the negative input terminal of the operational amplifier OP1, the output terminal of the operational amplifier OP1 is connected to the gate of the MOS tube N2, the source thereof is grounded, and the drain is the negative output terminal OUTN of the detuning buffer, and the negative output terminal OUTN is also connected to the positive input terminal of the operational amplifier OP1.

[0077] Therefore, by switching the input stage of the detuning buffer, the offset voltage introduced by the input stage is modulated to the high frequency end, and then the high frequency component can be eliminated by the subsequent filter, thereby achieving the purpose of buffer detuning.

[0078] In practical applications, the core of the dynamic ripple elimination circuit of the present invention is to amplify the ripple signal at the output end through ripple extraction, integration, chopping modulation, and buffered output, process it into a synchronous signal related to the main path clock, and inject it into the main circuit of the Hall signal amplifier, thereby achieving the purpose of ripple elimination.

[0079] The ripple attenuation coefficient of this circuit is related to the loop gain of the vanishing modulation loop. Due to the presence of an integrator in the vanishing modulation loop, the loop can achieve very high low-frequency gain, thereby achieving very high ripple rejection. Simulations show that the ripple rejection ratio can reach 70dB within a 20kHz bandwidth.

[0080] The dynamic ripple cancellation circuit for a linear Hall signal amplifier employing this invention comprises a ripple extraction network, a fully differential integrator, a chopper, and a detuning buffer connected in sequence. The ripple extraction network extracts ripple from the amplifier's output signal. After integration, chopping, and buffering, it generates a ripple-cancelling compensation signal that is injected into the amplifier's main circuit, eliminating ripple in the linear Hall signal amplifier's output signal. This eliminates the need for a low-pass filter in the subsequent stage, thus reducing the adverse effects on bandwidth. Furthermore, the circuit structure of this invention is simple and has a wide range of applications.

[0081] In this specification, the present invention has been described with reference to specific embodiments thereof. However, it will be apparent that various modifications and variations may be made without departing from the spirit and scope of the present invention. Accordingly, the specification and drawings are to be regarded as illustrative rather than restrictive.

Claims

1. A dynamic ripple elimination circuit for a linear Hall signal amplifier, characterized in that: The dynamic ripple elimination circuit includes a ripple extraction network, a fully differential integrator, a chopper and a vanishing modulation buffer connected in sequence. The input end of the ripple extraction network is connected to the output signal of the linear Hall signal amplifier to extract the ripple signal from the output signal of the linear Hall signal amplifier; a fully differential integrator for integrating the ripple signal; a chopper for chopping the ripple signal after the integration process; The detuning buffer buffers the ripple signal after the chopping process, generates the output signal of the dynamic ripple elimination circuit as a compensation signal, and feeds the compensation signal back to the input end of the linear Hall signal amplifier to eliminate the ripple in the output signal of the linear Hall signal amplifier.

2. The dynamic ripple elimination circuit for a linear Hall signal amplifier according to claim 1, characterized in that: The ripple extraction network is a switched capacitor ripple extraction network, which includes eight capacitors C1 to C8 and multiple switches. The ripple extraction network operates in four phases A, B, C, and D. The multiple switches have different conduction states corresponding to different phases, thereby: In phase A, capacitor C1 is connected between the common-mode voltage Vcm and the positive input signal IP; capacitor C2 is connected between the common-mode voltage Vcm and the negative input signal IN; In phase B, capacitor C3 is connected between the common-mode voltage Vcm and the positive input signal IP; capacitor C4 is connected between the common-mode voltage Vcm and the negative input signal IN; In phase A or phase B, capacitors C6 and C7 are connected in parallel between the common-mode voltage Vcm and the positive output signal O1P, and capacitors C5 and C8 are connected in parallel between the common-mode voltage Vcm and the negative output signal O1N. In phase C, capacitor C5 is connected between the common-mode voltage Vcm and the positive input signal IP; capacitor C6 is connected between the common-mode voltage Vcm and the negative input signal IN; In the D phase, the capacitor C7 is connected between the common mode voltage Vcm and the positive input signal IP; the capacitor C8 is connected between the common mode voltage Vcm and the negative input signal IN; In phase C or phase D, capacitors C2 and C3 are connected in parallel between the common-mode voltage Vcm and the positive output signal O1P, and capacitors C1 and C4 are connected in parallel between the common-mode voltage Vcm and the negative output signal O1N. Where: V_O1P(CD) is the positive output signal of CD phase; V_IP(B) is the positive input signal of B phase; V_IN(A) is the negative input signal of A phase; V_O1N(CD) is the CD phase negative output signal; V_IP(A) is the A phase positive input signal; V_IN(B) is the B phase negative input signal; V_O1(CD) is the CD phase output signal; V_I(A) is the A phase output; V_I(B) is the B phase output; the difference between the A phase output and the B phase output is used as the ripple signal.

3. The dynamic ripple elimination circuit for a linear Hall signal amplifier according to claim 2, characterized in that: The fully differential integrator is a fully differential operational amplifier with a common-mode feedback unit. The positive output signal O1P of the ripple extraction network is connected to the positive input terminal of the fully differential operational amplifier, and the negative output signal O1N of the ripple extraction network is connected to the negative input terminal of the fully differential operational amplifier. The positive output terminal OP and the negative output terminal ON of the fully differential operational amplifier are both connected to the input terminal of the chopper.

4. The dynamic ripple elimination circuit for a linear Hall signal amplifier according to claim 3, characterized in that: The fully differential integrator includes a differential pair of transistors consisting of multiple sets of matched NMOS and PMOS pairs, and the differential pair of transistors adopts a common source and common gate connection mode. The input reference terminal VBI and the output adjustment terminal VBO of the common-mode feedback unit are connected to the common gate connection of the PMOS tubes of the differential pair tubes, and the positive output terminal OP and the negative output terminal ON of the fully differential operational amplifier and the common-mode voltage Vcom are all connected to the common-mode feedback unit; The common-mode feedback unit includes a capacitor network of multiple capacitors and multiple switches, each switch is controlled by two non-overlapping clocks Φ1 and Φ2. In the clock Φ1 phase, the input reference terminal VBI and the common mode voltage Vcom are connected to both ends of the first group of capacitors, and the positive output terminal OP and the output adjustment terminal VBO as well as the negative output terminal ON and the output adjustment terminal VBO are connected to both ends of the second group of capacitors; In the clock Φ2 phase, the input reference terminal VBI and the common mode voltage Vcom are connected to the second group of capacitors, and the positive output terminal OP and the output adjustment terminal VBO as well as the negative output terminal ON and the output adjustment terminal VBO are connected to the first group of capacitors.

5. The dynamic ripple elimination circuit for a linear Hall signal amplifier according to claim 4, characterized in that: The chopper includes an input terminal IA and an input terminal IB, which are respectively the positive output terminal OP and the negative output terminal ON of the fully differential operational amplifier. The input terminal IA and the input terminal IB are connected to the output terminals OA and OB of the chopper through a set of chopper control switches ΦAB and ΦCD. In phase A or phase B, the chopping control switch ΦAB is turned on, the chopping control switch ΦCD is turned off, the input terminal IA is connected to the output terminal OA, and the input terminal IB is connected to the output terminal OB; In the C phase or the D phase, the chopping control switch ΦCD is turned on, the chopping control switch ΦAB is turned off, the input terminal IA is connected to the output terminal OB, and the input terminal IB is connected to the output terminal OA.

6. The dynamic ripple elimination circuit for a linear Hall signal amplifier according to claim 5, characterized in that: The vanishing modulation buffer includes two operational amplifiers OP1 and OP2 and two MOS transistors N1 and N2; In the B phase or the D phase, the output terminal OA of the chopper is connected to the negative input terminal of the operational amplifier OP1, the output terminal of the operational amplifier OP1 is connected to the gate of the MOS transistor N1, the source thereof is grounded, and the drain is the positive output terminal OUTP of the zero-modulation buffer, and the positive output terminal OUTP is also connected to the positive input terminal of the operational amplifier OP1; the output terminal OB of the chopper is connected to the negative input terminal of the operational amplifier OP2, the output terminal of the operational amplifier OP2 is connected to the gate of the MOS transistor N2, the source thereof is grounded, and the drain is the negative output terminal OUTN of the zero-modulation buffer, and the negative output terminal OUTN is also connected to the positive input terminal of the operational amplifier OP2; In phase A or phase C, the output end OA of the chopper is connected to the negative input end of the operational amplifier OP2, the output end of the operational amplifier OP2 is connected to the gate of the MOS tube N1, the source thereof is grounded, and the drain is the positive output end OUTP of the detuning buffer, and the positive output end OUTP is also connected to the positive input end of the operational amplifier OP2; the output end OB of the chopper is connected to the negative input end of the operational amplifier OP1, the output end of the operational amplifier OP1 is connected to the gate of the MOS tube N2, the source thereof is grounded, and the drain is the negative output end OUTN of the detuning buffer, and the negative output end OUTN is also connected to the positive input end of the operational amplifier OP1.

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