Delay system, controller power supply system, controller power supply method and vehicle

Abstract

The invention provides a time delay system, a controller power supply system, a controller power supply method and a vehicle. The time delay system comprises a latch circuit and a timing circuit, the timing circuit comprises an oscillating circuit and a counting circuit. The oscillating circuit is used for outputting reference clock signals with the same frequency; the oscillating circuit is connected with the counting circuit, the counting circuit is connected with the latch circuit, and the latch circuit is connected with a controller in a vehicle. Under the condition that the working voltage of the controller is abnormal, the abnormal signals are latched through the latch circuit, and the abnormal signals are accurately recorded through the oscillation circuit outputting the reference clock signals with the same frequency and the counting circuit, so that high-precision time delay of the abnormal signals is achieved.

Description

Technical Field

[0001] The present invention relates to the field of vehicle technology, and in particular to a delay system, a controller power supply system, a controller power supply method, and a vehicle. Background Art

[0002] With the increasing intelligence of automotive electronic systems, the controllers inside vehicles are gradually developing in the direction of integration and intelligence. During the power supply process of the controller, more and more key signals need to be output according to a certain timing to ensure that the controller can start and run normally. In actual production applications, various unexpected signal timings often appear inside the controller, causing the entire device to fail to start or malfunction.

[0003] To ensure the proper functioning of the controller, its status must be monitored. To avoid special circumstances such as measurement errors or interference, a delay can be added to detect anomalies, allowing for more accurate monitoring of the controller's status over a period of time. This delay is typically achieved using RC delay circuits or 555 timers. These devices essentially delay signals by charging and discharging capacitors. However, due to inherent capacitance errors, they cannot achieve high-precision delays, which can affect controller status detection.

[0004] The above content is only used to assist in understanding the technical solution of the present invention and does not constitute an admission that the above content is prior art. Summary of the Invention

[0005] The main purpose of the present invention is to provide a delay system, a controller power supply system, a controller power supply method and a vehicle, aiming to solve the technical problem in the prior art that the abnormal signal of the controller working voltage cannot be delayed with high precision due to the capacitance characteristics.

[0006] To achieve the above object, the present invention proposes a delay system, which includes: a latch circuit and a timing circuit;

[0007] The timing circuit includes: an oscillating circuit and a counting circuit; the oscillating circuit is used to output a reference clock signal with the same frequency;

[0008] The oscillation circuit is connected to the counting circuit, the counting circuit is connected to the latch circuit, and the latch circuit is connected to a controller in the vehicle;

[0009] The latch circuit is configured to detect an abnormal signal corresponding to when the operating voltage of the controller is not within a standard voltage range, and output a timing signal to the counting circuit when the abnormal signal is detected;

[0010] The counting circuit is configured to record the number of reference clock signals output by the oscillation circuit upon receiving the timing signal, and output a timing completion signal to the latch circuit when the number of reference clock signals reaches a preset number;

[0011] The latch circuit is further configured to output the abnormality signal when receiving the timing completion signal.

[0012] Optionally, the oscillation circuit is a crystal oscillator provided in the controller, and the counting circuit is a counter;

[0013] The output end of the crystal oscillator is connected to the fundamental frequency clock signal input end of the counter, and the signal input end and the signal output end of the counter are both connected to the latch circuit.

[0014] Optionally, the timing circuit further includes: a dial button;

[0015] The dial button is connected to the counter and is used to input the number code corresponding to the preset number into the counter;

[0016] The counter is further configured to determine a preset number corresponding to the reference clock signal according to the number code.

[0017] Optionally, the latch circuit includes: a first D flip-flop, a second D flip-flop and a delay circuit;

[0018] The first input terminal of the first D flip-flop is connected to the abnormal signal output terminal of the controller through the delay circuit, the second input terminal of the first D flip-flop is connected to the abnormal signal output terminal of the controller, and the output terminal of the first D flip-flop is connected to the counting circuit;

[0019] The first input terminal of the second D flip-flop is connected to the abnormal signal output terminal of the controller, and the second input terminal of the D flip-flop is connected to the output terminal of the counting circuit;

[0020] The first D flip-flop is configured to be activated when receiving the abnormal signal through the second input terminal, and output a timing signal to the counting circuit when receiving the abnormal signal after the delay of the delay circuit through the first input terminal;

[0021] The second D flip-flop is configured to output the abnormality signal received through the first input terminal when receiving the timing completion signal output by the counting circuit.

[0022] Optionally, the latch circuit further includes: a first AND gate, a second AND gate, a third AND gate and a reset chip;

[0023] The first input end of the first AND gate is connected to the abnormal signal output end of the controller, the input end of the second AND gate, and the second input end of the third AND gate; the second input end of the first AND gate is connected to the reset end of the reset chip, the first input end of the second AND gate, and the first input end of the third AND gate; the output end of the first AND gate is connected to the input end of the delay circuit;

[0024] The third input terminal of the second AND gate is connected to the second output terminal of the second D flip-flop, and the output terminal of the second AND gate is connected to the second input terminal of the first D flip-flop;

[0025] The output terminal of the third AND gate is connected to the first input terminal of the second D flip-flop.

[0026] Optionally, the delay system further comprises: a communication circuit;

[0027] The communication circuit is connected to the latch circuit and an external terminal;

[0028] The communication circuit is used to receive the abnormal signal output by the latch circuit and output the abnormal signal to the external terminal.

[0029] In addition, to achieve the above-mentioned purpose, the present invention also provides a controller power supply system, the controller power supply system comprising: a voltage conversion circuit, a voltage detection circuit and the delay system;

[0030] The voltage conversion circuit is connected to the external power supply and the controller, and the voltage detection circuit is connected to the controller and the delay system;

[0031] The voltage conversion circuit is used to convert the external voltage input by the external power supply into the operating voltage required by the controller and output it to the controller;

[0032] The voltage detection circuit is used to detect the operating voltage of the controller and output an abnormal signal to the delay system when the operating voltage is not within the standard voltage range.

[0033] Optionally, the controller power supply system further includes: a power supply switching circuit and a backup power supply:

[0034] The power supply switching circuit is connected to the voltage detection circuit, the backup power supply and the delay system;

[0035] The power supply switching circuit is used to output the backup voltage output by the backup power supply to the delay system when receiving the abnormal signal output by the voltage detection circuit.

[0036] In addition, to achieve the above-mentioned purpose, the present invention further provides a controller power supply method, which is applied to the controller power supply system; the controller power supply method includes:

[0037] Detect the operating voltage of the controller;

[0038] When the operating voltage is not within the standard voltage range, the delay time during which the operating voltage is not within the standard voltage range is recorded by the delay system;

[0039] When the delay time reaches a preset time, an abnormal signal is output and power supply to the controller is stopped.

[0040] In addition, to achieve the above-mentioned purpose, the present invention also provides a vehicle, which includes: the controller power supply system.

[0041] The present invention provides a time delay system, a controller power supply system, a controller power supply method, and a vehicle. The time delay system includes: a latch circuit and a timing circuit; the timing circuit includes: an oscillator circuit and a counting circuit; the oscillator circuit is used to output a reference clock signal with the same frequency; the oscillator circuit is connected to the counting circuit, the counting circuit is connected to the latch circuit, and the latch circuit is connected to the controller in the vehicle; the latch circuit is used to detect an abnormal signal corresponding to when the operating voltage of the controller is not within the standard voltage range, and when the abnormal signal is detected, output a timing signal to the counting circuit; the counting circuit is used to record the number of signals of the reference clock signal output by the oscillator circuit when receiving the timing signal, and output a timing completion signal to the latch circuit when the number of signals reaches a preset number; the latch circuit is also used to output the abnormal signal when receiving the timing completion signal. In the case of an abnormal operating voltage of the controller, the present invention latches the abnormal signal through the latch circuit, and uses the oscillator circuit that outputs the reference clock signal with the same frequency and the counting circuit to accurately record the abnormal signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the structures shown in these drawings without paying any creative work.

[0043] Figure 1 This is a schematic structural diagram of a first embodiment of a charging system proposed by the present invention;

[0044] Figure 2This is a schematic structural diagram of a second embodiment of the delay system proposed by the present invention;

[0045] Figure 3 This is a circuit diagram of a latch circuit in the delay system proposed by the present invention;

[0046] Figure 4 This is a schematic structural diagram of a third embodiment of the delay system proposed by the present invention;

[0047] Figure 5 This is a first structural diagram of an embodiment of a controller power supply system proposed by the present invention;

[0048] Figure 6 This is a second structural diagram of an embodiment of the controller power supply system proposed by the present invention;

[0049] Figure 7 This is a third structural diagram of an embodiment of the controller power supply system proposed by the present invention;

[0050] Figure 8 This is a flow chart of an embodiment of a controller power supply method proposed in the present invention.

[0051] The purpose, features and advantages of the present invention will be further described with reference to the accompanying drawings and in conjunction with the embodiments. DETAILED DESCRIPTION

[0052] It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0053] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. All other embodiments obtained by ordinary technicians in this field based on the embodiments of the present invention without making any creative efforts shall fall within the scope of protection of the present invention.

[0054] It should be noted that all directional indications in the embodiments of the present invention (such as up, down, left, right, front, back, etc.) are only used to explain the relative position relationship, movement status, etc. between the various components under a certain specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indication will also change accordingly.

[0055] In addition, the descriptions of "first", "second", etc. in the present invention are for descriptive purposes only and should not be understood as indicating or implying their relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" or "second" may explicitly or implicitly include at least one of such features. In addition, the technical solutions between the various embodiments can be combined with each other, but this must be based on the fact that they can be implemented by ordinary technicians in this field. When the combination of technical solutions is contradictory or cannot be implemented, it should be deemed that such combination of technical solutions does not exist and is not within the scope of protection required by the present invention.

[0056] Reference Figure 1 , Figure 1 This is a schematic diagram of the structure of the first embodiment of the charging system proposed by the present invention. Figure 1 In the embodiment, the charging system includes: a latch circuit 10 and a timing circuit 20;

[0057] The timing circuit 20 includes an oscillating circuit 201 and a counting circuit 202; the oscillating circuit 201 is used to output a reference clock signal with the same frequency;

[0058] The oscillation circuit 201 is connected to the counting circuit 202 , the counting circuit 202 is connected to the latch circuit 10 , and the latch circuit 10 is connected to a controller in the vehicle.

[0059] It should be understood that there are a certain number of controllers in the vehicle, and each controller controls the operation of the corresponding load. Once a controller becomes abnormal, the vehicle load controlled by the controller will not be able to operate normally, causing vehicle failure or even safety risks. When detecting the status of the controller, the status of the controller is mainly determined by some parameters during the controller's operation. These parameters may be subject to external interference or the randomness of the detection, which may lead to inaccurate parameter detection. Therefore, multiple detections over a period of time can be performed to obtain an accurate controller status. In the actual detection process, the detection of the controller needs to be timed to record the parameters over a period of time. The accuracy of the timing will affect the controller status detection results.

[0060] It should be noted that the latch circuit 10 is a circuit for latching a signal and outputting it when the trigger condition is met. The latch circuit 10 can be composed of a latch or a trigger. In the event of a controller anomaly, the latch circuit 10 can first store the corresponding abnormal signal of the controller. After a period of time, if the controller is indeed abnormal, the abnormal signal can be output. The timing circuit 20 is a circuit for recording the duration of the trigger condition and can achieve precise timing. The oscillator circuit 201 is a circuit for generating a precise reference clock signal. The reference clock signal has a uniform frequency, and the time interval between each pulse corresponding to the reference clock signal is uniform. The oscillator circuit 201 can use a device such as a crystal oscillator or a silicon oscillator that outputs a very accurate reference clock signal. The counting circuit 202 is a circuit for recording the number of reference clock signals generated by the oscillator circuit 201 or the number of pulses in the reference clock signal. The oscillator circuit 201 and the counting circuit 202 can accurately record the duration of the abnormal signal. The abnormal signal is a signal indicating that the controller is abnormal when the operating voltage of the controller does not match the actual required operating voltage.

[0061] In a specific implementation, the latch circuit 10 can detect an interface connected to the controller or an output end of a detection structure for the controller. When the operating voltage of the controller is not within the standard voltage range, the controller or the output end of the detection structure will output an abnormal signal. When the abnormal signal is detected, a timing signal is output to the counting circuit 202; when the counting circuit 202 receives the timing signal, it can record the number of signals of the reference clock signal output by the oscillation circuit from the moment of receiving the timing signal, and when the number of signals reaches a preset number, it outputs a timing completion signal to the latch circuit 10; when the latch circuit 10 receives the timing completion signal, it can determine that the operating voltage of the controller has not been within the standard voltage range during the timing period, that is, the controller has indeed experienced an abnormality, and then output the abnormal signal to remind the user that there is an abnormality in the controller in the vehicle.

[0062] Among them, the standard voltage range is the range of the working voltage during the normal operation of the controller. The standard voltage range can be a voltage range that fluctuates within a smaller range centered on the rated voltage of the controller. For example, if the rated voltage of the controller is 12V, the standard voltage range can be a voltage range of 11.5V to 12.5V. The abnormal signal is a signal used to prompt that there is an abnormality in the controller when the working voltage of the controller is not within the standard voltage range. The timing signal is a start signal for timing the length of time that the working voltage of the controller is not within the standard voltage range. The timing completion signal is an end timing signal when the length of time that the working voltage of the controller is not within the standard voltage range reaches a point where external interference can be eliminated.

[0063] It is understood that during the timing time, the latch circuit 10 will continue to detect abnormal signals. When the number of signals of the reference clock signal does not reach the preset number, and the abnormal signal detected by the latch circuit 10 is interrupted, it can be determined that the operating voltage of the controller is not within the standard voltage range for a short period of time, and is not caused by a controller failure. The number of signals is the number of reference clock signals recorded by the counting circuit 202 after the timing is started; the preset number is a pre-set number used to determine the timing duration. For example, if the reference clock signal is output every 0.01 seconds, if the number of recorded signals is 100, it can be determined that the timing duration has reached 1 second. The preset number can be set according to the specific interference situation of the controller. For example, the interference received by a controller may last for 1 second, and the preset number can be set to the number corresponding to the continuous output of the reference clock signal for 1.5 seconds or 2 seconds.

[0064] In this embodiment, the delay system includes: a latch circuit 10 and a timing circuit 20; the timing circuit 20 includes: an oscillator circuit 201 and a counting circuit 202; the oscillator circuit 201 is used to output a reference clock signal with the same frequency; the oscillator circuit 201 is connected to the counting circuit 202, the counting circuit 202 is connected to the latch circuit 10, and the latch circuit 10 is connected to a controller in the vehicle; the latch circuit 10 detects an abnormal signal corresponding to when the operating voltage of the controller is not within the standard voltage range, and when the abnormal signal is detected, outputs a timing signal to the counting circuit 202; when the counting circuit 202 receives the timing signal, it records the number of signals of the reference clock signal output by the oscillator circuit, and when the number of signals reaches a preset number, it outputs a timing completion signal to the latch circuit 10; when the latch circuit 10 receives the timing completion signal, it outputs the abnormal signal. In this embodiment, when the operating voltage of the controller is abnormal, the abnormal signal is latched by the latch circuit, and the abnormal signal is accurately recorded by using the oscillator circuit that outputs the reference clock signal with the same frequency and the counting circuit.

[0065] Based on the first embodiment of the delay system described above, the present invention proposes a second embodiment of the delay system. Figure 2 , Figure 2 This is a schematic structural diagram of the second embodiment of the delay system proposed by the present invention.

[0066] In this embodiment, the oscillation circuit 201 in the delay system is a crystal oscillator arranged in the controller, and the counting circuit 202 is a counter; the output end of the crystal oscillator is connected to the base frequency clock signal input end of the counter, and the signal input end and signal output end of the counter are both connected to the latch circuit 10.

[0067] It is understood that oscillator circuit 201 requires a stable baseband clock signal with a constant output frequency. Considering that a vehicle controller is typically equipped with a crystal oscillator or connected to a crystal oscillator, the crystal oscillator can provide a stable baseband clock signal for the controller's signal input and output processes. Crystal oscillators typically achieve an accuracy of ±10ppm, or a set time error of one part in 100,000, which is far greater than the accuracy of capacitor charging and discharging timing.

[0068] In order to reduce costs, in this embodiment, a crystal oscillator provided inside the controller or a crystal oscillator connected to the controller can be directly used as the oscillator circuit 10. The baseband clock signal stably output by the crystal oscillator is used as an accurate timing unit. The counter can be a set counter, which is triggered once when a baseband clock signal is received to record the baseband clock signal. When a baseband clock signal includes only one pulse, the counter can directly count the number of signals of the baseband clock signal according to the rising edge or falling edge of the pulse; of course, if a baseband clock signal includes multiple pulses, each pulse in the baseband clock signal can also be recorded using the rising edge or falling edge of the pulse, and then the number of signals of the baseband clock signal is determined based on the total number of recorded pulses. Of course, the number of pulses included in each baseband clock signal needs to be the same.

[0069] The timing circuit 20 within the delay system also includes a dial button 203, which is connected to a counter and can be used to set a preset number in the counter for number determination. After the user determines the specific duration for which the abnormal signal needs to be delayed, the user can use the dial button 203 to input the preset number of baseband clock signals corresponding to the delay duration. When setting the preset number using the dial button 203, the number code corresponding to the preset number can be determined, and then the corresponding number code can be input through the dial button 203, thereby setting the preset number of baseband clock signals within the counter. For example, when using multiple binary dial buttons, if the preset number of baseband clock signals required is 10, the corresponding number code is 1010; for another example, when using dial buttons corresponding to addition and subtraction, if the preset number of baseband clock signals required is 10, then pressing the corresponding dial button for the number plus the corresponding number 10 times will suffice.

[0070] The number code is used to prevent interference that causes the controller's operating voltage to be outside the standard voltage range, generating an abnormal signal duration. This number code corresponds to a preset number set in the counter. Different vehicle controllers require different time durations, and the corresponding number codes are also different.

[0071] During the specific setting process, the duration of the abnormal signal delay can be determined based on the specific controller type or the duration of the interference that usually occurs in the environment where the controller is located, and then the number of baseband clock signal signals that need to be recorded can be determined based on the delay duration and the frequency of the baseband clock signal output by the crystal oscillator, and the number code corresponding to the number of signals can be determined based on the specific type of the dial button 203, and the number code can be input into the counter through the dial button 203; when the counter receives the number code, it can determine the preset number corresponding to the reference clock signal based on the number code, and store the preset number for subsequent recording of the number of baseband clock signals.

[0072] In this embodiment, by using the crystal oscillator used by the controller as oscillator circuit 10, the crystal oscillator can be reused, eliminating the need for additional components for generating a baseband clock signal, thereby reducing the cost of the delay system. Furthermore, by configuring dial buttons 203, different preset numbers of baseband clock signals can be set for different controllers or interference during controller testing, enabling more accurate delay of abnormal signals.

[0073] In addition, the counting circuit 202 inside the delay system can also be set by cascading multiple counters and matching corresponding dial buttons to achieve time settings from microseconds to seconds. The range of free setting of the delay time is very large and the adjustability is strong.

[0074] Based on the first embodiment or the second embodiment of the delay system described above, a third embodiment of the delay system of the present invention is proposed. Figure 3 , Figure 3 This is a circuit principle diagram of the latch circuit in the delay system proposed by the present invention.

[0075] In this embodiment, the latch circuit includes: a first D flip-flop D1, a second D flip-flop D2 and a delay circuit 101; the first input terminal CLK1 of the first D flip-flop D1 is connected to the abnormal signal output terminal of the controller through the delay circuit 101, the second input terminal CLR1 of the first D flip-flop D1 is connected to the abnormal signal output terminal of the controller, and the output terminal Q1 of the first D flip-flop D1 is connected to the counting circuit 202; the first input terminal CLR2 of the second D flip-flop D2 is connected to the abnormal signal output terminal of the controller, and the second input terminal CLK2 of the D flip-flop D2 is connected to the output terminal of the counting circuit 202.

[0076] It should be understood that the D flip-flop itself has the function of triggering based on the relevant control signals it receives. Specifically, the trigger condition for the first D flip-flop D1 is the receipt of an abnormality signal, specifically triggering it to output a timing signal to the counting circuit 202. The trigger condition for the second D flip-flop is the receipt of a timing completion signal, specifically triggering it to output an abnormality signal. In other words, the first D flip-flop D1 is actually the trigger that controls the counting circuit 202 to start timing; the second D flip-flop D2 is the trigger that outputs the abnormality signal when it detects an abnormality in the controller.

[0077] It should be noted that the delay circuit 101 is a circuit for delaying the abnormal signal input to the first D flip-flop D1. Considering that the first D flip-flop D1 may not be in normal operation when the controller outputs the abnormal signal, there may be a time delay between the controller outputting the abnormal signal, the first D flip-flop D1 starting up, and then outputting the timing signal. Therefore, the delay circuit 101 can be used to delay the abnormal signal input to the first input terminal CLK1 of the first D flip-flop D1. The second input terminal CLR1 of the first D flip-flop D1 is also connected to the controller. When the abnormal signal is received through the second input terminal CLR1, the first D flip-flop D1 can be controlled to start up and enter normal operation. The abnormal signal passing through the first input terminal CLK1 of the first D flip-flop D1 can then control the output terminal Q1 of the first D flip-flop D1 to output a timing signal to the counting circuit 202, thereby avoiding the problem of inaccurate timing that may be caused by the first D flip-flop D1 not being in an operating state. The delay circuit 101 can comprise a conventional delay circuit to ensure that the first D flip-flop D1 has completed its self-test and other processes before the abnormal signal CLK1 is received at the first input terminal of the first D flip-flop D1. For example, an RC delay circuit can be employed, or multiple AND gates can be connected in series. Of course, to ensure delay accuracy, the timing circuit 202 and latch circuit 10 within the delay system can also be employed to provide accurate delay.

[0078] In a specific implementation, the first D flip-flop D1 is first started when it receives the abnormal signal through the second input terminal CLR1. After the startup is completed, the first D flip-flop D1 receives the abnormal signal after the delay circuit 101 through the first input terminal CLK1, and outputs a timing signal to the counting circuit 202 when the delayed abnormal signal is received through the first input terminal CLK1; when the counting circuit 202 receives the timing signal, it can record the number of signals of the reference clock signal output by the oscillation circuit with the moment of receiving the timing signal as the starting point, and output a timing completion signal to the second input terminal CLK2 of the second D flip-flop D2 when the number of signals reaches a preset number; when the second D flip-flop D2 receives the timing completion signal output by the counting circuit 202, it outputs the abnormal signal received through the first input terminal CLR1 through the first output terminal Q2.

[0079] In addition, in this embodiment, the latch circuit 10 further includes: a first AND gate, a second AND gate, a third AND gate and a reset chip Reset;

[0080] The first input end of the first AND gate is connected to the abnormal signal output end of the controller, the input end of the second AND gate and the second input end of the third AND gate; the second input end of the first AND gate is connected to the reset end of the reset chip Reset, the first input end of the second AND gate and the first input end of the third AND gate; the output end of the first AND gate is connected to the input end of the delay circuit 101; the third input end of the second AND gate is connected to the second output end Q3 of the second D flip-flop D2; the output end of the second AND gate is connected to the second input end CLR1 of the first D flip-flop D1; the output end of the third AND gate is connected to the first input end CLR2 of the second D flip-flop D2.

[0081] It should be understood that after the first D flip-flop D1 and the second D flip-flop D2 are triggered, considering that the operating voltage of the controller may not be within the standard voltage range, the first D flip-flop D1 and the second D flip-flop D2 need to be used in sequence. Therefore, after the first D flip-flop D1 and the second D flip-flop D2 are triggered once, the first D flip-flop D1 and the second D flip-flop D2 need to be reset. The reset chip Reset is the chip that resets the first D flip-flop D1 and the second D flip-flop D2. The reset chip Reset can use the watchdog MAX823 chip. The watchdog chip MAX823 will clear and release the D flip-flop; of course, other reset chips can also be used, which is not specifically limited here. The AND gate is a logic operation device. When the same type of level signal is input to the two input terminals, the output terminal of the AND gate will output a high level signal. On the contrary, when different types of level signals are input to the two input terminals, the output terminal of the AND gate will output a low level signal.

[0082] It should be noted that in Figure 3 The first AND gate is used to control the abnormal signal and the signal output by the reset chip Reset for judgment. When the reset signal is received at the second input terminal of the first AND gate, the abnormal signal can be controlled to no longer be input through the first input terminal CLK1 of the first D flip-flop D1. The second AND gate is used to control the reset of the counting circuit 202 through the first D flip-flop D1, and to control the reset of the counting circuit 202 through the second input terminal CLR1 and the first output terminal Q1. The third AND gate is used to control the recharging of the second D flip-flop D2. Through the combination of the first and third AND gates and the reset chip Reset, after the controller completes the detection, the first D flip-flop D1, the second D flip-flop D2, and the counting circuit 202 can all be reset so that the controller's detection process can be executed again.

[0083] In a specific implementation, a signal rising edge start-up delay can be used as an example. Before being activated, the first D flip-flop D1 is in a state of waiting for the rising edge of an abnormality signal. When the abnormality signal is received through the second input terminal CLR1, the first D flip-flop D1 is activated. At this time, the first output terminal Q1 outputs a low level, the counting circuit 202 is in a set state, and the second D flip-flop D2 is in a state of waiting for the rising edge of the count completion flag. The first output terminal Q2 of the second D flip-flop D2 outputs a low level. When the abnormality signal is received through the first input terminal CLK1, the first output terminal Q1 outputs a high level timing signal, and the counter in the counting circuit 202 starts timing. After the timing is completed, the timing completion signal is output to the second input terminal CLK2 of the second D flip-flop D2. The first output terminal Q2 of the second D flip-flop D2 outputs an abnormality signal. The second output terminal Q3 of the second D flip-flop clears the timer of the first D flip-flop D1 and the counting circuit 202 through the second AND gate, and the second D flip-flop D2 is cleared through the third AND gate. Of course, the first D flip-flop D1 can also be directly cleared through the reset chip Reset and the first AND gate. After the clearing is completed, the first D flip-flop D1 , the second D flip-flop D2 and the counting circuit 202 are in a state of waiting for the second rising edge of the abnormal signal.

[0084] Reference Figure 4 , in this embodiment, the delay system further includes: a communication circuit 30;

[0085] The communication circuit 30 is connected to the latch circuit 10 and an external terminal.

[0086] It should be noted that after the latch circuit outputs the abnormality signal, in order to ensure that the user is aware that the controller is in an abnormal state, the abnormality signal indicating that the controller is in an abnormal state can also be output to an external terminal through the communication circuit 30, and the controller abnormality prompt can be provided to the user through the external terminal. The communication circuit 30 can be a network dial-up device that sends the abnormality signal of the controller to the external terminal via network dial-up. Of course, the communication circuit 30 can also be a wireless output module that, when connected to the external terminal, can directly output the abnormality signal of the controller to the external terminal via wireless transmission.

[0087] In a specific implementation, when the latch circuit 10 outputs an abnormal signal, it may output the abnormal signal to the communication circuit 30 , and when the communication circuit receives the abnormal signal output by the latch circuit, it may output the abnormal signal to the external terminal.

[0088] In this embodiment, by defining the specific circuitry within latch circuit 10, the controller status can be accurately determined. After the controller outputs an abnormality signal or stops testing when no abnormality has occurred, the components within latch circuit 10 and timing circuit 20 are reset, allowing for more convenient controller testing. Furthermore, by configuring communication circuit 30, an abnormality signal can be directly output to an external terminal to alert the user of an abnormality in the vehicle's controller.

[0089] Furthermore, since the vehicle includes multiple controllers, during the abnormal signal output process, the abnormal signal can carry the identification information of the controller. When the user receives the abnormal signal, he can directly determine which controller in the vehicle is in an abnormal state.

[0090] Reference Figure 5 , Figure 5 This is a first structural diagram of an embodiment of a controller power supply system proposed by the present invention. An embodiment of a controller power supply system of the present invention is proposed based on any one of the first to third embodiments of the above-mentioned delay system.

[0091] In this embodiment, the controller power supply system includes: a voltage conversion circuit 100, a voltage detection circuit 200 and the delay system described in any of the above embodiments;

[0092] The voltage conversion circuit 100 is connected to an external power supply and the controller, and the voltage detection circuit 200 is connected to the controller and the delay system.

[0093] It should be noted that the external power supply is a power source used to power the controller within the vehicle. The external power supply can be a low-voltage battery within the vehicle, or of course, other power sources within the vehicle. The voltage conversion circuit 100 is a circuit used to convert the power voltage output by the external power supply. The voltage conversion circuit 100 can convert the power voltage of the external power supply into the operating voltage required by the controller based on the operating voltage of the controller. For example, if the power voltage of the external power supply is a 12V DC voltage, and the controller only requires a 5V DC voltage, the voltage conversion circuit 100 can convert the 12V DC voltage into a 5V DC voltage to power the controller. For another example, if the power voltage of the external power supply is a 12V AC voltage, and the operating voltage required by the controller is a 5V DC voltage, the controller can also convert the 12V AC voltage into a 12V DC voltage, and then further convert it into a 5V DC voltage. Of course, the voltage conversion circuit 100 can also first convert the 12V AC voltage into a 5V AC voltage, and then convert the 5V AC voltage into a 5V DC voltage. The voltage conversion circuit 100 may include a transformer, a buck-boost circuit, a rectifier circuit, etc.

[0094] It should be understood that the voltage detection circuit 200 is a circuit for detecting the operating voltage of the controller. The voltage detection circuit 200 may include detection devices, such as sampling resistors, sampling capacitors, etc. The voltage detection circuit 200 may be connected to the latch circuit 10 within the delay system, and may output an abnormality signal to the latch circuit 10 when the operating voltage of the controller is not within the standard voltage range.

[0095] In a specific implementation, the voltage conversion circuit 100 converts the external voltage input from the external power supply into the operating voltage required by the controller and outputs it to the controller, thereby enabling the controller to start executing the relevant control process. The voltage detection circuit 200 can detect the operating voltage of the controller during normal operation and output an abnormal signal to the latch circuit 10 in the delay system if the operating voltage is not within the standard voltage range.

[0096] Further, refer to Figure 6 and Figure 7 , Figure 6 This is a second structural diagram of an embodiment of the controller power supply system proposed by the present invention; Figure 7 This is a third structural diagram of an embodiment of the controller power supply system proposed by the present invention.

[0097] In this embodiment, the controller power supply system further includes: a power supply switching circuit 300 and a backup power supply 400:

[0098] The power supply switching circuit 300 is connected to the voltage detection circuit 200 , the backup power supply 400 , and the delay system.

[0099] It should be understood that the crystal oscillator, latch circuit 10, and counter circuit 202 used in the controller all require power to delay the controller's abnormal signals. Typically, these components are powered directly by the controller. If the controller's operating voltage is outside the standard voltage range, the operating voltage provided by the controller to these components may not enable them to operate properly. For example, if the controller's operating voltage is very low, the corresponding voltage supplied to the timing circuit 20 is insufficient, and the timing circuit 20 may be unable to generate a timer.

[0100] To avoid the above-mentioned problems, this embodiment provides a backup power supply 400 and a power supply switching circuit 300. When the controlled operating voltage is abnormal, the power supply to the crystal oscillator, latch circuit 10, and counting circuit 202 is directly switched through the power supply switching circuit 300, and the backup power supply 400 is used to power these components. The backup voltage output by the backup power supply 400 should be the same as the operating voltage required by the crystal oscillator, latch circuit 10, and counting circuit 202. Of course, if the backup voltage output by the backup power supply 400 is different from the operating voltage required by the crystal oscillator, latch circuit 10, and counting circuit 202, an additional voltage conversion circuit can also be used to perform voltage conversion and then power the above-mentioned components.

[0101] In a specific implementation, the voltage detection circuit 200 detects the operating voltage of the controller. When the operating voltage of the controller is not within the standard voltage range, it can output an abnormal signal to the power supply switching circuit 300. When the power supply switching circuit 300 receives the abnormal signal, it outputs the backup voltage output by the backup power supply to the delay system, and then powers the crystal oscillator, the latch circuit 10 and the counting circuit 202, thereby delaying the abnormal signal of the controller and more accurately determining whether the controller is in an abnormal state.

[0102] The standby voltage is a voltage output by a standby power supply, and the standby voltage is usually the same as the operating voltage required by the crystal oscillator, the latch circuit 10 and the counting circuit 202 .

[0103] Reference Figure 8 , Figure 8 This is a flow chart of an embodiment of a controller power supply method proposed in the present invention. Based on the embodiment of the controller power supply system of the above-mentioned delay system, an embodiment of a controller power supply method of the present invention is proposed.

[0104] In this embodiment, the controller power supply method includes:

[0105] Step S10: Detecting the operating voltage of the controller.

[0106] It should be understood that the execution entity of the controller power supply method can be the above-mentioned controller power supply system, which can power the controller and adjust the power supply of the delay system according to the operating voltage of the controller during the power supply process.

[0107] In a specific implementation, the operating voltage of the controller when it is working can be directly collected by using the voltage detection circuit in the controller power supply system.

[0108] Step S20: When the operating voltage is not within the standard voltage range, the delay system records the delay time during which the operating voltage is not within the standard voltage range.

[0109] It is understood that when it is detected that the operating voltage of the controller is not within the standard voltage range, the abnormal signal can be delayed by the delay system and the delay duration of the abnormal signal can be recorded. When the operating voltage of the controller is within the standard voltage range, the voltage detection circuit in the controller power supply system still detects the operating voltage of the controller in real time.

[0110] Step S30: When the delay time reaches a preset time, an abnormal signal is output and power supply to the controller is stopped.

[0111] It is understood that when the delay time for the delay system to record the abnormal signal reaches a preset time, it can be determined that the operating voltage of the controller is indeed abnormal, the abnormal signal can be output, and power supply to the controller can be stopped. The preset time corresponds to the preset number in the counter of the delay system and is the time period used to determine whether the controller has an abnormality.

[0112] When the delay time does not reach the preset time, the voltage detection circuit detects that the operating voltage of the controller is within the standard voltage range, and then stops the current detection process; and re-executes the detection process to determine whether an abnormality occurs in the controller.

[0113] It is understandable that there are other steps in the controller power supply method, such as device resetting in the delay system, etc. These steps can be directly referred to the above-mentioned delay system and controller power supply system embodiments and will not be elaborated here.

[0114] In addition, to achieve the above-mentioned purpose, the present invention also provides a vehicle, in which the above-mentioned controller and the controller power supply system are provided, and the controller power supply system includes a delay system. The specific structure of the controller power supply system and the delay system can refer to the above-mentioned embodiment, and the controller power supply system can be used to execute the steps of the above-mentioned controller power supply method embodiment.

[0115] The above are only preferred embodiments of the present invention and are not intended to limit the patent scope of the present invention. Any equivalent structure or equivalent process transformation made using the contents of the present invention description and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present invention.

Claims

1. A time delay system, characterized in that: The delay system includes: a latch circuit and a timing circuit; The timing circuit includes: an oscillating circuit and a counting circuit; the oscillating circuit is used to output a reference clock signal with the same frequency; The oscillation circuit is connected to the counting circuit, the counting circuit is connected to the latch circuit, and the latch circuit is connected to a controller in the vehicle; The latch circuit is configured to detect an abnormal signal corresponding to when the operating voltage of the controller is not within a standard voltage range, and output a timing signal to the counting circuit when the abnormal signal is detected; The counting circuit is configured to record the number of reference clock signals output by the oscillation circuit upon receiving the timing signal, and output a timing completion signal to the latch circuit when the number of reference clock signals reaches a preset number; The latch circuit is further configured to output the abnormality signal when receiving the timing completion signal.

2. The time delay system according to claim 1, wherein: The oscillation circuit is a crystal oscillator provided in the controller, and the counting circuit is a counter; The output end of the crystal oscillator is connected to the fundamental frequency clock signal input end of the counter, and the signal input end and the signal output end of the counter are both connected to the latch circuit.

3. The time delay system according to claim 2, wherein: The timing circuit further includes: a dial button; The dial button is connected to the counter and is used to input the number code corresponding to the preset number into the counter; The counter is further configured to determine a preset number corresponding to the reference clock signal according to the number code.

4. The time delay system according to claim 1, wherein: The latch circuit includes: a first D flip-flop, a second D flip-flop and a delay circuit; The first input terminal of the first D flip-flop is connected to the abnormal signal output terminal of the controller through the delay circuit, the second input terminal of the first D flip-flop is connected to the abnormal signal output terminal of the controller, and the output terminal of the first D flip-flop is connected to the counting circuit; The first input terminal of the second D flip-flop is connected to the abnormal signal output terminal of the controller, and the second input terminal of the D flip-flop is connected to the output terminal of the counting circuit; The first D flip-flop is configured to be activated when receiving the abnormal signal through the second input terminal, and output a timing signal to the counting circuit when receiving the abnormal signal after the delay of the delay circuit through the first input terminal; The second D flip-flop is configured to output the abnormality signal received through the first input terminal when receiving the timing completion signal output by the counting circuit.

5. The delay system according to claim 4, characterized in that: The latch circuit further includes: a first AND gate, a second AND gate, a third AND gate and a reset chip; The first input end of the first AND gate is connected to the abnormal signal output end of the controller, the input end of the second AND gate, and the second input end of the third AND gate; the second input end of the first AND gate is connected to the reset end of the reset chip, the first input end of the second AND gate, and the first input end of the third AND gate; the output end of the first AND gate is connected to the input end of the delay circuit; The third input terminal of the second AND gate is connected to the second output terminal of the second D flip-flop, and the output terminal of the second AND gate is connected to the second input terminal of the first D flip-flop; The output terminal of the third AND gate is connected to the first input terminal of the second D flip-flop.

6. The time delay system according to claim 1, wherein: The delay system further includes: a communication circuit; The communication circuit is connected to the latch circuit and an external terminal; The communication circuit is used to receive the abnormal signal output by the latch circuit and output the abnormal signal to the external terminal.

7. A controller power supply system, characterized in that: The controller power supply system comprises: a voltage conversion circuit, a voltage detection circuit and the delay system according to any one of claims 1 to 6; The voltage conversion circuit is connected to the external power supply and the controller, and the voltage detection circuit is connected to the controller and the delay system; The voltage conversion circuit is used to convert the external voltage input by the external power supply into the operating voltage required by the controller and output it to the controller; The voltage detection circuit is used to detect the operating voltage of the controller and output an abnormal signal to the delay system when the operating voltage is not within the standard voltage range.

8. The controller power supply system according to claim 7, wherein: The controller power supply system also includes: a power supply switching circuit and a backup power supply: The power supply switching circuit is connected to the voltage detection circuit, the backup power supply and the delay system; The power supply switching circuit is used to output the backup voltage output by the backup power supply to the delay system when receiving the abnormal signal output by the voltage detection circuit.

9. A controller power supply method, characterized in that: The controller power supply method is applied to the controller power supply system according to any one of claims 7 to 8; The controller power supply method includes: Detect the operating voltage of the controller; When the operating voltage is not within the standard voltage range, the delay time during which the operating voltage is not within the standard voltage range is recorded by the delay system; When the delay time reaches a preset time, an abnormal signal is output and power supply to the controller is stopped.

10. A vehicle, characterized in that: The vehicle comprises: a controller and a controller power supply system according to any one of claims 7 to 8.

Images