High-voltage grid protection circuit and device

Abstract

The invention relates to the technical field of electronic circuits, and discloses a high-voltage grid protection circuit and device.The high-voltage grid protection circuit comprises a high-voltage driving circuit, the high-voltage driving circuit comprises a high-voltage PMOS transistor and a high-voltage NMOS transistor, and further comprises a switch and a grid protection circuit which are arranged at the input end of the high-voltage driving circuit, and the grid protection circuit comprises a resistor and a plurality of MOS transistors; the resistor and the MOS tubes are connected in series to form a self-bias structure, the grid protection circuit is respectively connected with the grid and the output end of the high-voltage driving circuit, and the grid voltage of the high-voltage PMOS tubes is increased when the voltage is suddenly changed. A Zener diode is equivalently replaced by the combination of a high-voltage MOS tube and a resistor, a driving circuit output stage of a P tube is structurally protected in a self-bias mode, grid voltage can be rapidly clamped to proper voltage when overvoltage occurs, the specific grid protection function is optimized, meanwhile, the area of a chip is saved, the number of MASKs of the chip is reduced, and the cost is reduced. And the cost is reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of electronic circuits, and in particular to a high-voltage gate protection circuit and device. Background Art

[0002] High-voltage driver circuits are commonly used in motor drive, industrial control, and high-voltage bus applications. They convert input signals into output square waves with specific duty cycles, driving subsequent high-voltage transistors or buses to control various high-voltage devices. High-voltage driver circuits have the following characteristics: The input and output stages are typically powered by low- or medium-voltage power supplies, such as 3.3V, 5V, or 12V. The driver output port produces a square wave with an amplitude close to that power supply voltage. Because this output port is directly connected to a long bus or high-voltage device, it offers high voltage resistance and a degree of high-voltage protection. It's important to note that the gate input signal amplitude of the output transistor is 0-VDD. To ensure good drive capability and signal linearity, output transistors with gate-source voltages that can withstand the same voltage as VDD are selected. The threshold voltage of such output transistors is around 1V, with a typical value of 0.8V. The drain of the output transistor, connected to the high-voltage bus, typically has a voltage V0 that far exceeds VDD and can even go negative, requiring a high voltage rating. Of course, it's possible to increase the input signal amplitude to 0-VO and select an output transistor with a gate-source withstand voltage equal to the output high voltage VO. Alternatively, a charge pump and floating voltage technology can be used to generate a special gate drive signal with a low voltage of VO-5V and a high voltage of VO. This high-voltage drive circuit does not require a gate protection circuit. The disadvantage is that the higher VDD and floating high voltage level place higher demands on the power supply circuit design. Furthermore, the area of a multi-terminal high-voltage MOS transistor is much larger than that of a MOS transistor with a drain withstand voltage, resulting in high cost. Furthermore, the switching speed is slow, and the parasitic resistance is large, which can reduce the performance of the drive circuit.

[0003] For example, if the high-voltage driver circuit's power supply voltage is 5V and the output port's withstand voltage requirement is -24V to 24V, asymmetric high-voltage transistors are typically used for the output. The output stage of the driver circuit and specialized protection circuitry protect the internal 0-5V circuitry from damage by the high voltage at the output port.

[0004] Chinese patent document CN113381591A discloses a "high-side switch driver circuit to protect against reverse high voltage." The circuit comprises a first high-voltage switching transistor and a second high-voltage switching transistor connected in series, as well as a comparator circuit and a floating power supply module. The first high-voltage switching transistor is connected to a power supply, and the second high-voltage switching transistor is connected to an IO port. The first high-voltage switching transistor is connected to a comparator circuit that compares the power supply voltage with the input voltage. When reverse high voltage is present, the gate of the first high-voltage switching transistor is connected to the reverse high voltage, turning the first high-voltage switching transistor off. The floating power supply module is connected to the source of the second high-voltage switching transistor and the common ground of the driver stage. When the IO is at a high voltage, the floating power supply module pulls up the common ground voltage of the driver stage to protect the driver stage. This technical solution lacks an equivalent circuit configuration for gate protection. Conventional gate protection circuits currently employ a Zener diode connected between the gate and source of the output power transistor. This circuit utilizes the Zener diode's characteristic of a fixed voltage of 5-6V after reverse breakdown, combined with other circuits, to clamp the voltage drop between the gate and source of the output transistor within a reasonable voltage range. Summary of the Invention

[0005] The present invention mainly solves the technical problem that the original technical solution lacks an equivalent circuit setting for gate protection. It provides a high-voltage gate protection circuit, which replaces the Zener diode by an equivalent circuit combining a high-voltage MOS tube and a resistor. The structure protects the output stage of the P-tube drive circuit by self-biasing. When an overvoltage occurs, the gate voltage can be quickly clamped to an appropriate voltage, thereby optimizing the gate protection function. At the same time, it saves chip area, reduces the number of MASKs (masks) required in the chip production process, and reduces costs.

[0006] The above-mentioned technical problems of the present invention are mainly solved by the following technical solutions: The present invention includes a high-voltage drive circuit, the high-voltage drive circuit includes an asymmetric high-voltage MOS transistor, and a high-voltage gate protection circuit includes a switch arranged at the input end of the high-voltage drive circuit and a gate protection circuit between the input end and the output end of the high-voltage drive circuit. The gate protection circuit includes a resistor and a plurality of MOS transistors, the resistor and the plurality of MOS transistors are connected in series to form a self-biased structure, and the gate protection circuit is respectively connected to the gate and the output end of the asymmetric high-voltage MOS transistor; when a voltage mutation occurs, the gate voltage of the asymmetric high-voltage MOS transistor is pulled up or down to protect the gate of the asymmetric high-voltage MOS transistor. The number of MOS transistors connected in series can be 2, 3, or 4. When the voltage at the D end of the high-voltage MOS transistor suddenly changes, the voltage at the G end is pulled up or down from 0-VDD to close to the voltage at the D end. No more than 4 MOS transistors are sufficient to meet the sudden voltage requirement.

[0007] Under normal operating conditions, S2 and S1 are closed, and a square wave is input to the VIP node, i.e., the gate of MP1. For example, when VIP = 0V and MP1 is turned on, the voltage Vout at the output port VO is pulled up to VDD - 0.7V. Because MP2's body diode is forward-biased and VIP = 0V, MP3 turns on, causing current to flow from the output port VO. Due to the large resistance (e.g., greater than 100k), this protection branch consumes only a small amount of current.

[0008] When the voltage Vout at the output port VO rapidly rises to a level far exceeding the power supply voltage, S1 and S2 are first disconnected, disconnecting the VIP node, i.e., the gate of MP1, from the previous circuit. The output port VO rapidly pulls up node N (located between MP2 and MP3) to a higher voltage through the body diode of MP2 (the voltage is equal to Vout minus the voltage drop of the MP2 body diode, approximately Vout-Vdon, where Vdon is the turn-on voltage of the body diode, approximately 0.7V). At this time, the voltage at the G terminals of MP2 and MP3 is still relatively low, between 0V and VDD, because they are grounded through resistors. Therefore, the MP3 transistor must be in the on state, rapidly raising the voltage at the D terminal of MP3, i.e., the G terminal voltage, and the voltage at the VIP node to a high voltage close to the N node (the voltage is equal to the voltage at point N minus the threshold voltage of the MP3 transistor, approximately VN-Vth).

[0009] This raises the gate voltage of MP1 to Vout-Vdon-Vth, a high voltage close to Vout. At this point, the GS voltage of MP1 is close to Vout, preventing breakdown and damage due to the rapid rise in Vout. The resulting floating high voltage protects the G and S terminals of MP1.

[0010] When the voltage Vout of the output port VO drops to a negative voltage far below the ground, the body diode of MP2 is reverse biased, the G terminal of MP2 will not be lower than the GND potential, and MP2 is cut off. Therefore, no current will flow through the branch composed of MP2 and MP3 when the output port VO is negative, and the normal operation of other circuits will not be affected.

[0011] When the voltage Vout at the output port VO drops to a negative voltage far below ground, the node P (located between MN2 and MN3) is quickly pulled up to a lower voltage through the body diode of MN2 (the voltage is equal to Vout plus the voltage drop of the body diode of MN2, approximately Vout + Vdon, where Vdon is the turn-on voltage of the body diode, approximately 0.7V). At this time, the voltage at the G terminals of MN2 and MN3 is still high, between 0V and VDD, because they are connected to the power supply through resistors. Therefore, the MN3 transistor must be in the on state, quickly pulling the voltage at the D terminal of MN3, that is, the G terminal, down to a low voltage close to the P node (the voltage is equal to the voltage at point P plus the threshold voltage of the MN3 transistor, approximately VN + Vth).

[0012] This raises the gate voltage of MN1 to Vout+Vdon+Vth, a low voltage close to Vout. At this point, the GS voltage of MN1 is close and will not break down due to the rapid rise in Vout. The resulting floating high voltage protects the G and S terminals of MP1.

[0013] When the voltage Vout at the output port VO drops to a positive voltage far above ground, the body diode of MN2 is reverse biased, the G terminal of MN2 will not be higher than the VDD potential, and MN2 will be cut off. Therefore, no current will flow through the branch formed by MN2 and MN3 when the output port VO is positive, and the normal operation of other circuits will not be affected.

[0014] Preferably, the asymmetric high-voltage MOS transistor includes a high-voltage PMOS transistor MP1. The gate protection circuit includes a positive high-voltage gate protection circuit disposed between the gate and drain of the high-voltage PMOS transistor MP1. The positive high-voltage gate protection circuit includes a high-voltage PMOS transistor MP2 and a high-voltage PMOS transistor MP3. The gates of the high-voltage PMOS transistors MP2 and MP3 are connected and connected to the gate of the high-voltage PMOS transistor MP1. The source of the high-voltage PMOS transistor MP2 is connected to the source of the high-voltage PMOS transistor MP3, and the drain of the high-voltage PMOS transistor MP2 is connected to the drain of the high-voltage PMOS transistor MP1. The drain of the high-voltage PMOS transistor MP1 serves as the output of the high-voltage drive circuit. MP1, MP2, and MP3 are PMOS transistors with D terminals capable of withstanding negative high voltages. During normal operation, the withstand voltages of GS, GB, and SB are relatively low, generally at a minimum of -5V. The withstand voltages of DS and DB are relatively high, and are available in multiple voltage ratings, such as -12V, -24V, and -30V, depending on the circuit.

[0015] Preferably, the drain of the high-voltage PMOS transistor MP3 is grounded via the resistor R1 and is connected to the gates of the high-voltage PMOS transistor MP2 and the high-voltage PMOS transistor MP3.

[0016] Preferably, the asymmetric high-voltage MOS transistor further comprises a high-voltage NMOS transistor MN1, which is connected to the drain of the high-voltage PMOS transistor MP1. The gate protection circuit comprises a negative high-voltage gate protection circuit disposed between the gate and drain of the high-voltage NMOS transistor MN1. The negative high-voltage gate protection circuit comprises high-voltage NMOS transistors MN2 and MN3, with the gates of the high-voltage NMOS transistors MN2 and MN3 connected and connected to the gate of the high-voltage NMOS transistor MN1. The source of the high-voltage NMOS transistor MN2 is connected to the source of the high-voltage NMOS transistor MN3, and the drain of the high-voltage NMOS transistor MN2 is connected to the drain of the high-voltage NMOS transistor MN1. MN1, MN2, and MN3 are NMOS transistors with D-terminals capable of withstanding positive high voltage. During normal operation, the withstand voltages of GS, GB, and SB are relatively low, generally up to +5V. The withstand voltages of DS and DB are relatively high, with various voltage ratings, such as +12V, +24V, and +30V, depending on the circuit.

[0017] Preferably, the drain of the high-voltage NMOS transistor MN3 is connected to the power supply terminal through the resistor R2, and is also connected to the gates of the high-voltage NMOS transistor MN2 and the high-voltage NMOS transistor MN3.

[0018] Preferably, the switch includes a switch S2, the gate of the high-voltage PMOS transistor MP1 is connected to the switch S2, the source is connected to the cathode of the diode D2, and the anode of the diode D2 is connected to the power supply terminal. The resistance of R2 is greater than 10 times the on-resistance of MN3.

[0019] Preferably, the switch includes a switch S1. The gate of the high-voltage NMOS transistor MN1 is connected to the switch S1, and the source is connected to the anode of a diode D1. The cathode of the diode D1 is grounded. The reverse breakdown voltages of D1 and D2 are slightly greater than the DS withstand voltage of all MOS transistors. For example, if the DS withstand voltage of MP1 is -12V, a 13V withstand voltage diode can be used for D1.

[0020] Preferably, the asymmetric high-voltage MOS transistor includes a high-voltage PMOS transistor MP1, and the gate protection circuit includes a forward high-voltage gate protection circuit arranged between the gate and drain of the high-voltage PMOS transistor MP1. The forward high-voltage gate protection circuit includes a high-voltage PMOS transistor MP2, a high-voltage PMOS transistor MP3, and a high-voltage PMOS transistor MP4. The gates of the high-voltage PMOS transistors MP2 and MP4 are connected and connected to the gate of the high-voltage PMOS transistor MP1; the source of the high-voltage PMOS transistor MP2 is connected to the source of the high-voltage PMOS transistor MP3, and the drain of the high-voltage PMOS transistor MP2 is connected to the drain of the high-voltage PMOS transistor MP1. The drain of the high-voltage PMOS transistor MP1 serves as the output end of the high-voltage drive circuit, the drain of the high-voltage PMOS transistor MP3 is connected to the gate, and is connected to the source of the high-voltage PMOS transistor MP4. The drain of the high-voltage PMOS transistor MP4 is grounded through a resistor R1 and is connected to the gates of the high-voltage PMOS transistors MP2 and MP4. The asymmetric high-voltage MOS transistor also includes a high-voltage NMOS transistor MN1, and the drains of MN1 and MP1 are connected. The gate protection circuit includes a negative high-voltage gate protection circuit arranged between the gate and drain of the high-voltage NMOS transistor MN1. The negative high-voltage gate protection circuit includes high-voltage NMOS transistors MN2, MN3, and MN4. The gates of the high-voltage NMOS transistors MN2 and MN4 are connected and connected to the gate of the high-voltage NMOS transistor MN1. The source of the high-voltage NMOS transistor MN2 is connected to the source of the high-voltage NMOS transistor MN3, the drain of the high-voltage NMOS transistor MN2 is connected to the drain of the high-voltage NMOS transistor MN1, the drain and gate of the high-voltage NMOS transistor MN3 are connected, and are connected to the source of the high-voltage NMOS transistor MN4. The drain of the high-voltage NMOS transistor MN4 is connected to the power supply terminal through the resistor R2, and is also connected to the gates of the high-voltage NMOS transistors MN2 and MN4.

[0021] Preferably, the asymmetric high-voltage MOS transistor includes a high-voltage PMOS transistor MP1, and the gate protection circuit includes a forward high-voltage gate protection circuit arranged between the gate and drain of the high-voltage PMOS transistor MP1. The forward high-voltage gate protection circuit includes a high-voltage PMOS transistor MP2, a high-voltage PMOS transistor MP3, a high-voltage PMOS transistor MP4 and a high-voltage PMOS transistor MP5. The gates of the high-voltage PMOS transistors MP2 and MP5 are connected and connected to the gate of the high-voltage PMOS transistor MP1; the source of the high-voltage PMOS transistor MP2 is connected to the source of the high-voltage PMOS transistor MP3, and the drain of the high-voltage PMOS transistor MP2 is connected to the drain of the high-voltage PMOS transistor MP1. The drain of the high-voltage PMOS transistor MP1 serves as the output end of the high-voltage drive circuit, the drain of the high-voltage PMOS transistor MP3 is connected to the gate and to the source of the high-voltage PMOS transistor MP4, the drain of the high-voltage PMOS transistor MP4 is connected to the gate and to the source of the high-voltage PMOS transistor MP5, and the drain of the high-voltage PMOS transistor MP5 is grounded through a resistor R1 and is connected to the gates of the high-voltage PMOS transistors MP2 and MP5. The asymmetric high-voltage MOS transistor also includes a high-voltage NMOS transistor MN1, and the drains of MN1 and MP1 are connected. The gate protection circuit includes a negative high-voltage gate protection circuit arranged between the gate and drain of the high-voltage NMOS transistor MN1. The negative high-voltage gate protection circuit includes high-voltage NMOS transistors MN2, MN3, MN4, and MN5. The gates of the high-voltage NMOS transistors MN2 and MN5 are connected and connected to the gate of the high-voltage NMOS transistor MN1. The source of the high-voltage NMOS transistor MN2 is connected to the source of the high-voltage NMOS transistor MN3, the drain of the high-voltage NMOS transistor MN2 is connected to the drain of the high-voltage NMOS transistor MN1, the drain and gate of the high-voltage NMOS transistor MN3 are connected and connected to the source of the high-voltage NMOS transistor MN4, the drain and gate of the high-voltage NMOS transistor MN4 are connected and connected to the source of the high-voltage NMOS transistor MN5, and the drain of the high-voltage NMOS transistor MN5 is connected to the power supply terminal through the resistor R2, and is also connected to the gates of the high-voltage NMOS transistors MN2 and MN5.

[0022] For example, if only MP2 and MP3 can clamp the GS voltage to 2-3V, increasing the number to MP2, MP3, MP4, and MP5 can clamp the GS voltage to 4-5V. The former will recover slower than the latter. Faster recovery speed is not necessarily better, as the slew rate requirements of high-voltage drive output signals vary depending on the circuit. Choosing the appropriate gate protection circuit depends on the actual application environment.

[0023] The preferred number of high-voltage MOS transistors connected in series is 2-4. Specifically, the clamping voltage generated by the protection circuit composed of four MOS transistors is close to the voltage drop after a Zener diode's reverse breakdown (5-6V), effectively protecting output transistors with a 5V GS withstand voltage. For high-voltage output transistors with a VDD voltage of 12V and a 12V GS withstand voltage, clamping at 5-6V is sufficient to protect the gate, as the gate input signal swing is generally 5V. Clamping at a higher voltage will affect the switching speed of the output transistor.

[0024] A high-voltage gate protection device comprises any one of the above-mentioned high-voltage gate protection circuits and a high-voltage drive circuit.

[0025] The beneficial effects of the present invention are: by equivalently replacing the Zener diode with a high-voltage MOS tube and a resistor, the output stage of the P-tube driving circuit is structurally protected by self-biasing, and the gate voltage can be quickly clamped to an appropriate voltage when an overvoltage occurs, thereby optimizing the protection function for the gate, saving chip area, reducing the number of masks on the chip, and reducing costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 This is a circuit diagram of a high-voltage gate protection circuit provided by Example 1 of the present invention.

[0027] Figure 2 It is a typical high-voltage drive circuit output stage circuit.

[0028] Figure 3 It is a circuit that uses a Zener diode to achieve gate voltage protection.

[0029] Figure 4 This is a waveform diagram of the voltage at the output end of the high-voltage drive circuit provided by the present invention when it rises to a positive voltage far higher than the power supply.

[0030] Figure 5 This is a waveform diagram of the voltage at the output end of the high-voltage drive circuit provided by the present invention when it drops to a negative voltage far below the ground.

[0031] Figure 6 This is a circuit diagram of an equivalent high-voltage gate protection circuit with different numbers of MOS tubes provided by Example 2 of the present invention.

[0032] Figure 7 This is a circuit diagram of another equivalent high-voltage gate protection circuit with a different number of MOS tubes provided by Example 2 of the present invention. DETAILED DESCRIPTION

[0033] In order to make the objectives, technical solutions and advantages of the present invention more clear, the technical solutions of the present application are further described in detail below through examples and in combination with the accompanying drawings. It should be understood that the specific implementation method described here is only an optimal embodiment of the present application, which is only used to explain the present application and does not limit the scope of protection of the present application. All other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.

[0034] Typical high voltage drive circuit output stage circuit such as Figure 2 As shown, the circuit consists of a high-voltage PMOS transistor, a pull-up circuit with a high-voltage diode in series, and a high-voltage NMOS transistor, a pull-down circuit with a high-voltage diode in series. To clearly understand the protection principle of the voltage-withstand circuit, the parasitic body diodes of all MOS transistors are shown. High-voltage MOS transistors are characterized by their GS, GB, and BS components being non-high-voltage tolerant and operating at a low voltage of 5V; DS and DB components being high-voltage tolerant, with the maximum withstand voltage flexibly selected based on the withstand voltage of the output port, such as 12V, 24V, or 30V. The high-voltage diodes prevent the positive high voltage at the output port from flowing current into the low-voltage power supply, or the negative high voltage from drawing current from the ground line, potentially damaging the low-voltage power supply and other 0-5V circuits by pulling them up or down.

[0035] Due to the presence of high-voltage diodes, the high voltage at the output port can damage the gates of the NMOS and PMOS transistors. For example, if the bus port voltage suddenly exceeds the power supply voltage, the PMOS transistor's S terminal will be pulled to a voltage close to the output port's high voltage through its body diode. Furthermore, because the G terminal of the PMOS transistor is not resistant to high voltage, the voltage at the G terminal will drop to 0-5V at the moment the D terminal voltage suddenly changes, inevitably causing G terminal breakdown and damage.

[0036] In order to protect the output tube gate from breakdown damage caused by overvoltage at the output port, the high voltage output stage circuit will be equipped with a gate protection circuit. Figure 3 As shown in the figure, a traditional gate protection circuit is implemented using a Zener diode and a switch across the GS terminal. When a high voltage appears at the source terminal of the MOS transistor, the connection between the previous stage circuit and the output stage circuit is immediately disconnected, that is, S1 and S2 are disconnected. When the voltage difference between SG exceeds the reverse breakdown voltage of the Zener diode, the Zener diode reversely breaks down and maintains the voltage across SG at 5V-6V. This effectively raises the voltage at the G terminal to close to the voltage at the D terminal, thus preventing damage to the output MOS transistor due to overvoltage breakdown.

[0037] This circuit using Zener diodes to achieve gate voltage protection has the following disadvantages: Zener diodes have a complex structure and occupy a large area in planar integrated circuit processes. Since reverse breakdown takes a long time, the instantaneous current flowing through them is proportional to their area. Therefore, a large device area is required to quickly clamp the voltage at the GS terminal of the MOS transistor. The high-voltage MOS transistors in the output stage have a large width-to-length ratio, typically 500 / 1 or 1000 / 1. The parasitic capacitance at the GS terminal is non-negligible and diverts some of the instantaneous current flowing through the Zener diode. Therefore, a larger Zener diode area is required to increase the instantaneous current during reverse breakdown and speed up the reverse breakdown. Zener diode manufacturing typically requires three or more additional photolithography steps, increasing product cost.

[0038] In order to solve the problems of large Zener diode occupation area, high cost and slow reverse breakdown in high-voltage gate protection circuits, the present invention proposes an equivalent solution using a high-voltage MOS tube and a resistor, which does not require a Zener diode. When overvoltage occurs, the gate voltage is quickly clamped to an appropriate voltage, achieving better gate protection function with a smaller chip area.

[0039] Before discussing the exemplary embodiments in more detail, it should be mentioned that some exemplary embodiments are described as processes or methods depicted as flow charts. Although the flow charts describe the operations (or steps) as sequential processes, many of the operations (or steps) therein can be performed in parallel, concurrently, or simultaneously. In addition, the order of the operations can be rearranged. The process can be terminated when its operations are completed, but can also have additional steps not included in the figures; the process can correspond to a method, function, procedure, subroutine, subprogram, etc.

[0040] The technical solution of the present invention will be further specifically described below through embodiments and in conjunction with the accompanying drawings.

[0041] Example 1: A high voltage gate protection circuit of this embodiment, such as Figure 1As shown, a circuit diagram of a high-voltage gate protection circuit is provided, which can be used to protect a high-voltage drive circuit. The high-voltage drive circuit includes asymmetric high-voltage MOSFETs, specifically a high-voltage PMOS transistor MP1 and a high-voltage NMOS transistor MN1. The high-voltage gate protection circuit includes switches disposed at the input end of the high-voltage drive circuit, specifically switches S1 and S2. The gate of the high-voltage PMOS transistor MP1 is connected to switch S2, the drain is connected to the output end, the source is connected to the cathode of diode D2, and the anode of diode D2 is connected to the power supply end. The reverse breakdown voltage of D1 and D2 is slightly greater than the DS withstand voltage of all MOS transistors. For example, if the DS withstand voltage of MN1 is +12V, a 13V withstand voltage diode can be used for D1. The gate of the high-voltage NMOS transistor MN1 is connected to switch S1, the drain is connected to the drain of MP1, and the source is connected to the anode of diode D1. The cathode of diode D1 is grounded. The reverse breakdown voltage of D1 and D2 is slightly greater than the DS withstand voltage of all MOS transistors. For example, if the DS withstand voltage of MN1 is +12V, a 13V withstand voltage diode can be used for D1. The switch remains closed when the high-voltage drive circuit operates normally, and opens when the output terminal is overvoltage.

[0042] The high-voltage gate protection circuit also includes a gate protection circuit disposed between the input and output terminals of the high-voltage drive circuit. This gate protection circuit includes a positive high-voltage gate protection circuit disposed between the drain and gate of the high-voltage PMOS transistor MP1, and a negative high-voltage gate protection circuit disposed between the gate and drain of the high-voltage NMOS transistor MN1. The drain of the high-voltage PMOS transistor MP1 serves as the output terminal of the high-voltage drive circuit and is connected to the drain of the high-voltage NMOS transistor MN1.

[0043] Under normal operating conditions, S2 and S1 are closed, and a square wave is applied to the VIP node, i.e., the MP1 gate. For example, if VIP = 0V and MP1 is open, the VO voltage is pulled up to VDD - 0.7V. Because MP2's body diode is forward-biased and VIP = 0V, MP3 turns on, allowing current to flow from VO. Due to the large resistance (e.g., greater than 100kΩ), this protection branch consumes only a small amount of current.

[0044] VO is the output terminal, and its output voltage is defined as Vout. When Vout rapidly rises to a value far exceeding the power supply voltage, S1 and S2 are first disconnected, disconnecting the VIP node, i.e., the gate of MP1, from the previous circuit. VO rapidly pulls up node N (located between MP2 and MP3) to a higher voltage through MP2's body diode (the voltage is equal to Vout minus the voltage drop of MP2's body diode, approximately Vout - Vdon, where Vdon is the body diode's turn-on voltage, approximately 0.7V). At this time, the voltages at the G terminals of MP2 and MP3 are still relatively low, between 0V and VDD, due to being grounded through resistors. Therefore, MP3 must be in the on state, rapidly raising the voltage at MP3's D terminal, i.e., the G terminal voltage, and the VIP node voltage to a high voltage close to the N node (the voltage is equal to the voltage at point N minus the threshold voltage of MP3, approximately VN - Vth).

[0045] This raises the gate voltage of MP1 to Vout-Vdon-Vth, a high voltage close to the VO voltage. At this point, the GS voltage of MP1 is close and will not break down due to the rapid rise in Vout. The resulting floating high voltage protects the G and S terminals of MP1.

[0046] When the voltage of VO drops to a negative voltage far below the ground, the body diode of MP2 is reverse biased, the G terminal of MP2 will not be lower than the GND potential, and MP2 is cut off. Therefore, no current will flow through the branch composed of MP2 and MP3 when the voltage of VO is negative, and the normal operation of other circuits will not be affected.

[0047] When the voltage of VO drops to a negative voltage far below ground, the node P (located between MN2 and MN3) is quickly pulled up to a lower voltage through the body diode of MN2 (the voltage is equal to the voltage of VO plus the voltage drop of the body diode of MN2, approximately Vout + Vdon, where Vdon is the turn-on voltage of the body diode, approximately 0.7V). At this time, the voltage of the G terminals of MN2 and MN3 is still high at this time, being connected to the power supply through resistors, and is between 0V and VDD. Therefore, the MN3 transistor must be in the open state, and the voltage of the D terminal of MN3, that is, the G terminal, is quickly pulled down to a low voltage close to the P node (the voltage is equal to the voltage at point P plus the threshold voltage of the MN3 transistor, approximately VN + Vth).

[0048] This raises the gate voltage of MN1 to Vout+Vdon+Vth, which is also a low voltage close to the VO voltage. At this time, the GS voltage of MN1 is close and will not be damaged by the rapid increase of VO. The resulting floating high voltage protects the G and S terminals of MP1.

[0049] When the voltage of VO drops to a positive voltage far above ground, the body diode of MN2 is reverse biased, the G terminal of MN2 will not be higher than the VDD potential, and MN2 is cut off. Therefore, no current will flow through the branch composed of MN2 and MN3 when the voltage of VO is positive, and the normal operation of other circuits will not be affected.

[0050] The positive high-voltage gate protection circuit includes high-voltage PMOS transistors MP2 and MP3. The gates of MP2 and MP3 are connected, and also to the gate of MP1. MP1, MP2, and MP3 are PMOS transistors with negative high-voltage protection at their D terminals. The normal operating voltages of GS, GB, and SB are relatively low, typically -5V at the lowest.

[0051] like Figure 6 As shown, the number of MOS tubes connected in series can be 2, 3 or 4, which can clamp the GS terminal voltage difference at 2-3V, 3-4V, and 4-5V respectively. No more than 4 MOS tubes are sufficient to meet the demand for protecting the gate after a sudden voltage change.

[0052] In such Figure 1 In the gate protection circuit shown, the GS voltage of the protected output tube can be clamped to 2-3V. If it needs to be clamped to 3-4V or 4-5V, the number of high-voltage MOS tubes can be increased to 3 or 4, and the connection method can be as follows: Figure 6 and Figure 7 As shown in the figure, different clamping voltages can maintain the output transistor gate-source voltage (Vgs) between 2-5V, allowing the output transistor to operate in different operating ranges, such as weak linear range to strong linear range. When the output voltage (VO) returns to normal, the speed at which the output transistors in different operating ranges transition to the normal conduction state will vary. In practical applications, the switching speed requirements for the drive signal may vary, so it is necessary to flexibly select different gate protection circuits based on the actual operating conditions.

[0053] DS and DB have a high withstand voltage rating and are available in various models, including -12V, -24V, and -30V, depending on the circuit. The source of the high-voltage PMOS transistor MP2 is connected to the source of the high-voltage PMOS transistor MP3, and the drain of the high-voltage PMOS transistor MP2 is connected to the drain of the high-voltage PMOS transistor MP1. The drain of the high-voltage PMOS transistor MP1 serves as the output terminal VO of the high-voltage drive circuit. The drain of the high-voltage PMOS transistor MP3 is grounded through resistor R1 and is also connected to the gates of both the high-voltage PMOS transistors MP2 and MP3. The resistance of R1 and R2 is greater than 10 times the on-resistance of MN3 and MP3.

[0054] The negative high-voltage gate protection circuit includes high-voltage NMOS transistors MN2 and MN3. Their gates are connected, and also to the gate of high-voltage NMOS transistor MN1. MN1, MN2, and MN3 are NMOS transistors capable of withstanding positive high voltages at their D terminals. The normal operating voltages of GS, GB, and SB are relatively low, typically a maximum of +5V. DS and DB have higher voltage ratings, available in various voltage ranges, including +12V, +24V, and +30V, depending on the circuit.

[0055] The source of the high-voltage NMOS transistor MN2 is connected to the source of the high-voltage NMOS transistor MN3 , and the drain of the high-voltage NMOS transistor MN2 is connected to the drain of the high-voltage NMOS transistor MN1 .

[0056] The drain of the high-voltage NMOS transistor MN3 is connected to the power supply terminal through resistor R2, and is also connected to the gates of the high-voltage NMOS transistors MN2 and MN3. The resistance of R1 and R2 is greater than 10 times the on-resistance of MN3 and MP3.

[0057] Example 2 To protect the output transistor gate from breakdown damage caused by overvoltage at the output port, high-voltage output stage circuits incorporate a gate protection circuit. Traditional gate protection circuits utilize a Zener diode and a switch connected across the GS terminal. When high voltage appears at the source of the MOS transistor, the circuit immediately disconnects the previous stage from the output stage, effectively disconnecting S1 and S2. When the voltage difference between SG exceeds the Zener diode's reverse breakdown voltage, the Zener diode reversely breaks down and maintains the voltage across SG at 5V to 6V. This effectively raises the voltage at the G terminal to near the voltage at the D terminal, thus preventing damage to the output MOS transistor caused by overvoltage breakdown.

[0058] Zener diodes have a complex structure and occupy a large area in planar integrated circuit processes. Since reverse breakdown takes a long time, the instantaneous current flowing through them is proportional to their area. Therefore, a large device area is required to quickly clamp the voltage at the GS terminal of the MOS transistor. The high-voltage MOS transistors in the output stage have a large width-to-length ratio, typically 500 / 1 or 1000 / 1. The parasitic capacitance at the GS terminal is non-negligible and diverts some of the instantaneous current flowing through the Zener diode. Therefore, a larger Zener diode area is required to increase the instantaneous current during reverse breakdown and speed up the reverse breakdown. Zener diode manufacturing typically requires three or more additional photolithography steps, increasing product cost.

[0059] In order to solve the problems of large Zener diode occupation area, high cost and slow reverse breakdown in high-voltage gate protection circuits, and to adapt to more practical working conditions, the present invention proposes an equivalent solution using high-voltage MOS transistors and resistors. A special high-voltage MOS transistor and resistor are used to generate a floating high-voltage and low-voltage gate protection circuit. The circuit has a fast turn-on speed and does not require a Zener diode. When an overvoltage occurs, the gate voltage is quickly clamped to an appropriate voltage. This achieves better gate protection function with a smaller chip area, improves the performance of the gate protection circuit, reduces costs, and can also clamp the voltage of the protected output tube GS to a higher voltage. The specific structure is as follows: The positive high-voltage gate protection circuit consists of resistor R1 and two high-voltage PMOS transistors MP2 and MP3 connected in series. The sources of the PMOS transistors are connected together, with the D terminal of the upper PMOS transistor MP2 connected to the output terminal. The drain of the lower PMOS transistor is connected to the G terminals of both transistors and to the G terminal of the output transistor MP1 to be protected. The drain of the output transistor MP1 serves as the output terminal. The negative high-voltage gate protection circuit consists of resistor R2 and two high-voltage NMOS transistors connected in series. The sources of the NMOS transistors are connected together, with the D terminal of the lower NMOS transistor MN2 connected to the output terminal, and the drain of the upper NMOS transistor MN3 connected to the G terminals of both transistors and to the G terminal of the output transistor MN1 to be protected.

[0060] The gate of the output tube is connected to the previous stage circuit through switches S1 and S2.

[0061] MP1, MP2, and MP3 are PMOS transistors with a D-terminal voltage capability that can withstand negative high voltages. During normal operation, the voltage tolerances of GS, GB, and SB are relatively low, typically as low as -5V. DS and DB have higher voltage tolerances, with various models offering -12V, -24V, and -30V tolerances depending on the circuit.

[0062] MN1, MN2, and MN3 are NMOS transistors with forward high voltage resistance at their D terminals. During normal operation, the voltage resistance of GS, GB, and SB is relatively low, typically up to +5V. DS and DB have higher voltage resistances, with various models offering +12V, +24V, and +30V resistances depending on the circuit.

[0063] The resistance of R1 and R2 is greater than 10 times the on-resistance of MN3 and MP3.

[0064] The reverse breakdown voltage of D1 and D2 is slightly higher than the DS withstand voltage of all MOS tubes. For example, if MN1 withstands +12V, D1 can use a 13V withstand voltage diode.

[0065] When working, the working principle is as follows: Under normal operating conditions, S2 and S1 are closed, and a square wave is applied to the VIP node, i.e., the MP1 gate. For example, if VIP = 0V and MP1 is open, the VO voltage is pulled up to VDD - 0.7V. Because MP2's body diode is forward-biased and VIP = 0V, MP3 turns on, allowing current to flow from VO. Due to the large resistance (e.g., greater than 100kΩ), this protection branch consumes only a small amount of current.

[0066] When Vout, the output port voltage, rapidly rises to a point far exceeding the power supply voltage, S1 and S2 are first disconnected, disconnecting the VIP node, or MP1's gate, from the previous circuit. Vout rapidly pulls node N (located between MP2 and MP3) to a higher voltage through MP2's body diode (the voltage is equal to Vout minus the MP2 body diode voltage drop, approximately Vout-Vdon, where Vdon is the body diode's turn-on voltage, approximately 0.7V). At this point, the G-terminal voltages of MP2 and MP3 are still relatively low, between 0V and VDD, due to being grounded through resistors. Therefore, MP3 must be in the on state, rapidly raising MP3's D-terminal, or G-terminal voltage, and the VIP node voltage to a high voltage close to the N-node (the voltage is equal to the N-point voltage minus the MP3 transistor's threshold voltage, approximately VN-Vth).

[0067] This raises the gate voltage of MP1 to Vout-Vdon-Vth, a high voltage close to Vout. At this point, the GS voltage of MP1 is close to Vout, preventing breakdown and damage due to the rapid rise in Vout. The resulting floating high voltage protects the G and S terminals of MP1.

[0068] Working waveform Figure 4 shown.

[0069] When the output voltage Vout of VO drops to a negative voltage far below ground, the body diode of MP2 is reverse biased, the G terminal of MP2 will not be lower than the GND potential, and MP2 is cut off. Therefore, no current will flow through the branch composed of MP2 and MP3 when the voltage of VO is negative, and the normal operation of other circuits will not be affected.

[0070] When the output voltage Vout of VO drops to a negative voltage far below ground, the node P (located between MN2 and MN3) is quickly pulled up to a lower voltage through the body diode of MN2 (the voltage is equal to Vout plus the voltage drop of the body diode of MN2, approximately Vout + Vdon, where Vdon is the turn-on voltage of the body diode, approximately 0.7V). At this time, the voltage at the G terminals of MN2 and MN3 is still high, between 0V and VDD, because they are connected to the power supply through resistors. Therefore, the MN3 transistor must be in the on state, quickly pulling the voltage at the D terminal of MN3, that is, the G terminal, down to a low voltage close to the P node (the voltage is equal to the voltage at point P plus the threshold voltage of the MN3 transistor, approximately VN + Vth).

[0071] This raises the gate voltage of MN1 to Vout+Vdon+Vth, a low voltage close to the VO output voltage Vout. At this point, the GS voltage of MN1 is close and will not break down due to the rapid rise in VO. The resulting floating high voltage protects the G and S terminals of MP1.

[0072] When the output voltage Vout of VO drops to a positive voltage far above ground, the body diode of MN2 is reverse biased, the G terminal of MN2 will not be higher than the VDD potential, and MN2 will be cut off. Therefore, no current will flow through the branch composed of MN2 and MN3 when the VO voltage is positive, and the normal operation of other circuits will not be affected.

[0073] Waveform Figure 5 shown.

[0074] It should be noted that MP2, MP3, MN2, and MN3 do not need to be too large. High-voltage MOS tubes with the same voltage resistance as the output driver tube can be used. This saves chip area, reduces the number of masks on the chip, and reduces costs.

[0075] It's important to note that the resistor value should be significantly larger than the on-resistance of the MOS transistor in series and the series resistance of the body diode to ensure the generated floating high voltage remains within a reasonable range. However, a resistor that is too large will occupy more area, so the resistor value should be selected based on various factors. A value of 10-50 times the on-resistance of the MOS transistor is sufficient, for example, 100k-500k.

[0076] The gate of high-voltage NMOS transistor MN1 is connected to switch S1, the source is connected to the positive terminal of diode D1, and the negative terminal of diode D1 is grounded. Up to two high-voltage MOS transistors with the same connection method as MP3 and MN3 can be added between MP3 and resistor R1, and between MN3 and R2. The connection method is: the gate and drain are shorted as the first terminal, and the source and substrate are shorted as the second terminal. The first terminal is connected to the ground (positive high-voltage protection circuit) or the power supply (negative high-voltage protection circuit) and then connected to the second terminal of the next MOS transistor. MOS transistors are connected in series until resistor R1 or R2 is reached. The non-ground terminal of R1 and the non-power supply terminal of R2 are still connected to the gates of MP2 and MN2, and are also connected to the gates of the high-voltage output transistors to be protected.

[0077] like Figure 6As shown, the asymmetric high-voltage MOS transistor includes a high-voltage PMOS transistor MP1, and the gate protection circuit includes a forward high-voltage gate protection circuit arranged between the gate and drain of the high-voltage PMOS transistor MP1. The forward high-voltage gate protection circuit includes a high-voltage PMOS transistor MP2, a high-voltage PMOS transistor MP3, and a high-voltage PMOS transistor MP4. The gates of the high-voltage PMOS transistors MP2 and MP4 are connected and connected to the gate of the high-voltage PMOS transistor MP1; the source of the high-voltage PMOS transistor MP2 is connected to the source of the high-voltage PMOS transistor MP3, and the drain of the high-voltage PMOS transistor MP2 is connected to the drain of the high-voltage PMOS transistor MP1. The drain of the high-voltage PMOS transistor MP1 serves as the output end of the high-voltage drive circuit, the drain of the high-voltage PMOS transistor MP3 is connected to the gate, and is connected to the source of the high-voltage PMOS transistor MP4. The drain of the high-voltage PMOS transistor MP4 is grounded through a resistor R1 and is also connected to the gates of the high-voltage PMOS transistors MP2 and MP4. The asymmetric high-voltage MOS transistor also includes a high-voltage NMOS transistor MN1, the drains of which are connected to those of MP1. The gate protection circuit includes a negative high-voltage gate protection circuit disposed between the gate and drain of the high-voltage NMOS transistor MN1. The negative high-voltage gate protection circuit includes a high-voltage NMOS transistor MN2, a high-voltage NMOS transistor MN3, and a high-voltage NMOS transistor MN4. The gates of the high-voltage NMOS transistors MN2 and MN4 are connected and connected to the gate of the high-voltage NMOS transistor MN1. The source of the high-voltage NMOS transistor MN2 is connected to the source of the high-voltage NMOS transistor MN3, the drain of the high-voltage NMOS transistor MN2 is connected to the drain of the high-voltage NMOS transistor MN1, the drain and gate of the high-voltage NMOS transistor MN3 are connected and connected to the source of the high-voltage NMOS transistor MN4. The drain of the high-voltage NMOS transistor MN4 is connected to the power supply terminal via a resistor R2 and is also connected to the gates of the high-voltage NMOS transistors MN2 and MN4.

[0078] like Figure 7As shown, the asymmetric high-voltage MOS transistor includes a high-voltage PMOS transistor MP1, and the gate protection circuit includes a forward high-voltage gate protection circuit arranged between the gate and drain of the high-voltage PMOS transistor MP1. The forward high-voltage gate protection circuit includes a high-voltage PMOS transistor MP2, a high-voltage PMOS transistor MP3, a high-voltage PMOS transistor MP4 and a high-voltage PMOS transistor MP5. The gates of the high-voltage PMOS transistors MP2 and MP5 are connected and connected to the gate of the high-voltage PMOS transistor MP1; the source of the high-voltage PMOS transistor MP2 is connected to the source of the high-voltage PMOS transistor MP3, the drain of the high-voltage PMOS transistor MP2 is connected to the drain of the high-voltage PMOS transistor MP1, and the drain of the high-voltage PMOS transistor MP1 serves as the output end of the high-voltage driving circuit. The drain of the high-voltage PMOS transistor MP3 is connected to the gate and connected to the source of the high-voltage PMOS transistor MP4. The drain of the high-voltage PMOS transistor MP4 is connected to the gate and connected to the source of the high-voltage PMOS transistor MP5. The drain of the high-voltage PMOS transistor MP5 is grounded through a resistor R1 and is also connected to the gates of the high-voltage PMOS transistors MP2 and MP5. The asymmetric high-voltage MOS transistor further includes a high-voltage NMOS transistor MN1, the drains of which are connected to those of MP1. The gate protection circuit includes a negative high-voltage gate protection circuit disposed between the gate and drain of the high-voltage NMOS transistor MN1. The negative high-voltage gate protection circuit includes high-voltage NMOS transistors MN2, MN3, MN4, and MN5. The gates of the high-voltage NMOS transistors MN2 and MN5 are connected and are also connected to the gate of the high-voltage NMOS transistor MN1. The source of the high-voltage NMOS transistor MN2 is connected to the source of the high-voltage NMOS transistor MN3, the drain of the high-voltage NMOS transistor MN2 is connected to the drain of the high-voltage NMOS transistor MN1, the drain and gate of the high-voltage NMOS transistor MN3 are connected and are also connected to the source of the high-voltage NMOS transistor MN4, the drain and gate of the high-voltage NMOS transistor MN4 are connected and are also connected to the source of the high-voltage NMOS transistor MN5. The drain of the high-voltage NMOS transistor MN5 is connected to the power supply terminal via a resistor R2 and is also connected to the gates of the high-voltage NMOS transistors MN2 and MN5.

[0079] It should be noted that in this embodiment, the number of high-series MOS tubes in the gate protection circuit is preferably 2-4. Specifically, in most practical application scenarios, the clamping voltage generated by the protection circuit composed of 4 MOS tubes is close to the voltage drop after the reverse breakdown of a Zener tube (5-6V), which can effectively protect the output tube with a GS withstand voltage of 5V. For high-voltage output tubes with a VDD voltage of 12V and a GS withstand voltage of 12V, since the gate input signal swing is generally 5V, clamping at 5-6V is sufficient to protect the gate. Clamping at a higher voltage will affect the switching speed of the output tube. If there are more than 4 high-voltage MOS tubes, not only will there be a waste of clamping voltage, but the volume will also be closer to the conventional Zener tube form, making it difficult to achieve the effect of saving space and cost.

[0080] Example 3 The present application also provides a high-voltage gate protection device, comprising the high-voltage drive circuit and the gate protection circuit in any of the above embodiments.

[0081] The specific embodiments described herein are merely examples of the spirit of the present invention. The above embodiments only express several implementation methods of the present application, and their descriptions are relatively specific and detailed, but they cannot be understood as limiting the scope of protection of the present application. It should be pointed out that those skilled in the art of the present application can make various modifications or supplements to the described specific embodiments or replace them in a similar manner, but they will not deviate from the spirit of the present application or exceed the scope defined by the appended claims. For those of ordinary skill in the art, multiple variations and improvements can be made without departing from the concept of the present application. Therefore, the scope of protection of the present application should be based on the appended claims.

Claims

1. A high-voltage gate protection circuit can be used to protect a high-voltage drive circuit, wherein the high-voltage drive circuit includes an asymmetric high-voltage MOS transistor, characterized in that: The high-voltage gate protection circuit includes a switch arranged at the input end of the high-voltage drive circuit and a gate protection circuit between the input end and the output end of the high-voltage drive circuit. The gate protection circuit includes a resistor and a plurality of MOS transistors, which are connected in series to form a self-biased structure. The gate protection circuit is respectively connected to the gate and output end of the asymmetric high-voltage MOS transistor; when the voltage suddenly changes, the gate voltage of the asymmetric high-voltage MOS transistor is pulled up or down to protect the gate of the asymmetric high-voltage MOS transistor.

2. The high voltage gate protection circuit according to claim 1, characterized in that: The asymmetric high-voltage MOS transistor includes a high-voltage PMOS transistor MP1. The gate protection circuit includes a forward high-voltage gate protection circuit arranged between the gate and drain of the high-voltage PMOS transistor MP1. The forward high-voltage gate protection circuit includes a high-voltage PMOS transistor MP2 and a high-voltage PMOS transistor MP3. The gates of the high-voltage PMOS transistor MP2 and the high-voltage PMOS transistor MP3 are connected and connected to the gate of the high-voltage PMOS transistor MP1; the source of the high-voltage PMOS transistor MP2 is connected to the source of the high-voltage PMOS transistor MP3, and the drain of the high-voltage PMOS transistor MP2 is connected to the drain of the high-voltage PMOS transistor MP1. The drain of the high-voltage PMOS transistor MP1 serves as the output end of the high-voltage drive circuit.

3. A high voltage gate protection circuit according to claim 2, characterized in that: The drain of the high-voltage PMOS transistor MP3 is grounded through the resistor R1 and is connected to the gates of the high-voltage PMOS transistor MP2 and the high-voltage PMOS transistor MP3.

4. A high voltage gate protection circuit according to claim 2 or 3, characterized in that: The asymmetric high-voltage MOS transistor also includes a high-voltage NMOS transistor MN1, and the drains of MN1 and MP1 are connected; the gate protection circuit includes a negative high-voltage gate protection circuit arranged between the gate and drain of the high-voltage NMOS transistor MN1; the negative high-voltage gate protection circuit includes a high-voltage NMOS transistor MN2 and a high-voltage NMOS transistor MN3, and the gates of the high-voltage NMOS transistors MN2 and MN3 are connected and connected to the gate of the high-voltage NMOS transistor MN1; the source of the high-voltage NMOS transistor MN2 is connected to the source of the high-voltage NMOS transistor MN3, and the drain of the high-voltage NMOS transistor MN2 is connected to the drain of the high-voltage NMOS transistor MN1.

5. A high voltage gate protection circuit according to claim 4, characterized in that: The drain of the high-voltage NMOS transistor MN3 is connected to the power supply terminal through the resistor R2 , and is also connected to the gates of the high-voltage NMOS transistor MN2 and the high-voltage NMOS transistor MN3 .

6. A high voltage gate protection circuit according to claim 2, characterized in that: The gate of the high-voltage PMOS transistor MP1 is connected to the switch S2 , the source is connected to the cathode of the diode D2 , and the anode of the diode D2 is connected to the power supply terminal.

7. The high voltage gate protection circuit according to claim 4, characterized in that: The gate of the high-voltage NMOS transistor MN1 is connected to the switch S1 , the source is connected to the anode of the diode D1 , and the cathode of the diode D1 is grounded.

8. The high voltage gate protection circuit according to claim 1, characterized in that: The asymmetric high-voltage MOS transistor includes a high-voltage PMOS transistor MP1, and the gate protection circuit includes a forward high-voltage gate protection circuit arranged between the gate and drain of the high-voltage PMOS transistor MP1. The forward high-voltage gate protection circuit includes a high-voltage PMOS transistor MP2, a high-voltage PMOS transistor MP3, and a high-voltage PMOS transistor MP4. The gates of the high-voltage PMOS transistors MP2 and MP4 are connected and connected to the gate of the high-voltage PMOS transistor MP1; the source of the high-voltage PMOS transistor MP2 is connected to the source of the high-voltage PMOS transistor MP3, and the drain of the high-voltage PMOS transistor MP2 is connected to the drain of the high-voltage PMOS transistor MP1, which together serve as the output end of the high-voltage drive circuit; the drain and gate of the high-voltage PMOS transistor MP3 are connected to the source of the high-voltage PMOS transistor MP4, and the drain of the high-voltage PMOS transistor MP4 is grounded through a resistor R1 and is connected to the gates of the high-voltage PMOS transistors MP2 and MP4; The asymmetric high-voltage MOS transistor also includes a high-voltage NMOS transistor MN1, the drains of which are connected to those of MP1. The gate protection circuit includes a negative high-voltage gate protection circuit disposed between the gate and drain of the high-voltage NMOS transistor MN1. The negative high-voltage gate protection circuit includes high-voltage NMOS transistors MN2, MN3, and MN4, the gates of which are connected to each other and to the gate of the high-voltage NMOS transistor MN1. The source of the high-voltage NMOS transistor MN2 is connected to the source of the high-voltage NMOS transistor MN3, the drain of the high-voltage NMOS transistor MN2 is connected to the drain of the high-voltage NMOS transistor MN1, the drain and gate of the high-voltage NMOS transistor MN3 are connected to the source of the high-voltage NMOS transistor MN4, the drain of the high-voltage NMOS transistor MN4 is connected to the power supply terminal via a resistor R2, and is also connected to the gates of the high-voltage NMOS transistors MN2 and MN4. The drain of the high-voltage PMOS transistor MN1 serves as the output terminal of the high-voltage drive circuit.

9. The high voltage gate protection circuit according to claim 1, characterized in that: The asymmetric high-voltage MOS transistor includes a high-voltage PMOS transistor MP1, and the gate protection circuit includes a forward high-voltage gate protection circuit arranged between the gate and drain of the high-voltage PMOS transistor MP1. The forward high-voltage gate protection circuit includes a high-voltage PMOS transistor MP2, a high-voltage PMOS transistor MP3, a high-voltage PMOS transistor MP4 and a high-voltage PMOS transistor MP5. The gates of the high-voltage PMOS transistor MP2 and the high-voltage PMOS transistor MP5 are connected and connected to the gate of the high-voltage PMOS transistor MP1; the source of the high-voltage PMOS transistor MP2 is connected to the source of the high-voltage PMOS transistor MP3. The drain of the high-voltage PMOS tube MP2 is connected to the drain of the high-voltage PMOS tube MP1, and together serve as the output end of the high-voltage drive circuit. The drain and gate of the high-voltage PMOS tube MP3 are connected to the source of the high-voltage PMOS tube MP4. The drain and gate of the high-voltage PMOS tube MP4 are connected to the source of the high-voltage PMOS tube MP5. The drain of the high-voltage PMOS tube MP5 is grounded through the resistor R1 and connected to the gates of the high-voltage PMOS tube MP2 and the high-voltage PMOS tube MP5. The drain of the high-voltage PMOS tube MP1 serves as the output end of the high-voltage drive circuit. The asymmetric high-voltage MOS transistor further comprises a high-voltage NMOS transistor MN1, wherein the drains of MN1 and MP1 are connected; the gate protection circuit comprises a negative high-voltage gate protection circuit provided between the gate and drain of the high-voltage NMOS transistor MN1; the negative high-voltage gate protection circuit comprises a high-voltage NMOS transistor MN2, a high-voltage NMOS transistor MN3, a high-voltage NMOS transistor MN4 and a high-voltage NMOS transistor MN5, wherein the gates of the high-voltage NMOS transistors MN2 and MN5 are connected and are also connected to the gate of the high-voltage NMOS transistor MN1; the high-voltage NMOS transistor MN2 The source of the high-voltage NMOS transistor MN3 is connected to the source of the high-voltage NMOS transistor MN3, the drain of the high-voltage NMOS transistor MN2 is connected to the drain of the high-voltage NMOS transistor MN1, the drain and gate of the high-voltage NMOS transistor MN3 are connected to the source of the high-voltage NMOS transistor MN4, the drain and gate of the high-voltage NMOS transistor MN4 are connected to the source of the high-voltage NMOS transistor MN5, the drain of the high-voltage NMOS transistor MN5 is connected to the power supply end through the resistor R2, and is also connected to the gates of the high-voltage NMOS transistors MN2 and MN5. The drain of the high-voltage PMOS transistor MN1 serves as the output end of the high-voltage drive circuit.

10. A high voltage gate protection device, characterized in that: It comprises the high-voltage gate protection circuit and the high-voltage drive circuit as described in any one of claims 1 to 9.

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