Multi-level straight drive circuit of depletion type switching device

Abstract

The invention discloses a multi-electric-level straight drive circuit of a depletion type switching device, which is characterized in that by dynamically switching positive voltage, zero voltage and deep and shallow negative voltage, the positive voltage is utilized to reduce on resistance in a conduction stage, the deep negative voltage is utilized to quickly cut off current in a turn-off stage, and then the shallow negative voltage is switched to maintain a turn-off state, so that the static power consumption is remarkably reduced. A surge suppression circuit and a power driver work cooperatively, surge current is suppressed through a current-limiting resistor and a fast bypass switch at the moment of starting, and a short circuit Ra is formed after negative voltage is established to reduce loss; and before power failure, the capacitor stored energy is released through the active discharge switch, so that mistaken switching-on caused by residual voltage is eliminated. Through system-level innovation, the direct connection problem of a depletion type device is effectively solved, and a high-efficiency, reliable and compact solution is provided for a high-power-density power supply system.

Description

Technical Field

[0001] The invention relates to a multi-level direct drive circuit of a depletion-type switching device, belonging to the technical field of integrated circuit design. Background Art

[0002] Gallium nitride (GaN) devices, as representatives of third-generation semiconductors, demonstrate significant advantages in areas such as efficient energy conversion and electric vehicle drive thanks to their high electron mobility, low conduction losses, and high-frequency operation. However, GaN devices are categorized as depletion-mode (D-mode) and enhancement-mode (E-mode) based on their driving characteristics, and these two types present fundamental differences in circuit design. Depletion-mode devices are on at zero gate voltage and require a negative voltage (e.g., -4V to -10V) to turn them off. Enhancement-mode devices, on the other hand, are off by default at zero gate voltage and require a positive voltage (e.g., +5V to +6V) to turn them on. While this characteristic gives depletion-mode devices superior conduction performance, their "normally on" nature means that if the driver circuit fails to establish a negative voltage immediately upon system power-up, the input voltage will short-circuit the device, inducing inrush current and potentially damaging the device. Furthermore, if the energy storage capacitor is not actively discharged during system power-down, residual voltage may remain on through parasitic circuits, leading to the risk of secondary shoot-through. In contrast, while enhancement-mode devices inherently avoid the shoot-through problem, their higher on-resistance and cost limit their widespread application in high-voltage, high-current scenarios. Therefore, solving the shoot-through problem of depletion-mode devices while simultaneously unleashing their performance potential has become a core challenge in high-reliability power supply design.

[0003] A traditional surge suppression solution such as Figure 1 As shown, this surge suppression circuit is connected in series between the bridge rectifier and the energy storage capacitor. It uses a surge suppression limiting resistor RT in parallel with a relay, and the circuit is placed at positions A, B, or C. This circuit is simple, easy to drive, low-cost, and simple to control. However, the relay is large, and its resistance after conduction is over 50mΩ, resulting in high operating losses, making it unsuitable for the design of high-power, high-density, and high-efficiency power supplies. RT often uses a thermistor to suppress the inrush current generated at power-up. After the power supply is operating normally, the relay delays the current limiting current short-circuit to reduce power consumption. However, the relay's on-resistance of approximately 100mΩ is still large, and the surge suppression circuit is connected in series with the main power circuit, resulting in high conduction current. The losses generated by the relay are still significant. Furthermore, the relay's large size makes it unsuitable for the design requirements of high-power-density power supplies. The relay also requires an additional driver and a third-party power supply, making the circuit complex and costly.

[0004] Another traditional surge suppression solution such as Figure 2As shown, this solution places the surge suppression resistor RT below C5, with the other end grounded. At the moment of power-on, RT, connected in series with C5, suppresses current. When C5 is fully charged and the inrush current returns to normal, the depletion-mode gallium nitride (GaN) power device Qr is turned on by the control and drive circuitry, short-circuiting RT and redirecting the current through Qr. RT no longer consumes power, and Qr's low on-resistance also reduces its power consumption. Furthermore, since neither Qr nor RT are part of the main power circuit, the current flowing through it is only 3%-20% of the main power circuit, further reducing power consumption.

[0005] like Figure 3 and 4 As shown in the figure, there are two connection methods for single-tube depletion-mode gallium nitride (GaN) power devices: direct drive and cascade.

[0006] In direct-drive circuits, the isolated driver must adopt a positive and negative voltage control strategy: positive voltage turns Q2 on, and negative voltage turns it off. This circuit has a fatal flaw because Q2 is a depletion-mode device. During startup and power-down, the driver has no output, but Q2 remains in a naturally on state. If this state persists for too long, excessive current in Q2 can burn out the device.

[0007] In the cascade circuit, GaN device Q2 forms a cascade connection with enhancement-mode Si-based MOSFET Q3. The isolated driver actually indirectly turns Q2 on and off by driving Q3. Because Q3 is an enhancement-mode device, it does not require positive or negative voltages; only single-voltage control is required. Furthermore, this circuit avoids the problem of excessive current burning components during startup and power-down, as in direct-drive circuits. However, the addition of Q3 in series increases the circuit's on-resistance, thereby increasing operating losses. Q3's large junction capacitance also limits the circuit's operating frequency.

[0008] like Figure 5 and Figure 6 As shown in the figure, dual-bridge depletion-mode gallium nitride (GaN) power devices can be connected in series or cascade. However, the dual-bridge structure has a fatal flaw. Because Q1 and Q2 are depletion-mode devices, both bridge transistors are naturally on during power-on and power-off. This can cause shoot-through failures and damage the device. To prevent shoot-through, especially during power-on and power-off, an enhancement-mode Si-based MOSFET is often required.

[0009] In a series circuit, GaN devices Q1 and Q2 are connected in series with an enhancement-mode Si-based MOSFET Q3, each using three independent drivers. Q2 and Q3 turn on and off simultaneously, while Q1 turns on and off 180° out of phase with Q2 and Q3. This approach is uncommon because the timing control of the three independent drivers is complex. Furthermore, the series approach uses multiple stages of circuitry to achieve shutdown, adding negative voltage, resulting in complex circuitry, bulky design, and low efficiency.

[0010] In a cascade circuit, GaN device Q2 is cascaded with enhancement-mode Si-based MOSFET Q3, effectively integrating Q2 and Q3 into a single device. Q2 and Q3 naturally switch on and off simultaneously, while Q1 switches on and off 180° out of phase with Q2 and Q3. This approach is the most common and relatively simple to control. While the cascade approach simplifies the drive logic, it struggles with high-frequency switching requirements, and delayed dynamic response leads to increased switching losses.

[0011] Whether it is a series or cascade circuit, Q3 is connected in series, which will increase the on-resistance in the circuit and thus increase the working loss, and the large junction capacitance of Q3 will also limit the operating frequency of the circuit.

[0012] Furthermore, traditional protection circuits (such as pre-charge circuits and RC delay circuits) rely on additional components and have slow response times, making them ineffective at suppressing inrush currents at startup. Shutdown protection often relies on passive discharge resistors, which are inefficient and difficult to precisely control the discharge timing. These limitations make it difficult for existing solutions to balance dynamic performance, system efficiency, and reliability. In multi-level topologies, the risk of device shoot-through and losses are particularly prominent. Furthermore, the three-level drive gate-source voltage (VGS) of enhancement-mode devices typically consists of positive, negative, and 0V. Restoring to 0V can be easily achieved by short-circuiting, but this is more difficult to achieve if the three-level VGS voltages are positive, relatively negative, and relatively negative. A short-circuit only yields 0V, not a relatively negative voltage. Summary of the Invention

[0013] The object of the present invention is to provide a multi-level direct drive circuit for a depletion-type switching device, so as to solve the problem of direct conduction during startup and shutdown and improve the reliability of the device.

[0014] The purpose of the present invention is achieved through the following technical solutions:

[0015] A multi-level direct drive circuit for a depletion-type switching device includes resistors Ra, Rc, and Rx, a diode group Da, a capacitor C1, power devices Q1, Q2, Q3, Q4, and Q5, and also includes an isolated three-level switching high-end device drive unit, an isolated three-level switching low-end device drive unit, and a surge suppression time control unit. The source of the power device Q5 is connected to a negative voltage. The resistor Rc is a gate-source discharge resistor of the power device Q5, one end of which is connected to the source of the power device Q5 and the other end is connected to the gate of the power device Q5. The gate of Q5 is connected to a voltage regulator diode ZD. 1, the positive electrode of the voltage regulator tube ZD1 is connected to the gate of the power device Q4, the drain of the power device Q5 is connected to the gate of the power device Q3, the source of the power device Q3 is connected to the source of the power device Q4 and the negative electrode of the diode group Da, the drain of the power device Q3 is connected to one end of the resistor Rx, and the other end of the resistor Rx is connected between the output of the high-end device drive unit and the gate of Q1 to prevent the output of the high-end device drive unit from short-circuiting after Q3 is turned on, the source of the power device Q1 is connected to the drain of the power device Q2, and the source of the power device Q2 is connected to the diode The positive electrode of group Da, the negative electrode of capacitor C1, and the drain of power device Q4 are connected, and the resistor Ra is connected in parallel with the diode group Da. The surge suppression time control unit is used to provide drive signals to the power devices Q4 and Q5, and provide a voltage input terminal for the direct drive circuit. The drain of the power device Q4 is connected to the reference zero potential, the negative input terminal of the input terminal is connected to the negative electrode of the diode group Da, and the positive input terminal is connected to the drain of the power device Q1 and the positive electrode of the capacitor C1 at the same time. The high-end device drive unit adopts positive and negative voltage isolation power supply, providing the power device Q1 with three kinds of voltages: positive voltage, first negative voltage, and second negative voltage. The low-end device driving unit is used to provide a driving signal to Q2. The low-end device driving unit adopts positive and negative voltage isolation power supply to provide three level states of positive voltage, first negative voltage and second negative voltage to the power device Q2, and the absolute value of the first negative voltage is higher than the second negative voltage. The power device Q2 is turned on at positive voltage and turned off at the first negative voltage, and its gate-source voltage is restored to the second negative voltage after being turned off.

[0016] Preferably, the surge suppression time control unit includes a diode D1, resistors R1, R2, R3, R4, R5 and R6, a capacitor C2, transistors M1 and M2, the collector of transistor M2 is connected to the power supply voltage source Vcc of the direct drive circuit, the signal output by the emitter is the control signal of the power devices Q4 and Q5, the base is connected to one end of the resistor R5, the other end of the resistor R5 is connected to the emitter of the transistor M1, the collector of the transistor M1 is simultaneously connected to one end of the capacitor C2 and one end of the resistor R3, and the input end of the direct drive circuit is between one end of the resistor R3 and the positive electrode of the diode D1, the base is connected to one end of the resistor R6, the other end of the resistor R6 is simultaneously connected to the other end of the capacitor C2, the other end of the resistor R3 and one end of the resistor R2, the resistor R2 is connected in series with R1, the other end of the resistor R1 is connected to the negative electrode of the diode D1, one end of the resistor R4 is connected to the collector of the transistor M2, and the other end is connected to the base of the transistor M2, wherein the transistor M1 is a PNP transistor and the transistor M2 is an NPN transistor.

[0017] Preferably, the control logic of the surge suppression timing control unit is: the node connecting the resistors R2, R3, R6 and the capacitor C2 is defined as point C, and the voltage Vc at point C is detected. When Vc is lower than the voltage source input voltage Vcc, the transistor M1 is turned on and the base of M2 is pulled down, so that M2 is turned off. The surge suppression timing control unit outputs a low-level signal, the power device Q4 is turned off, the Zener diode ZD1 is blocked, and the power device Q5 is turned off; otherwise, a high-level signal is output to drive Q4 to turn on, the Zener diode ZD1 is connected, and Q5 is turned on.

[0018] Preferably, the high-end device driving unit has the same structure as the low-end device driving unit, and controls the power devices Q1 and Q2 to be turned on and off 180 degrees out of phase, that is, when Q1 is turned on, Q2 is turned off, and when Q2 is turned on, Q1 is turned off. In the high-end device driving unit, the input voltage is converted by the push-pull circuit, and then rectified and filtered by diodes Dp1, Dp2, capacitors Cp1, and Cp2 to output two sets of symmetrical positive and negative voltages, which are recorded as the first positive voltage and the first negative voltage. The first positive voltage is filtered by capacitor Cp3 and linearly stepped down by LDO to the second positive voltage, which is provided to the single voltage isolation driver chip as the driving power supply voltage. The two positive voltages and the first negative voltage are divided by resistors Rg1, Rg2, and Rg3, and then added together to generate a third negative voltage that is less than the first negative voltage. The third negative voltage is sent to the analog switch via diode Dp3. The single-voltage isolation driver chip has a set of PWM signal inputs and outputs VOA1 and VOA2 based on the PWM signals. VOA1 and VOA2 operate 180 degrees out of phase. VOA1 is connected to the gate of power device Q1 via resistor Rg1, and the gate of power device Q1 is connected to VOA2 via diode Dg1. The output signal of VOA2 is also sent to the analog switch via diode Dg1 and resistors Rg2 and Rg3.

[0019] When VOA1 outputs a high level, VOA2 is in a high-impedance state, the analog switch is in the cut-off state, and the power device Q1 is turned on by positive voltage;

[0020] When VOA2 outputs a low level, VOA1 is in a high-impedance state. Diode Dg1 first pulls down the gate-source voltage of the power device Q1 to 0V, and then the gate voltage of Q1 is pulled down to the first negative voltage through Rg3, the analog switch, and Rg2. The power device Q1 is turned off and then returns to the second negative voltage, where the second negative voltage is the weighted sum of the first negative voltage and the third negative voltage.

[0021] Preferably, the analog switch includes an operational amplifier Us1, XOR gates Us2 and Us3 with enable terminals, a delay buffer Us4, transistors Ms1 and Ms2, a diode Ds1, resistors Rs1, Rs3, Rs4, Rs5, and Rs6, one end of the resistor Rg2 is connected between VOA2 and the negative electrode of the diode Dg1, and the other end is respectively connected to one end of the resistor Rs1, one end of the resistor Rs5, and one end of the resistor Rs6, the other end of the resistor Rs1 is connected to the negative input terminal x1 of the operational amplifier Us1, and the positive input terminal x2 of Us1 is connected in series with the resistors Rs3 and Rs4 through an additional positive voltage supply to divide the voltage to the reference zero potential of Us1. The output end of Us1 is connected to an input end of the exclusive OR gate Us2 and an input end of the exclusive OR gate Us3. One end of the resistor Rg3 is connected between the positive electrode of the diode Dg1 and the gate of the power device Q1, and the other end is connected to the other input end of the exclusive OR gate Us2 and the other input end of the exclusive OR gate Us3. The enable ends of the exclusive OR gates Us2 and Us3 are both connected to the resistor Rs3 to judge the level signal, which is valid under a low-level signal. The output end of the exclusive OR gate Us2 is connected to the gate of the transistor Ms1 to provide a control signal. The other two stages of the transistor Ms1 are respectively connected to the input first negative voltage and the other end of the resistor Rs5. The output end of the exclusive OR gate Us3 is connected to the gate of the transistor Ms2 through the delay buffer Us4 to provide a control signal. The other two stages of the transistor Ms2 are respectively connected to the input third negative voltage and the positive electrode of the diode Ds1. The negative electrode of the diode Ds1 is connected to the other end of the resistor Rs6.

[0022] Preferably, the power devices Q1, Q2, Q3, and Q5 are all p-type transistors or depletion-mode gallium nitride-based power devices, and the power device Q4 is an n-type transistor or an enhancement-mode gallium nitride-based power device.

[0023] Preferably, a power insertion circuit is further included, wherein the input end of the power insertion circuit is connected to the source of the power device Q4, the output end is connected to the drain of Q1, and is connected to the positive electrode of the capacitor C1. The power insertion circuit is a direct short circuit or a power factor correction circuit.

[0024] Preferably, the analog switch further includes a resistor Rs2 , one end of which is connected to the positive input terminal x2 of the operational amplifier Us1 , and the other end of which is connected between the transistor Ms2 and the diode Ds1 .

[0025] Preferably, the diode group Da is composed of several diodes connected in series.

[0026] To simplify the circuit, the additional positive voltage power supply can be the same as the negative voltage power supply of the power device Q5, and can be selected from the isolated power supply in the drive unit. The drive unit can be a high-end device drive unit or a low-end device drive unit. Considering the wiring position, the wiring of the low-end device drive unit is more convenient.

[0027] The present invention discloses a multi-level direct drive circuit for a depletion-type switching device. It overcomes technical difficulties through innovative design. The core of the circuit lies in the integration of negative voltage three-level drive technology and dynamic shoot-through suppression mechanism. Traditional drive relies on single-level switching, resulting in high turn-off loss and limited response. The present invention dynamically switches between positive voltage (+6V), zero voltage (0V) and negative voltage (-10V / -4V), uses positive voltage to reduce on-resistance in the on-state, and quickly cuts off the current through deep negative voltage (-10V) in the off-state, and then switches to shallow negative voltage (-4V) to maintain the off state, significantly reducing static power consumption. To address the risk of shoot-through during startup, the surge suppression circuit works in conjunction with the power driver: at the moment of startup, the current limiting resistor (Ra) and the fast bypass switch (Q4) are used to suppress the inrush current, and after the negative voltage is established, Ra is short-circuited to reduce losses; before power failure, the active discharge switch (Q3) is used to release the capacitor energy storage to eliminate the false start caused by the residual voltage. Furthermore, the dual-isolation architecture for power and drive, combined with a dynamic negative voltage switching unit, utilizes analog switches and logic gates to precisely control the gate voltage of high-end devices, resolving the slow response and imprecise level transitions associated with traditional isolated drivers. This patented system-level innovation not only effectively addresses the pass-through problem of depletion-mode devices, but also provides an efficient, reliable, and compact solution for high-power density power systems.

[0028] The beneficial effects of the present invention are as follows:

[0029] 1. Isolated positive and negative voltage three-level drive: reduces reverse working loss and improves device working reliability;

[0030] 2. Combination of surge suppression circuit and power device driver: solve the problem of power-on direct current;

[0031] 3. Complete capacitor discharge before power off: solve the problem of shutdown pass-through;

[0032] 4. Double isolation of power supply and drive (optional). BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 For traditional surge suppression solutions1.

[0034] Figure 2 For traditional surge suppression solutions2.

[0035] Figure 3 It is a direct drive connection method for single-tube depletion-mode gallium nitride (GaN) power devices.

[0036] Figure 4 It is a cascade connection method for single-tube depletion-mode gallium nitride (GaN) power devices.

[0037] Figure 5 It is a series connection method of bridge-type dual-tube depletion-mode gallium nitride (GaN) power devices.

[0038] Figure 6 It is a cascade connection method of bridge-type dual-tube depletion-mode gallium nitride (GaN) power devices.

[0039] Figure 7 This is a multi-level direct drive circuit diagram of a depletion-type switching device of the present invention.

[0040] Figure 8 This is a timing diagram of the circuit startup operation of the present invention.

[0041] Figure 9 This is a timing diagram of the circuit shutdown or input power-down operation of the present invention.

[0042] Figure 10 The present invention is an implementation plan for a surge suppression time control unit.

[0043] Figure 11 Implementation plan for Q1 and Q2 drive units.

[0044] Figure 12 Implementation of an analog switch unit.

[0045] Figure 13 This is the voltage change effect diagram after implementation. DETAILED DESCRIPTION

[0046] To make the objectives, technical solutions, and advantages of the present invention more apparent, the following describes the technical solutions in the embodiments of the present invention in more detail with reference to the accompanying drawings. Throughout the drawings, identical or similar reference numerals represent identical or similar elements or elements having identical or similar functions. The described embodiments are only some, not all, of the embodiments of the present invention.

[0047] All other embodiments obtained by persons of ordinary skill in the art based on the embodiments of the present invention without creative work shall fall within the scope of protection of the present invention.

[0048] Example 1

[0049] like Figure 7As shown, the depletion-mode GaN device direct drive circuit with no insertion loss has a pure DC input current or a pulsed DC formed by rectified AC, and includes: resistors Ra, Rc, and Rx, a diode group Da, a capacitor C1, and power devices Q1, Q2, Q3, Q4, and Q5. The power devices Q1, Q2, Q3, and Q5 are all p-type transistors or depletion-mode GaN-based power devices, and the power device Q4 is an n-type transistor or an enhancement-mode GaN-based power device.

[0050] It also includes a high-end device driving unit, a low-end device driving unit and a surge suppression time control unit. The source of the power device Q5 is connected to a negative voltage of -10V, which is a negative voltage in the symmetrical positive and negative voltages output by the low-end device driving unit. The resistor Rc is the gate-source bleeder resistor of the power device Q5, which is commonly but not limited to 2k-20kΩ. One end is connected to the source of the power device Q5, and the other end is connected to the gate of the power device Q5. The gate of Q5 is connected to the negative electrode of the voltage regulator ZD1. The value of ZD1 is commonly but not limited to 2-10V. The positive electrode of the voltage regulator ZD1 is connected to the gate of the power device Q4, and the drain of the power device Q5 is connected to the power device Q 3, the source of the power device Q3 is connected to the source of the power device Q4 and the negative electrode of the diode group Da at the same time, the drain of the power device Q3 is connected to one end of the resistor Rx, the high-end device driving unit adopts positive and negative voltage isolation power supply, and provides the power device Q1 with three levels of positive voltage, first negative voltage and second negative voltage, and the absolute value of the first negative voltage is higher than the second negative voltage. When the voltage is positive, the power device Q1 is turned on, and when the voltage is first negative, the power device Q1 is turned off, and after turning off, its gate-source voltage is restored to the second negative voltage. The low-end device driving unit is used to provide a driving signal to Q2. The low-end device driving unit adopts positive and negative voltage isolation power supply to provide the power device Q1 with three levels of positive voltage, first negative voltage and second negative voltage. Component Q2 provides three levels of positive voltage, first negative voltage and second negative voltage, and the absolute value of the first negative voltage is higher than the second negative voltage. When the voltage is positive, the power device Q2 is turned on, and when the voltage is first negative, the power device Q2 is turned off, and after turning off, its gate-source voltage is restored to the second negative voltage. The other end of the resistor Rx is connected between the output of the high-end device driving unit and the gate of Q1 to prevent the output of the high-end device driving unit from being short-circuited after Q3 is turned on. The source of the power device Q1 is connected to the drain of the power device Q2, and the source of the power device Q2 is simultaneously connected to the positive electrode of the diode group Da, the negative electrode of the capacitor C1, and the drain of the power device Q4. The resistor Ra is connected to the two The diode group Da is connected in parallel, and Ra is connected in series with the input to suppress the input surge current. Its resistance is usually designed to be in the range of several ohms to tens of ohms. It can also suppress the through-current of Q1 and Q2. The surge suppression timing control unit is used to provide drive signals to the power devices Q4 and Q5, and provide a voltage input end to the direct drive circuit. At the same time, the surge suppression timing control unit can also detect whether the input is power-off. Ra can be short-circuited through Q4, and the drain of the power device Q4 is connected to the reference zero potential. The negative input end of the input end is connected to the negative electrode of the diode group Da, and the positive input end is connected to the drain of the power device Q1 and the positive electrode of the capacitor C1 at the same time.

[0051] like Figure 10 As shown, the surge suppression time control unit includes a diode D1, resistors R1, R2, R3, R4, R5 and R6, a capacitor C2, transistors M1 and M2, the collector of transistor M2 is connected to an external power supply Vcc, VCC comes from an external independent power supply, which is common but not limited to 12-20V, the emitter outputs a control signal for power devices Q4 and Q5, the base is connected to one end of resistor R5, the other end of resistor R5 is connected to the emitter of transistor M1, the collector of transistor M1 is connected to one end of capacitor C2 and one end of resistor R3 at the same time, the The voltage input terminal of the direct drive circuit is connected between one end and the positive electrode of the diode D1. The base is connected to one end of the resistor R6. The other end of the resistor R6 is connected to the other end of the capacitor C2, the other end of the resistor R3 and one end of the resistor R2. The resistors R2 and R1 are connected in series. The other end of the resistor R1 is connected to the negative electrode of the diode D1. One end of the resistor R4 is connected to the collector of the transistor M2, and the other end is connected to the base of the transistor M2. The transistor M1 is a PNP transistor, and the transistor M2 is an NPN transistor. M1, M2, R4, R5, and R6 constitute a logic control unit.

[0052] The control logic of the surge suppression time control unit is as follows: the node where resistors R2, R3, R6 and capacitor C2 are connected is defined as point C, and the voltage V at point C is detected. c , when V c Lower than the voltage source input voltage V cc When , transistor M1 is turned on and pulls down the base of M2, causing M2 to turn off. The surge suppression time control unit outputs a low-level 0V signal, the power device Q4 is turned off, the voltage regulator ZD1 is not connected, the power device Q5 is turned off, and Q3 is naturally turned on; otherwise, a high-level signal is output to drive Q4 to turn on, the voltage regulator ZD1 is connected, Q5 is turned on, the gate of Q3 is pulled down to -10V, and Q3 is turned off.

[0053] like Figure 11As shown, the structure of the high-end device driving unit is the same as that of the low-end device driving unit, and the power devices Q1 and Q2 are controlled to be turned on and off 180 degrees out of phase, that is, when Q1 is turned on, Q2 is turned off, and when Q2 is turned on, Q1 is turned off. In the high-end device driving unit, the input voltage is converted by the push-pull circuit, and then rectified and filtered by diodes Dp1, Dp2, capacitors Cp1, and Cp2 to output two sets of symmetrical positive and negative voltages, which are commonly but not limited to +10V and -10V, and are recorded as the first positive voltage and the first negative voltage. The first positive voltage +10V is filtered by capacitor Cp3 and linearly stepped down by LDO to the second positive voltage +6V, which is provided to the single voltage isolation driver chip as the driving power supply voltage. The two positive voltages +6V and the first negative voltage -10V are divided by resistors Rg1, Rg2, and Rg3, and then added together to generate a third negative voltage -4V, which is less than the first negative voltage. The first negative voltage is sent to the analog switch, and the third negative voltage is sent to the analog switch via diode Dp3. The single-voltage isolation driver chip has a set of PWM signal inputs and outputs VOA1 and VOA2 based on the PWM signals. VOA1 and VOA2 operate 180 degrees out of phase. VOA1 is connected to the gate of power device Q1 via resistor Rg1, and the gate of power device Q1 is connected to VOA2 via diode Dg1. The output signal of VOA2 is also sent to the analog switch via diode Dg1 and resistors Rg2 and Rg3.

[0054] When VOA1 outputs a high level, VOA2 is in a high-impedance state, the analog switch is in the cut-off state, and the power device Q1 is turned on by positive voltage;

[0055] When VOA2 outputs a low level, VOA1 is in a high-impedance state. Diode Dg1 first pulls down the gate-source voltage of the power device Q1 to 0V, and then the gate voltage of Q1 is pulled down to -10V through Rg3, the analog switch, and Rg2. The power device Q1 is turned off and then returns to the second negative voltage, where the second negative voltage is the weighted sum of the first negative voltage and the third negative voltage.

[0056] like Figure 12As shown, the structure of the analog switch includes an operational amplifier Us1, XOR gates Us2 and Us3 with enable terminals, a delay buffer Us4, transistors Ms1 and Ms2, a diode Ds1, resistors Rs1, Rs3, Rs4, Rs5, and Rs6. One end of the resistor Rg2 is connected between VOA2 and the cathode of the diode Dg1, and the other end is connected to one end of the resistor Rs1, one end of the resistor Rs5, and one end of the resistor Rs6 respectively. The other end of the resistor Rs1 is connected to the negative input terminal x1 of the operational amplifier Us1. The positive input terminal x2 of Us1 is connected in series with the resistors Rs3 and Rs4 through an additional positive voltage supply to divide the voltage to the reference zero potential of Us1. The output terminal of Us1 is connected to one end of the XOR gate Us2. An input terminal and an input terminal of an XOR gate Us3 are connected. One end of resistor Rg3 is connected between the anode of diode Dg1 and the gate of power device Q1, and the other end is connected to the other input terminal of XOR gate Us2 and the other input terminal of XOR gate Us3. The output terminal of XOR gate Us2 is connected to the gate of transistor Ms1 to provide a control signal. The other two stages of transistor Ms1 are respectively connected to the input first negative voltage and the other end of resistor Rs5. The output terminal of XOR gate Us3 is connected to the gate of transistor Ms2 through delay buffer Us4 to provide a control signal. The other two stages of transistor Ms2 are respectively connected to the input third negative voltage and the anode of diode Ds1. The cathode of diode Ds1 is connected to the other end of resistor Rs6. Resistor Rs2 may also be included. One end of resistor Rs2 is connected to the positive input terminal x2 of op amp Us1, and the other end is connected between transistor Ms2 and diode Ds1.

[0057] Ms1 and Ms2 are enhancement type n-type transistors.

[0058] The analog switch operates as follows: When VOA1 outputs a high level, the voltage at point a is high, as is point b, and Ds1 is reverse-blocked. The voltage at point a is fed through Rg2 and Rs1 to the negative input x1 of Us1. Us1's positive input x2 is divided down to Us1's reference zero potential via the +6V supply and the series connection of Rs3 and Rs4. When VOA1 outputs a high level, the voltage at point x1 is higher than that at point x2, and Us1's output y1 is low. At this point, Us2's enable pin is high, its output is in a high-impedance state, and Ms1 is turned off. During this process, Us1's reference zero potential is effectively -10V. When VOA1's high-level output voltage is +6V relative to the source of power device Q1 or Q2, its reference zero potential relative to Us1 is +16V. Similarly, Us1's supply voltage is also effectively +16V.

[0059] In addition, at this time, the enable terminal of Us3 is at a high level, the output y2 of Us3 is also in a high-impedance state, Ms2 is also in a shut-off state, point x3 is floating, and Rs2 does not affect the voltage at point x2.

[0060] When VOA2 outputs a low level, point b is at a low level, point a is also pulled low, y1 is at a high level, the enable end of Us2 is at a low level, the two inputs of Us2 are one high and one low, the output of Us2 is at a high level, Ms1 is turned on, and the gate voltage of the power device Q1 or Q2 (i.e., the voltage at point a) is pulled down to -10V through Rg2, Rs5, and Ms1, and the power device is turned off. Similarly, the output of Us3 is also high, Ms2 is turned on, and after a delay of Us4, it drives Ms2 to turn on. -4V is sent to the positive terminal of US1 (node x2) through RS2, and is superimposed with the voltage divider of RS3 and RS4. By adjusting the resistance values of RS2, RS3, and RS4, the voltage of node x2 can be adjusted to ensure that it is higher than the voltage of node x1 (greater than 0V), ensuring that the output of US1 is high at this time. -4V is sent to point x0 through Rs6, Ds1, and Ms2, and is weighted with the voltage of -10V sent to point x0 through Rs5 and Ms1, so that the gate voltage of power device Q1 or Q2 (i.e., point a voltage) is too high to a smaller negative voltage state. The negative voltage value of point X0 can be adjusted by adjusting the ratio of Rs5 and Rs6.

[0061] It can also include a power insertion circuit, the input end of which is connected to the source of the power device Q4, the output end is connected to the drain of Q1, and is connected to the positive electrode of the capacitor C1. The power insertion circuit can be directly short-circuited or inserted into a common power factor correction circuit.

[0062] The timing diagram of the startup operation is as follows Figure 8 As shown, at the moment of power on, the input voltage is loaded. Due to the presence of large capacitor C1, the input current i0 (i0 is ic1 (that is, Figure 7 A surge spike occurs at the sum of i1) and i2 (the sum of the two components). The surge current flows through the parallel connection of Ra and Da, generating a high negative voltage (between -10V and -3V) at point b. At this time, since Q3 is in a naturally on state, the conduction of Q3 pulls the gate voltage of Q1 to the negative voltage at point b, forcing Q1 to turn off and preventing the direct conduction of Q1 and Q2. At this point, as long as the input remains, the loop from the input to C1 to point a and then to point b will continue to operate, and point b will always maintain a high negative voltage state (between -10V and -3V), thus ensuring that Q1 is always forced to turn off.

[0063] Q4 short-circuits Ra, reducing the negative voltage at point b (greater than -2V), thus affecting Q1's effective shutdown. Similarly, the conduction of Q3 also affects Q1's effective shutdown. Therefore, the operating timing of Q3 and Q4 must ensure Q1's effective shutdown and prevent shoot-through.

[0064] When the surge current duration ends, as long as Q3 remains on and Q4 remains off, point b will always maintain a high negative voltage state (between -10V and -3V), thus ensuring that Q1 is always forced to be turned off.

[0065] After the drive signals for Q1 and Q2 arrive and Q1 and Q2 enter their normal 180° phase-shifted on and off state, Q3 is turned off and Q4 is turned on. After Q3 is turned off, it will no longer hinder the normal on and off of Q1, and after Q4 is turned on, it will reduce the voltage drop across Ra, thereby reducing loop operating losses.

[0066] Shutdown or input power-down working sequence diagram is as follows Figure 9 As shown in the figure, the logic of the shutdown or input power-off moment is exactly the opposite of the startup moment.

[0067] After shutdown, due to the presence of large capacitor C1, the voltage on capacitor C1 begins to drop, accompanied by a delay in the input current i0 before slowly decreasing. To prevent a direct pass through in the loop from C1 to Q1 and Q2, Q1 must be forcibly turned off before the drivers of Q1 and Q2 are turned off. This is done by turning Q3 back on and Q4 back off at the same time when a drop in input voltage is detected, causing the voltage at point b to return to a higher negative voltage (between -10V and -3V), forcing Q1 to shut down.

[0068] In addition, it is also necessary to ensure that the power-off speed of the driving power supply of Q1 and Q2 is slower than the power-off speed of C1, so that Q1 and Q2 will terminate the normal 180° phase-shifted switching and closing working state only when the voltage of C1 drops to a lower value.

[0069] like Figure 13 As shown in the figure, with the use of an isolated three-level switching driver, the voltage across power device Q1 or Q2 transitions from two levels to three. The advantage of three-level switching is that the voltage drop during reverse conduction during the device's dead time is reduced, resulting in lower losses. Furthermore, the reduced negative voltage effectively improves device reliability.

[0070] The above embodiments are preferred implementation modes of the present invention, but the implementation modes of the present invention are not limited to the above embodiments. Any other changes, modifications, substitutions, combinations, and simplifications that do not deviate from the spirit and principles of the present invention should be considered as equivalent replacement methods and are included in the scope of protection of the present invention.

Claims

1. A multi-level direct drive circuit for a depletion-mode switching device, characterized in that: include: Resistors Ra, Rc, Rx, diode group Da, capacitor C1, power devices Q1, Q2, Q3, Q4, Q5, also include an isolated three-level switching high-end device drive unit, an isolated three-level switching low-end device drive unit and a surge suppression time control unit. The source of the power device Q5 is connected to a negative voltage. The resistor Rc is the gate-source discharge resistor of the power device Q5, one end of which is connected to the source of the power device Q5, and the other end is connected to the gate of the power device Q5. The gate of Q5 is connected to the negative electrode of the voltage regulator tube ZD1, and the positive electrode of the voltage regulator tube ZD1 is connected to the power supply. The gate of the power device Q4 is connected to the gate of the power device Q5, the drain of the power device Q3 is connected to the gate of the power device Q3, the source of the power device Q3 is connected to the source of the power device Q4 and the cathode of the diode group Da, the drain of the power device Q3 is connected to one end of the resistor Rx, and the other end of the resistor Rx is connected between the output of the high-end device drive unit and the gate of Q1 to prevent the output of the high-end device drive unit from short-circuiting after Q3 is turned on. The source of the power device Q1 is connected to the drain of the power device Q2, and the source of the power device Q2 is connected to the anode of the diode group Da and the capacitor C 1, the drain of the power device Q4 is connected, the resistor Ra is connected in parallel with the diode group Da, the surge suppression time control unit is used to provide a driving signal to the power devices Q4 and Q5, and provide a voltage input terminal for the direct drive circuit, the drain of the power device Q4 is connected to the reference zero potential, the negative input terminal of the input terminal is connected to the negative terminal of the diode group Da, and the positive input terminal is connected to the drain of the power device Q1 and the positive terminal of the capacitor C1 at the same time. The high-end device driving unit adopts positive and negative voltage isolation power supply, and provides the power device Q1 with three level states of positive voltage, first negative voltage and second negative voltage, and The absolute value of the first negative voltage is higher than the second negative voltage. The power device Q1 is turned on when the voltage is positive, and is turned off when the voltage is the first negative voltage. After turning off, the gate-source voltage is restored to the second negative voltage. The low-end device driving unit is used to provide a driving signal to Q2. The low-end device driving unit adopts positive and negative voltage isolated power supply to provide the power device Q2 with three level states: positive voltage, first negative voltage and second negative voltage. The absolute value of the first negative voltage is higher than the second negative voltage. The power device Q2 is turned on when the voltage is positive, and is turned off when the voltage is the first negative voltage. After turning off, the gate-source voltage is restored to the second negative voltage.

2. The multi-level direct drive circuit of the depletion-mode switching device according to claim 1, characterized in that: The surge suppression time control unit includes a diode D1, resistors R1, R2, R3, R4, R5 and R6, a capacitor C2, transistors M1 and M2, the collector of transistor M2 is connected to the power supply voltage source Vcc of the direct drive circuit, the signal output by the emitter is the control signal of the power devices Q4 and Q5, the base is connected to one end of the resistor R5, the other end of the resistor R5 is connected to the emitter of the transistor M1, the collector of the transistor M1 is simultaneously connected to one end of the capacitor C2 and one end of the resistor R3, and the area between one end of the resistor R3 and the positive electrode of the diode D1 serves as the input end of the direct drive circuit, the base is connected to one end of the resistor R6, the other end of the resistor R6 is simultaneously connected to the other end of the capacitor C2, the other end of the resistor R3 and one end of the resistor R2, the resistor R2 is connected in series with R1, the other end of the resistor R1 is connected to the negative electrode of the diode D1, one end of the resistor R4 is connected to the collector of the transistor M2, and the other end is connected to the base of the transistor M2, wherein the transistor M1 is a PNP transistor and the transistor M2 is an NPN transistor.

3. The multi-level direct drive circuit of the depletion-mode switching device according to claim 2, characterized in that: The control logic of the surge suppression time control unit is as follows: the node where resistors R2, R3, R6 and capacitor C2 are connected is defined as point C, and the voltage V at point C is detected. c , when V c Lower than the voltage source input voltage V cc When , transistor M1 is turned on and pulls down the base of M2, causing M2 to turn off. The surge suppression time control unit outputs a low-level signal, the power device Q4 is turned off, the voltage regulator ZD1 is blocked, and the power device Q5 is turned off; otherwise, a high-level signal is output to drive Q4 to turn on, the voltage regulator ZD1 is connected, and Q5 is turned on.

4. The multi-level direct drive circuit of a depletion-mode switching device according to claim 2, wherein: The high-end device driving unit has the same structure as the low-end device driving unit, and controls the power devices Q1 and Q2 to be turned on and off 180 degrees out of phase, that is, when Q1 is turned on, Q2 is turned off, and when Q2 is turned on, Q1 is turned off. In the high-end device driving unit, the input voltage is converted by the push-pull circuit, and then rectified and filtered by diodes Dp1, Dp2, capacitors Cp1, and Cp2 to output two sets of symmetrical positive and negative voltages, which are recorded as the first positive voltage and the first negative voltage. The first positive voltage is filtered by capacitor Cp3 and linearly stepped down by LDO to the second positive voltage, which is provided to the single voltage isolation driver chip as the driving power supply voltage. The second positive voltage and the first negative voltage are The resistors Rg1, Rg2, and Rg3 divide and superimpose the voltage to generate a third negative voltage that is less than the first negative voltage. The first negative voltage is sent to the analog switch, and the third negative voltage is sent to the analog switch via diode Dp3. The single-voltage isolation driver chip has a set of PWM signal inputs and outputs VOA1 and VOA2 based on the PWM signal. VOA1 and VOA2 operate 180 degrees out of phase. VOA1 is connected to the gate of power device Q1 via resistor Rg1, and the gate of power device Q1 is connected to VOA2 via diode Dg1. The output signal of VOA2 is also sent to the analog switch via diode Dg1 and resistors Rg2 and Rg3. When VOA1 outputs a high level, VOA2 is in a high-impedance state, the analog switch is in the cut-off state, and the power device Q1 is turned on by positive voltage; When VOA2 outputs a low level, VOA1 is in a high-impedance state. Diode Dg1 first pulls down the gate-source voltage of the power device Q1 to 0V, and then the gate voltage of Q1 is pulled down to the first negative voltage through Rg3, the analog switch, and Rg2. The power device Q1 is turned off and then returns to the second negative voltage, where the second negative voltage is the weighted sum of the first negative voltage and the third negative voltage.

5. The multi-level direct drive circuit of the depletion-mode switch device according to claim 4, characterized in that: The analog switch includes an operational amplifier Us1, XOR gates Us2 and Us3 with enable terminals, a delay buffer Us4, transistors Ms1 and Ms2, a diode Ds1, resistors Rs1, Rs3, Rs4, Rs5, and Rs6. One end of the resistor Rg2 is connected between VOA2 and the negative electrode of the diode Dg1, and the other end is respectively connected to one end of the resistor Rs1, one end of the resistor Rs5, and one end of the resistor Rs6. The other end of the resistor Rs1 is connected to the negative input terminal x1 of the operational amplifier Us1. The positive input terminal x2 of Us1 is connected in series with the resistors Rs3 and Rs4 through an additional positive voltage supply to divide the voltage to the reference zero potential of Us1. The output terminal of Us1 is connected to an input terminal of the XOR gate Us2 and an input terminal of the XOR gate Us3. One end of the resistor Rg3 is connected between the positive electrode of the diode Dg1 and the gate of the power device Q1, and the other end is connected to the other input end of the XOR gate Us2 and the other input end of the XOR gate Us3. The enable ends of the XOR gates Us2 and Us3 are both connected to the resistor Rs3 to judge the level signal. The output end of the XOR gate Us2 is connected to the gate of the transistor Ms1 to provide a control signal. The other two stages of the transistor Ms1 are respectively connected to the input first negative voltage and the other end of the resistor Rs5. The output end of the XOR gate Us3 is connected to the gate of the transistor Ms2 through the delay buffer Us4 to provide a control signal. The other two stages of the transistor Ms2 are respectively connected to the input third negative voltage and the positive electrode of the diode Ds1. The negative electrode of the diode Ds1 is connected to the other end of the resistor Rs6.

6. The multi-level direct drive circuit of a depletion-mode switch device according to any one of claims 1 to 5, characterized in that: The power devices Q1, Q2, Q3, and Q5 are all p-type tubes or depletion-mode gallium nitride-based power devices, and the power device Q4 is an n-type tube or enhancement-mode gallium nitride-based power device.

7. The multi-level direct drive circuit of the depletion-mode switch device according to claim 6, characterized in that: It also includes a power insertion circuit, the input end of which is connected to the source of the power device Q4, the output end is connected to the drain of Q1, and is connected to the positive electrode of the capacitor C1. The power insertion circuit is a direct short circuit or a power factor correction circuit.

8. The multi-level direct drive circuit of the depletion-mode switch device according to claim 7, characterized in that: The analog switch further includes a resistor Rs2 , one end of which is connected to the positive input terminal x2 of the operational amplifier Us1 , and the other end of which is connected between the transistor Ms2 and the diode Ds1 .

9. The multi-level direct drive circuit of a depletion-mode switch device according to claim 6, characterized in that: The diode group Da is composed of several diodes connected in series.

10. The multi-level direct drive circuit of the depletion-mode switch device according to claim 6, characterized in that: The negative voltage connected to the source of the power device Q5 comes from the negative voltage output by the low-end device driving unit, and the positive voltage power supply of the positive input terminal x2 of Us1 comes from the second positive voltage output by the low-end device driving unit.

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