Fractional frequency division phase-locked loop based on phase interpolation

Abstract

The invention discloses a fractional frequency division phase-locked loop based on phase interpolation, and the phase-locked loop comprises a main phase-locked loop which comprises a phase frequency detector, a charge pump module, a low-pass filter, a voltage-controlled oscillator, an N frequency divider and a phase interpolator module which are sequentially connected end to end; the main phase-locked loop further comprises an auxiliary digital circuit, the output end of the auxiliary digital circuit is connected with the N frequency divider and the phase interpolator module, and the input end of the auxiliary digital circuit is connected with the phase interpolator module and the phase frequency detector. The charge pump module is used for charging and discharging a current source, comprises two groups of multi-path parallel charge pump units, and is used for adapting to frequency adjustment of different ranges and speeds. According to the invention, a multi-path parallel stepped distributed charge pump design is adopted, the charge pump units can carry out current automatic calibration, accurate matching of the charge pumps under different condition changes is ensured, fractional frequency division is realized through the phase interpolator module, the precision and the resolution are high, and fractional stray can be eliminated.

Description

Technical Field

[0001] The present invention relates to the field of chip technology, and in particular to a fractional frequency phase-locked loop based on phase interpolation. Background Art

[0002] Phase-locked loops (PLLs), as key clock generators, are widely used in wireless communications, data transmission, and SoCs (System on Chips). In wireless communications, a growing number of communication protocol standards are emerging, all trending towards higher speeds, requiring higher PLL resonant frequencies. In data transmission, PLLs are a key technology for clock data recovery (CDR), and high-precision, low-jitter PLLs are crucial for clock data recovery. In SoCs, PLLs are essential building blocks for a variety of applications, such as frequency synthesis for wireless transceivers and system clocks for processors, memory, and I / O interfaces. SoCs are highly customized, requiring PLLs to have a wide dynamic adjustment range to accommodate diverse SoC requirements.

[0003] As people place higher demands on PLL accuracy, speed, and resolution, the demand for high-speed, low-jitter PLLs is increasing. However, basic integer-frequency PLLs can only multiply the frequency of a reference clock signal. The reference clock is typically derived from a crystal oscillator with a frequency in the MHz range. Consequently, the adjustment step size of integer-frequency PLLs is also in the MHz range, making them increasingly difficult to meet in applications requiring high precision and resolution. Summary of the Invention

[0004] In order to solve the problems of insufficient precision and resolution, narrow dynamic adjustment range and poor matching of integer frequency phase-locked loops in the prior art, the present invention proposes a fractional frequency phase-locked loop based on phase interpolation.

[0005] The specific technical solution is as follows: a fractional frequency phase-locked loop based on phase interpolation, comprising: a main phase-locked loop, the main phase-locked loop comprising a phase frequency detector, a charge pump module, a low-pass filter, a voltage-controlled oscillator, an N-divider, and a phase interpolator module connected end to end;

[0006] The main phase-locked loop further includes an auxiliary digital circuit, wherein the output end of the auxiliary digital circuit is connected to the N frequency divider and the phase interpolator module, and the input end of the auxiliary digital circuit is connected to the phase interpolator module and the frequency detector;

[0007] The charge pump module is used to charge and discharge the current source, and includes two groups of multi-channel parallel charge pump units, which are used to adapt to frequency regulation of different ranges and speeds.

[0008] Furthermore, the input end of the phase frequency detector is used to access the reference clock ref_clk and the feedback clock fbk_clk, and the output end of the phase frequency detector is used to output up and dn signals to access the input end of the charge pump unit;

[0009] The output end of the phase interpolator module is used to output the feedback clock fbk_clk to the input end of the frequency detector and the input end of the auxiliary digital circuit;

[0010] The output end of the auxiliary digital circuit is used to output code values. The integer sequence in the output code values is input into the N frequency divider, and the decimal sequence in the output code values is input into the phase interpolator module.

[0011] Furthermore, the characteristic dimensions inside the charge pump unit are distributed in a stepped manner, which is used to control the number of access paths according to the selection signal. The charge pump unit includes CP-int and CP-prop. The charge pump unit CP-int is used to control the frequency adjustment in a wide range and low speed, and the charge pump unit CP-prop is used to control the frequency adjustment in a narrow range and high speed.

[0012] Furthermore, the phase interpolator module includes a D trigger, a delay phase-locked loop and a data selector, and the delay phase-locked loop includes a phase detector, a third charge pump and a delay network.

[0013] Furthermore, the current source controlled by the charge pump unit includes an upper current source and a lower current source, and the up and dn signals connected to the input end of the charge pump unit are respectively connected to the charge pump unit to control the switches of the upper current source and the lower current source.

[0014] Furthermore, the output end of the charge pump unit CP-int is connected to the base Vint of the current source, and the output end of the charge pump unit CP-prop is connected to the drain Vctrl of the current source.

[0015] Furthermore, the charge pump unit CP-int includes a first current bias, a first operational amplifier and a first charge pump connected in sequence;

[0016] The first current bias includes current mirrors M1, M2, M3, and M4. M1 and M2 are used to copy the external input current source I1 to the current source M8 of the first operational amplifier through M3 and M4.

[0017] The first operational amplifier includes current mirrors M5 and M7, a current source M8, an input pair of transistors M9 and M10, active loads M6 and M11, and the gates of the input transistor M9 and the current mirror M4 are connected to the VINT_SENSE output terminal of the first charge pump.

[0018] Furthermore, the charge pump unit CP-prop includes a second current bias, a second charge pump, and a second operational amplifier connected in sequence;

[0019] Second current bias: including current mirrors M14, M15, and M16. Current mirror M14 is used to copy the external input current source I2 to the current source M28 of the second charge pump. Current mirrors M15 and M16 are used to copy the current of M14 to the current source M27 of the second charge pump.

[0020] The second operational amplifier: includes current sources M25 and M26. The current sources M25 and M26 of the second operational amplifier are used to obtain the current copied from the current mirror M14. The current source M26 of the second operational amplifier is the tail current source of the pmos tubes M31 and M32. The current source M25 of the second operational amplifier is the tail current source of the nmos tubes M33 and M34.

[0021] Furthermore, the input end of the D flip-flop is used to receive the data signal and the clock signal generated by frequency division of the clock signal output by the voltage-controlled oscillator, and the output end of the D flip-flop is connected to the input end of the phase detector and the delay network respectively;

[0022] The output end of the delay network is connected to the input end of the phase detector and the data selector respectively.

[0023] Furthermore, the D flip-flop is used to output the fbk_clk1 clock signal to access the delay network and output the fbk_clk2 clock signal to access the phase detector;

[0024] The delay network is used to output the delayed clock signal a

[16] compared with the fbk_clk2 clock signal, and output the delayed clock signals a

[15] ~a[0] connected to the data selector;

[0025] The data selector is used to select a delayed clock signal for output through a selection signal.

[0026] The above technical solution has the following advantages or technical effects:

[0027] 1. The present invention adopts a fractional-frequency phase-locked loop. Compared with a conventional integer-frequency phase-locked loop, the frequency division ratio can be a fraction, supporting up to 16 decimals, with a smaller frequency step length, and can adapt to occasions requiring high precision. The phase-locked loop of the present invention adopts a phase interpolator module to achieve fractional frequency division based on the principle of phase interpolation, with extremely low fractional spurious.

[0028] 2. The present invention adopts a multi-parallel stepped charge pump module design to ensure the matching of the charge pump under different process angles and environmental changes. At the same time, the charge pump unit has an automatic current calibration design, which enables the charge pump to better match the upper and lower current sources.

[0029] 3. The present invention utilizes a charge pump module and a phase interpolator module design to more quickly stabilize the negative feedback loop of a phase-locked loop. The charge pump module utilizes charge pump units CP-int and CP-prop to more quickly adjust the control voltage Vctrl and the control current of the voltage-controlled oscillator, thereby rapidly stabilizing the frequency. Simultaneously, the phase interpolator module can quickly align the reference clock and feedback clock during the convergence phase, thereby achieving lock. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 This is a structural block diagram of a fractional frequency phase-locked loop based on phase interpolation of the present invention;

[0031] Figure 2 is a circuit architecture diagram of the charge pump module of the present invention;

[0032] Figure 3 This is a circuit architecture diagram of the charge pump unit CP-int of the present invention;

[0033] Figure 4 This is a circuit architecture diagram of the charge pump unit CP-prop of the present invention;

[0034] Figure 5 1 is a schematic diagram of the phase interpolator module structure of the present invention;

[0035] Figure 6 is a timing diagram of the phase interpolation process of the phase interpolator module of the present invention;

[0036] Figure 7 It is a timing diagram of the fractional frequency phase-locked loop of the present invention. DETAILED DESCRIPTION

[0037] In order to make the technical solution of the present invention clearer, the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments.

[0038] like Figure 1 As shown, a fractional frequency phase-locked loop based on phase interpolation includes: a main phase-locked loop, which includes a phase frequency detector (PFD), a charge pump module (CP), a low-pass filter (LPF), a voltage-controlled oscillator (VCO), an N divider (N divider), and a phase mixer module (PMIX) connected in sequence; and also includes an auxiliary digital circuit (Frac Gen, Fraction Generator, fractional sequence generator).

[0039] The reference clock ref_clk and feedback clock fbk_clk connected to the main phase-locked loop are connected to the input end of the phase and frequency detector. The up and dn signals output by the phase and frequency detector are connected to the charge pump module, and respectively connected to the switches controlling the upper current source and the lower current source. The phase interpolator module implements fractional frequency division based on phase interpolation, and the output feedback clock fbk_clk is connected to the phase and frequency detector and the auxiliary digital circuit; the integer sequence mint and fractional sequence mfrac of the output code value at the output end of the auxiliary digital circuit are respectively connected to the N divider and the phase interpolator module, and the input end is connected to the phase interpolator module and the phase and frequency detector.

[0040] The phase and frequency detector compares the frequency and phase of the two input clock signals, and outputs an up or dn signal based on the phase difference between ref_clk and fbk_clk. The up and dn signals control the switch of the charge pump module, which charges or discharges the charge stored in the low-pass filter, thereby adjusting the control voltage of the voltage-controlled oscillator. The voltage-controlled oscillator then outputs a clock vco_clk with a frequency corresponding to the control voltage. After vco_clk is divided by N and the phase interpolation module in fractional mode, it generates the feedback clock fbk_clk, which is compared with the reference clock ref_clk in frequency and phase again, forming a negative feedback loop, gradually adjusting the frequency and phase of the fbk_clk clock until it is the same as the ref_clk clock.

[0041] This embodiment proposes a fractional-frequency phase-locked loop based on phase interpolation, in which each reference clock can contain a non-integer number of VCO clocks. PMIX generates a series of phase feedback clocks to ensure that for each reference clock, one of the phase feedback clocks is aligned with the reference clock. The clock of this phase is then selected through code, thereby ensuring that the number of VCO clocks contained in each reference / feedback clock is exactly the sum of the integer division ratio and the fractional division ratio. This not only achieves fractional division, but also, because there is no frequency switching, theoretically no fractional spurs. Compared with traditional fractional-frequency phase-locked loops based on Σ-ΔM (Sigma-Delta Modulator, Σ-Δ modulator), the PMIX has a more stable VCO frequency output and lower fractional spurs.

[0042] The charge pump module is used to charge and discharge the current source, such as Figure 2As shown, the device includes two sets of multi-channel parallel charge pump units, CP-int and CP-prop, and a pmos current source. The characteristic dimensions within the charge pump units are distributed in a stepped manner, and the number of connected channels can be selected according to the required operating conditions to improve matching. The CP-int is used to charge and discharge the base of the pmos current source. There are five CP-int groups, and their outputs are connected to the base of the pmos current source, Vint. The CP-prop is used to charge and discharge the drain of the pmos current source. There are six CP-prop groups, and their outputs are connected to the drain of the pmos current source, Vctrl. The two charge pump units are used to accommodate frequency regulation of different ranges and speeds. The number of connected circuits is controlled by their selection signal Sel. The pmos current source powers the voltage-controlled oscillator, and the supply current determines the output frequency of the voltage-controlled oscillator. Therefore, the CP-int is used for wide-range low-speed frequency regulation, while the CP-prop is used for narrow-range high-speed frequency regulation. The CP-int and CP-prop include an automatic current calibration design to improve the matching of the charge pump module.

[0043] like Figure 3 As shown, CP-int includes a first current bias, a first operational amplifier, and a first charge pump. In the first current bias, M1 and M2 act as current mirrors to copy the external input current source I1 to the tail current source M8 of the first operational amplifier through current mirrors M3 and M4. The gate input of the current mirror M4 and the gate of the first operational amplifier input tube M9 are connected to the VINT_SENSE output terminal of the first charge pump, which can improve the current matching. The gate of M10 is connected to the VINT output terminal of the first charge pump. The input tube M9 at the VINT_SENSE end of the first operational amplifier converts the change of the VINT_SENSE voltage into a change of current, and then copies it to the upper current source M13 of the first charge pump through the active load M6 and the current mirrors M5 and M7. Similarly, the input tube M10 at the VINT end converts the change of the VINT voltage into a change of current, and then copies it to the lower current source M12 of the first charge pump through the active load M11. The UP and DN signals output by the phase frequency detector and their inverted signals UPB and DNB are transmitted through the transmission gate (Transmission Gate). Gate (TG) TG1, TG2, TG3 and TG4 control the upper and lower current sources M12 and M13 to charge and discharge the output VINT and VINT_SENSE of the first charge pump.

[0044] The specific principle of CP-int is as follows: when the switches at the upper and lower ends of the control voltage VINT are both closed, the upper and lower current sources of the first charge pump are connected through the VINT_SENSE end. If the upper and lower current sources of the first charge pump are mismatched, the first charge pump will charge and discharge VINT_SENSE. If the current of the upper current source is greater than that of the lower current source, the first charge pump will charge VINT_SENSE, increasing the VINT_SENSE voltage. This will reduce the current of the PMOS transistor at the VINT_SENSE input of the op amp. The current mirror then reduces the upper power supply of the first charge pump until it equals the current of the lower current source, thus fixing the VINT_SENSE voltage. The matching of the upper and lower current sources of the first charge pump effectively reduces the change in VINT voltage caused by the phase frequency detector when the upper and lower switches of VINT are simultaneously turned on.

[0045] like Figure 4 As shown, CP-prop includes a second current bias, a second charge pump, and a second operational amplifier. In the second current bias, current mirror M14 copies the external input current source I2 to M28, serving as the current source for the second charge pump DN. Current mirrors M15 and M16 copy M14's current to M27, serving as the current source for the second charge pump UPB. M14's current is copied to the tail current sources M25 and M26 of the second operational amplifier via current mirrors M17, M18, M19, M20, M21, M22, M23, and M24. The gate inputs of current mirrors M21 and M22, along with the gates of the second operational amplifier input transistors M32 and M34, are connected to the VCTRL output of the second charge pump, improving current matching. The second operational amplifier is rail-to-rail and includes two groups of input pairs of tubes, M31 and M34 as one group, and M32 and M33 as another group. The pmos tubes M31 and M32 use M26 as the tail current source, and the nmos tubes M33 and M34 use M25 as the tail current source.

[0046] M31 and M34 convert the voltage change at the VINT_SENSE terminal into a current change via a diode-connected NMOS transistor M35. This current change is then fed back to the current source M30 at the UP terminal of the second charge pump via M36 and M37. M32 and M33 convert the voltage change at the VCTRL_SENSE terminal into a current change via a diode-connected PMOS transistor M38. This current change is then fed back to the current source M29 at the UP terminal of the second charge pump via M39 and M40. This process automatically calibrates the current of the second charge pump.

[0047] M41, M42, M43, and M44 are MOS switches controlled by UP and DN and their inverted signals UPB and DNB.

[0048] The specific principle of CP-prop is: when CP-prop is not working, that is, up and dn are both low, M43 and M44 are turned on, M41 and M42 are turned off, and the current of the second charge pump is discharged to M28 and M29 through M27 and M30. If the current of M27 and M30 does not match that of M28 and M29, the second charge pump will charge and discharge VCTRL_SENSE. If the current of M27 and M30 is greater than that of M28 and M29, the second charge pump will charge and discharge VCTRL_SENSE. E is charged, the VCTRL_SENSE voltage increases, and the increase in VCTRL_SENSE voltage is converted into a decrease in M31 current through M31, and then the M30 current is reduced through amplification and replication of M35, M36, and M37; the increase in VCTRL_SENSE voltage is converted into an increase in M33 current through M33, and then the M29 current is increased through amplification and replication of M38, M39, and M40, until the currents of M27 and M30 are equal to those of M28 and M29.

[0049] like Figure 5 As shown, the phase interpolator module includes a D flip-flop, a delay locked loop (DLL) and a data selector (MUX). The delay locked loop includes a phase detector (PD), a third charge pump and a delay network (Delay Cell Series). The output clock of the voltage-controlled oscillator is divided by N and divided by 2, and then used as the data signal input fbk_clk_int and clock signal input vco_clk_div2 of the D flip-flop respectively. The D flip-flop outputs two clock signals fbk_clk1 and fbk_clk2. The input of fbk_clk1 is connected to the delay network, and the input of fbk_clk2 is connected to the third charge pump. The output of the delay network is a[0]~a

[16] . The output a

[16] of the delay network is connected to the phase detector, and a

[16] is compared with fbk_clk2 to form a negative feedback loop. The outputs up and dn of the phase detector are connected to the third charge pump, and the outputs nbias and pbias of the third charge pump are connected to the delay network. The outputs a

[15] ~a[0] of the delay network are connected to the data selector. The selection signal sel selects one of a

[15] ~a[0] as the output fbk_clk of the data selector, that is, the output of the phase interpolator module.

[0050] like Figure 6As shown, the specific principle of PMIX is: the output clock of the voltage-controlled oscillator is divided by an integer multiple of the N divider, and the output clock fbk_clk_int is input to the D flip-flop as a data signal. The output clock vco_clk of the voltage-controlled oscillator is divided by 2, and the clock vco_clk_div2 is input to the D flip-flop as a clock signal. The double-edge triggering is performed. At this time, there is a phase difference of 90° between the output clocks fbk_clk1 and fbk_clk2 of the D flip-flop (with vco_clk_div2 as the reference, fbk_clk2 lags behind). After fbk_clk1 passes through the delay network Delay cell series, a series of delay clocks a[0]~a

[16] are generated. In the initial stage of feedback establishment, the control voltage pbias of the delay cell is close to the ground, and nbias is close to the power supply voltage. The delay of the delay cell is very small. The clock a

[16] at the end of the cell is fed back to the phase detector and phase-detected with fbk_clk2. The charge pump module then controls nbias and pbias, causing the nbias voltage to decrease and the pbias voltage to increase, increasing the delay of the delay cell. a

[16] gradually aligns with fbk_clk2 until a

[16] and fbk_clk2 are in phase. The phases of a[0] to a

[16] are evenly divided into the phase difference between fbk_clk1 and fbk_clk2. Based on the above structure, within the specified frequency range, regardless of the frequency of the VCO output clock, the delay phase-locked loop can provide a phase deviation as high as 270° and as low as 5.625°.

[0051] The common fractional-frequency phase-locked loop is implemented based on the Σ-Δ modulator. Its principle is to control the frequency of the voltage-controlled oscillator (VCO) by controlling the proportion of different integer division ratios in the cycle, thereby achieving fractional division in an average sense. In this case, the division ratio needs to be switched frequently, so the frequency of the VCO changes frequently. Therefore, the feedback clock is ahead of or behind the reference clock when the VCO frequency changes. It must be charged and discharged using a charge pump before it stabilizes again, which causes fractional spurs. The fractional spurs introduced by the Σ-Δ modulator method are reduced by increasing the order of the Σ-Δ modulator, but its fractional spurs cannot be eliminated in principle.

[0052] The fundamental principle that distinguishes this embodiment from the prior art is that it eliminates the need for each reference / feedback clock in a conventional frequency divider to contain VCO clocks with an integer division ratio, as this is the source of fractional spurs. Instead, each reference clock contains VCO clocks with the required integer division ratio plus the required fractional division ratio. Conventional frequency dividers cannot achieve this by including a number of VCO clocks equal to an integer division ratio plus a fractional division ratio. Therefore, this embodiment employs a phase interpolation method to generate a series of feedback clocks, ensuring that each reference clock has one phase of feedback clock aligned with the reference clock. This phase is then selected using a code, ensuring that each reference clock contains a number of VCO clocks equal to the integer division ratio plus the fractional division ratio. This not only achieves fractional division, but also, because there is no frequency switching, theoretically eliminates fractional spurs.

[0053] like Figure 7 As shown in the figure, it is an example of a timing diagram for a fractional-number phase-locked loop based on phase interpolation to achieve a division ratio of 6.5. For the reference clock ref_clk, to achieve a division ratio of 6.5, two integer division ratios of 6 and 8 are required. The reason for not using the two division ratios of 6 and 7 is that odd division ratios are more difficult to achieve than even division ratios, and more circuit modules will be used. Figure 7 In the figure, fbclk0~fbkclk270 are clocks with phases of 0°, 90°, 180° and 270° respectively delayed by the phase interpolator module. The black part indicates the sub-frequency division by 6, and the purple part indicates the sub-frequency division by 8. After every 3 times of 6 division, the frequency is divided by 8, so the following is obtained: Figure 7 As shown in the results, fbclk0 is selected as the feedback clock fbk_clk in the first clock cycle, fbclk90 is selected as fbk_clk in the second clock cycle, fbclk180 is selected as fbk_clk in the third clock cycle, and fbclk270 is selected as fbk_clk in the fourth clock cycle. In this way, the rising edges of fbk_clk and ref_clk are completely aligned. Because fbclk0~fbkclk270 are all divided by 6 and occupy 3 / 4 of the cycle, and divided by 8 and occupy 1 / 4 of the cycle, the average division ratio of fbclk0~fbkclk270 is:

[0054]

[0055] Under the phase interpolation rule, it is easy to observe that there are 6.5 VCO clocks in each reference clock, which is a strict 6.5 frequency division, and the VCO clock is strictly stable without frequency changes.

[0056] The above-described embodiments merely illustrate several implementations of the present invention, and while their descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the present invention. It should be noted that a person skilled in the art would be able to make numerous variations and improvements without departing from the spirit of the present invention, all of which fall within the scope of protection of the present invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims.

Claims

1. A fractional frequency phase-locked loop based on phase interpolation, characterized in that: include: A main phase-locked loop, comprising a phase frequency detector, a charge pump module, a low-pass filter, a voltage-controlled oscillator, an N-frequency divider, and a phase interpolator module connected end to end; The main phase-locked loop further includes an auxiliary digital circuit, wherein the output end of the auxiliary digital circuit is connected to the N frequency divider and the phase interpolator module, and the input end of the auxiliary digital circuit is connected to the phase interpolator module and the frequency detector; The charge pump module is used to charge and discharge the current source, and includes two groups of multi-channel parallel charge pump units, which are used to adapt to frequency regulation of different ranges and speeds.

2. The fractional frequency phase-locked loop based on phase interpolation according to claim 1, characterized in that: The input end of the phase frequency detector is used to access the reference clock ref_clk and the feedback clock fbk_clk, and the output end of the phase frequency detector is used to output up and dn signals to access the input end of the charge pump unit; The output end of the phase interpolator module is used to output the feedback clock fbk_clk to the input end of the frequency and phase detector and the input end of the auxiliary digital circuit; The output end of the auxiliary digital circuit is used to output code values. The integer sequence in the output code values is input into the N frequency divider, and the decimal sequence in the output code values is input into the phase interpolator module.

3. The fractional frequency phase-locked loop based on phase interpolation according to claim 1, characterized in that: The characteristic dimensions inside the charge pump unit are distributed in a stepped manner, and are used to control the number of access paths according to a selection signal. The charge pump unit includes CP-int and CP-prop. The charge pump unit CP-int is used to control wide-range low-speed frequency regulation, and the charge pump unit CP-prop is used to control narrow-range high-speed frequency regulation.

4. The fractional frequency phase-locked loop based on phase interpolation according to claim 2, characterized in that: The phase interpolator module includes a D trigger, a delay phase-locked loop and a data selector. The delay phase-locked loop includes a phase detector, a third charge pump and a delay network.

5. The fractional frequency phase-locked loop based on phase interpolation according to claim 3, characterized in that: The current source controlled by the charge pump unit includes an upper current source and a lower current source. The up and dn signals connected to the input end of the charge pump unit are respectively connected to the charge pump unit to control the switches of the upper current source and the lower current source.

6. The fractional frequency phase-locked loop based on phase interpolation according to claim 5, characterized in that: The output end of the charge pump unit CP-int is connected to the base Vint of the current source, and the output end of the charge pump unit CP-prop is connected to the drain Vctrl of the current source.

7. The fractional frequency phase-locked loop based on phase interpolation according to claim 6, characterized in that: The charge pump unit CP-int includes a first current bias, a first operational amplifier and a first charge pump connected in sequence; The first current bias includes current mirrors M1, M2, M3, and M4. M1 and M2 are used to copy the external input current source I1 to the current source M8 of the first operational amplifier through M3 and M4. The first operational amplifier includes current mirrors M5 and M7, a current source M8, an input pair of transistors M9 and M10, active loads M6 and M11, and the gates of the input transistor M9 and the current mirror M4 are connected to the VINT_SENSE output terminal of the first charge pump.

8. The fractional frequency phase-locked loop based on phase interpolation according to claim 6, characterized in that: The charge pump unit CP-prop includes a second current bias, a second charge pump and a second operational amplifier connected in sequence; Second current bias: including current mirrors M14, M15, and M16. Current mirror M14 is used to copy the external input current source I2 to the current source M28 of the second charge pump. Current mirrors M15 and M16 are used to copy the current of M14 to the current source M27 of the second charge pump. The second operational amplifier: includes current sources M25 and M26. The current sources M25 and M26 of the second operational amplifier are used to obtain the current copied from the current mirror M14. The current source M26 of the second operational amplifier is the tail current source of the pmos tubes M31 and M32. The current source M25 of the second operational amplifier is the tail current source of the nmos tubes M33 and M34.

9. The fractional frequency phase-locked loop based on phase interpolation according to claim 4, characterized in that: The input end of the D flip-flop is used to receive the data signal and the clock signal generated by the frequency division of the clock signal output by the voltage-controlled oscillator, and the output end of the D flip-flop is connected to the input end of the phase detector and the delay network respectively; The output end of the delay network is connected to the input end of the phase detector and the data selector respectively.

10. The fractional frequency phase-locked loop based on phase interpolation according to claim 9, characterized in that: The D flip-flop is used to output the fbk_clk1 clock signal to access the delay network and output the fbk_clk2 clock signal to access the phase detector; The delay network is used to output the delayed clock signal a[16] compared with the fbk_clk2 clock signal, and output the delayed clock signals a[15]~a[0] connected to the data selector; The data selector is used to select a delayed clock signal for output through a selection signal.

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