Capacitor mismatch correction method applied to high-precision successive comparison analog-to-digital converter
By combining split ADC structure and the LMS iterative algorithm of reverse perturbation injection, the problem of high-precision SAR ADC capacitor mismatch is solved, faster calibration speed and larger calibration range are achieved, and the accuracy and real-time performance of the analog-to-digital converter are improved.
Patent Information
- Application Number
- CN202510549790.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-04-28
- Publication Date
- 2025-08-12
AI Technical Summary
Capacitance mismatch problems in existing high-precision successive comparison analog-to-digital converters (SAR ADCs) lead to limited calibration range and slow convergence speed, making it difficult to meet real-time and accuracy requirements.
Using split (Split) ADC structure and reverse perturbation injection combined with minimum mean square (LMS) iterative algorithm, through complementary capacitor arrays and redundant capacitor design, dual-channel differential calculations and disturbance signals are used to correct in the analog domain, and the capacitance weight is dynamically adjusted.
It significantly broadens the calibration range, improves calibration efficiency and convergence speed, and does not need to interrupt the normal conversion process of the ADC, achieving high accuracy and real-time correction.
Smart Images
Figure CN120474548A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of analog-to-digital converters (ADCs), and in particular to a background digital correction method and system for a high-precision successive approximation analog-to-digital converter (SAR ADC). The method calibrates capacitance mismatch errors through a dual-channel structure combined with reverse disturbance injection and an LMS iterative algorithm. Background Art
[0002] In recent years, integrated circuit technology has been developing rapidly, and analog signal processing technology and digital signal processing technology have gradually matured. The demand for high-precision ADCs in the Internet of Things, medical electronics, and other fields has surged. The successive approximation analog-to-digital converter (SAR ADC) has gradually achieved high-speed and high-precision design with the support of nanometer-level CMOS technology due to its advantages of high precision, low power consumption, and small area. Its core digital-to-analog converter (DAC) adopts a charge redistribution capacitor array structure, in which each capacitor value is configured according to binary weighting (C i =2 i C u , i=0,1,…,N-1,N is the resolution, C u is the unit capacitance). However, as resolution increases, the total capacitance increases exponentially, leading to a surge in power consumption. To address this, capacitor array segmentation technology has been widely adopted, significantly reducing the total capacitance by optimizing the capacitor layout. However, unit capacitance mismatch caused by process variations still severely limits accuracy improvements and requires compensation through correction techniques.
[0003] Existing correction schemes fall into two main categories: foreground correction in the analog domain and background correction in the digital domain. Foreground correction requires an additional correction DAC to measure the mismatch of all capacitors before the ADC performs normal quantization. Correction coefficients are extracted using a specific algorithm and stored as error codes. During operation, the correction DAC superimposes the error voltage on the main DAC output, or directly compensates the error code at the digital output. This method requires interrupting the normal conversion process and relies on additional analog circuitry, making it difficult to meet real-time requirements. Background correction, on the other hand, uses an algorithm to track changes in capacitor parameters in real time. Error correction is performed directly in the digital backend without modifying analog circuitry or adding hardware modules. This technique can dynamically adapt to process drift and temperature variations, but requires iterative calibration of all capacitor units, increasing system complexity and becoming a current research hotspot and challenge. Currently, foreground correction offers controllable accuracy but lacks flexibility, while background correction offers high adaptability but faces algorithm optimization challenges. Balancing accuracy, power consumption, and real-time performance is a key research direction in the field of capacitor mismatch correction.
[0004] At present, many capacitor array structures and corresponding algorithms have been proposed for the digital background correction algorithm of capacitor mismatch. At present, the more widely used ones are split ADC algorithm, LMS adaptive algorithm and dynamic element matching (DEM) and the like. For the split ADC algorithm, although the principle is simple and the gain error between segments can be dynamically compensated, an additional calibration ADC auxiliary calibration is required, the hardware overhead is large and the calibration range is limited, and the correction effect is poor when the unit capacitance standard deviation is small. For adopting dynamic element matching (DEM) in combination with LMS algorithm, redundant capacitance and disturbance signal are not introduced, and the calibration efficiency is low. Therefore, the present invention proposes a novel digital background correction algorithm in combination with split ADC and injection disturbance algorithm, which widens the calibration range and improves the correction efficiency. Summary of the Invention
[0005] The present invention aims at the DAC capacitor array mismatch problem in a high-precision successive approximation analog-to-digital converter (SAR ADC) and proposes a background correction algorithm combining a split ADC structure and injected reverse dither.
[0006] In order to solve the problems existing in the prior art, the present invention provides a method for correcting capacitance mismatch in a high-precision successive approximation analog-to-digital converter, the method comprising:
[0007] Step 1: For the DAC segmented capacitor array in the SAR ADC, a p-end and n-end complementary capacitor array is used: the p-end capacitor array and the n-end capacitor array are composed of binary unit capacitors, C n =2 m C u , n, m are positive integers, C u is the unit capacitance;
[0008] Step 2: Sampling and quantization are performed using a split SAR ADC. The split ADC uses two identical SAR ADCs constructed with the aforementioned DAC capacitor array. The sampling and quantization process is identical to that of a traditional SAR ADC. The algorithm of the present invention can perform background correction, tracking the ADC operating status and correcting the output in real time without interrupting normal ADC operation.
[0009] Step 3: Calculate the difference between the outputs of the two ADCs to obtain diff. Use a switch to inject the disturbance signal into the two ADCs from opposite directions in the analog domain. That is, the disturbance signal voltage value is added to the input of one ADC and subtracted from the input of the other ADC.
[0010] Step 4: Perform LMS iteration on the output after the disturbance is injected to obtain the weight value w of each capacitor. n , n is a positive integer;
[0011] Step 5: Multiply each capacitance weight obtained by LMS iteration by the corresponding codeword and sum them to obtain the new output values of the two ADCs.
[0012] Step 6: Repeat steps 3 through 5 until the difference between the two ADC outputs is zero. The two channels are each subjected to opposite dithering in the analog domain and must be compensated accordingly in the digital domain. Therefore, the reverse dithering signal injected in step 3 will not affect the output. The weight value obtained from the last LMS iteration at this point is the final capacitor weight value, and the generated codeword is the corrected ADC output.
[0013] In step 1, all capacitors are sorted from small to large and numbered 1, 2, ... n. The sorted capacitors are divided into two groups, each with n / 2 capacitors. The group containing the lower capacitors is the LSB, and the group containing the higher capacitors is the MSB. A bridge capacitor C is added between the LSB and MSB. sp and C sn , whose size is a unit capacitor, so the segmented capacitor array is divided into P-end MSB / LSB and N-end MSB / LSB, and grounded quantized capacitors C are added to the four-segment capacitor array respectively. msbp 、C lsbp 、C msbn and C lsbn , add two binary redundant capacitors C to the above MSB capacitor array d , whose capacitance size is the same as the previous capacitance at the insertion position, so as to improve the error tolerance in the subsequent quantization process.
[0014] 3. The capacitance mismatch correction method for a high-precision successive approximation analog-to-digital converter according to claim 1, characterized in that:
[0015] The specific steps of LMS iteration in step 4 are:
[0016] Calculate the difference between the outputs of A and B.
[0017] differAB=DoutA-DoutB
[0018] Among them, DoutA and DoutB are the outputs of the two ADC channels in the analog domain, differAB is the difference between the two channels, and the error signal e is calculated. n 、e dither
[0019] e(n)=[b A (n)-b B (n)]*diffAB
[0020] edither =2*diffAB
[0021] Among them, b A and b B are the digital code words output by the two ADCs, e dither is the perturbed error signal, and then the weight w is calculated n , and its iterative formula is
[0022] w(n+1)=w(n)-μ w *e(n)
[0023] w dither_new =w dither -μ w *e dither
[0024] Among them, μ w is the iteration step, which is a constant, w dither is the weight of the disturbance signal, w dither_new To perturb the new round of weights obtained through iteration, finally, update the weights and calculate the new round of weights w corresponding to each capacitor n_new ,Since the sum of the weights of each capacitor position remains unchanged, there is
[0025] w n_new =w n +μ w *(e1+...+e n-1 )
[0026] Among them, e1~e n-1 is the error signal mentioned above.
[0027] According to the above steps, a set of capacitance weights w can be obtained after each LMS iteration. n_new. .
[0028] The proposed background correction algorithm, combining SplitSAR ADC and perturbation injection, adds perturbations in the analog domain compared to traditional SplitSAR ADCs, resulting in a larger difference between the two output values and faster iteration speeds. Furthermore, perturbation injection effectively compensates for the limited calibration range of SplitSAR ADC calibration alone.
[0029] When traditional Split ADC is designed, two identical channels will output D iA and D iB Due to manufacturing process errors, the two output values cannot be exactly the same and there will always be differences. By calculating the weight of the output code word and the corresponding capacitance, we can get X A and X B ,Right now:
[0030]
[0031] Where W i is the capacitance weight, D i is the output codeword, ξ i is the offset correction term. By differential calculation, we can get:
[0032]
[0033] After multiple conversions, multiple sets of digital outputs can be obtained, and finally a linear equation system can be obtained:
[0034] △X=D×ξ
[0035] Among them, △X, D, ξ are all matrices. Theoretically, as long as there are enough unknowns to make the matrix full rank, all ξ can be solved. iA and ξ iB The LMS (least mean square algorithm) is used to iteratively find an approximate solution to the equation, because in actual situations, matrix solving is difficult and it is easy to have no solution.
[0036] The LMS iteration of the traditional Split ADC is driven by the difference between the two channels diff. After the error signal e(k) is obtained, the formula is used
[0037] w(n+1)=w(n)+μe(k)x(k)
[0038] The weights are iteratively updated to minimize the mean square value of the error signal. Here, w is the weight vector, μ is the step size, e(k) is the error signal at time k, and x(k) is the input signal vector at time k. However, while the two channels of a split ADC are designed to be identical, the differences caused by random mismatches during manufacturing may not be large enough, further resulting in slow iterative convergence. Effective correction requires a large unit capacitance standard deviation. Therefore, the calibration range of traditional split ADCs is very limited, making effective correction difficult when the capacitance standard deviation is small.
[0039] According to the present invention, the difference between the two channels can be increased after injecting the reverse perturbation, and even if the above-mentioned capacitance standard deviation is small, effective correction can be performed. At the same time, the introduction of additional perturbations can help the algorithm jump out of the local minimum faster, thereby better exploring the local space and accelerating the LMS iteration speed. Figure 12-13 As shown, the algorithm of the present invention ( Figure 12 ) converges at 15K sampling points, while the traditional Split ADC correction ( Figure 13 ) converges at 20K sampling points, and the iteration speed is significantly faster than the traditional algorithm. Figure 14-15 As shown, when the capacitance standard deviation is small, the algorithm of the present invention ( Figure 15) The corrected effective number of bits is 15.81 bits, which is higher than the traditional algorithm ( Figure 14 ) is 14.01 bits after correction, indicating that the algorithm described in the present invention can also perform effective correction under harsh conditions. BRIEF DESCRIPTION OF THE DRAWINGS
[0040] Figure 1 Schematic diagram of the DAC segmented capacitor array structure.
[0041] Figure 2 Schematic diagram of the DAC segmented capacitor array of the 16-bit SAR ADC in the implementation case.
[0042] Figure 3 This is a schematic diagram of the split dual-channel SAR ADC structure.
[0043] Figure 4 Schematic diagram of the internal structure of SAR ADC.
[0044] Figure 5 This is a schematic diagram of the overall process of the background algorithm proposed in this invention.
[0045] Figure 6 This is a schematic diagram of the process of solving the output codeword in the implementation case.
[0046] Figure 7 This is a schematic diagram of the LMS iterative process in the algorithm proposed in this invention.
[0047] Figure 8 Added forward signal diagram to implementation example.
[0048] Figure 9 Added reverse signal diagram to implementation example.
[0049] Figure 10 This is the uncorrected FFT simulation result of the 16-bit SAR ADC in the implementation case.
[0050] Figure 11 This is the FFT simulation result of the 16-bit SAR ADC in the implementation case after correction by the algorithm proposed in the present invention.
[0051] Figure 12 This is a schematic diagram showing how the effective number of bits changes with the number of algorithm iterations when the algorithm of the present invention is used in a 16-bit SAR ADC in an implementation case.
[0052] Figure 13 This is a diagram showing how the effective number of bits changes with the number of algorithm iterations when the 16-bit SAR ADC in the implementation case uses only the simple Split ADC correction technology.
[0053] Figure 14This is the FTT simulation result when the 16-bit SAR ADC in the implementation case uses the simple Split ADC correction technology with a small capacitance standard deviation.
[0054] Figure 15 This is the FTT simulation result of the 16-bit SAR ADC in the implementation case when the algorithm of the present invention is used with a small capacitance standard deviation. DETAILED DESCRIPTION
[0055] The following provides a specific implementation example of the present invention, with reference to the accompanying drawings. It should be noted that the parameters in this implementation example do not affect the generality of the present invention. This implementation example uses a 16-bit SAR ADC as an example, utilizing the algorithm proposed in this invention and MATLAB / Simulink for simulation and comparison.
[0056] The DAC capacitor array that constitutes the SAR ADC is as follows: Figure 2 As shown, the array is divided into p-end and n-end. The figure shows the initial state, the voltage on the capacitor is 0 by default, and the switch is connected to GND. sp and C sn C is the bridge capacitor, and its size is Cu (Cu is the unit capacitance). 7d and C 10d are redundant capacitors, each with a size of 0.5C u and 4C u . C msbp / C msbn and C lsbp / C lsbn To quantize the capacitance.
[0057] In traditional SAR ADCs, the capacitance weights for each bit are binary. Factors like noise can cause comparator errors, leading to incorrect capacitor settings. The resulting voltage deviations accumulate in subsequent quantization steps, causing deviations in the successive approximation process and a rapid decrease in quantization accuracy. By adding binary redundant capacitors, the higher-order capacitance is reduced to less than the sum of the lower-order capacitances, ensuring digital domain calibration. This also increases the SAR ADC's conversion error tolerance, allowing for correction of erroneous judgments during subsequent calibration.
[0058] After using the above DAC to form a SAR ADC, two identical SAR ADCs are used to form a split ADC structure, such as Figure 3 Here, “identical to each other” means that the internal structure of SAR ADC is identical, such as Figure 4 As shown, due to the inevitable capacitance size error of the DAC capacitor array in actual industrial manufacturing, it can only be guaranteed that the structures of the two DAC capacitor arrays are exactly the same and the sizes of the component capacitors are approximately close.
[0059] The SAR ADC structure proposed by the present invention is successfully constructed through the above process. The application of the background correction algorithm on this structure is described below. The overall background correction algorithm process is as follows: Figure 5 The principle diagram of “analog value conversion to code word” is shown as follows. Figure 6 As shown. Figure 5 , add dither of the same size to Dout_A and Dout_B in two directions, that is, add dither to one output and subtract dither from one output. The outputs of the two ADCs are calculated differentially to obtain diff, and LMS iteration is performed to obtain a new set of capacitance weights. Continue iterating the calculation according to the new weights until the difference between the outputs of the two channels is 0, that is, the outputs of the two channels are the same. Introducing additional disturbances by adding dither signals can help the algorithm jump out of the local minimum faster, thereby better exploring the local space and accelerating the convergence of the algorithm. Here, each time we perform an LMS iteration, a set of capacitance weight values will be calculated. If the iteration is completed, the final weight value is the true weight of each capacitor, and this weight can be used to calculate the corrected output of the SAR ADC.
[0060] In the simulation analysis of this implementation case, the DAC capacitance mismatch is set to conform to the Gaussian distribution, and the sampling period is set to 1.9×10 -8 s, the FFT points are 1024, the input signal is a sine wave with an amplitude of 1V, a frequency of 2.6264MHz, and an initial phase and offset of 0. The simulation results are as follows Figure 10-12 As shown, Figure 10 is the result without correction. Figure 11 Figure 1 shows the results after correction. It can be seen that after correction, the effective number of bits (ENOB) increases from 9.09 bits to 15.75 bits, the spurious-free dynamic range (SFDR) reaches 112.16dB, and the signal-to-noise and distortion ratio (SNDR) reaches 96.60dB. Figure 12 The effective number of bits (ENOB) changes with the number of iterations. It can be seen that the ENOB is only 9.09 bits before correction, and it continues to improve with the iterations, eventually reaching 15.7 bits.
[0061] Generally, a 16-bit pure column-wise SAR ADC converges at approximately 20k sampling points, such as Figure 13 The figure shows the change of ENOB with the number of iterations when using the simple Split ADC technology for correction. It can be seen that the algorithm converges at about 20k times. Figure 12It can be seen that the algorithm converges at about 15k sampling points under the calibration of this algorithm. Therefore, the algorithm proposed in this invention converges faster than the simple use of the Split SAR ADC background LMS correction algorithm with the same accuracy. At the same time, the calibration effect of the simple Split ADC technology is poor when the difference between the two channels is small, and the injection perturbation technology can well compensate for this defect. Here we reduce the standard deviation of the capacitor mismatch, and the simulation results after correction using the simple Split technology are as follows Figure 14 As shown, after adding dither and simulating again, the results are as follows Figure 15 As shown in the figure, it can be seen that compared with the simple Split technology, the effective number of bits after correction by injecting dither combined with the Split technology is higher, and the correction effect is better when the standard deviation of the capacitor mismatch is small.
[0062] Therefore, compared with the general Split correction algorithm, the algorithm proposed in the present invention has a faster convergence speed and a larger calibrable error range.
[0063] It should be noted that the above embodiments are not intended to limit the scope of protection of the present invention, and equivalent changes or substitutions made on the basis of the above technical solutions fall within the scope of protection of the claims of the present invention.
Claims
1. A capacitance mismatch correction method for a high-precision successive approximation analog-to-digital converter, characterized in that: The method comprises the following steps, Step 1: For the DAC segmented capacitor array in the SAR ADC, a p-end and n-end complementary capacitor array is used: the p-end capacitor array and the n-end capacitor array are composed of binary unit capacitors, C n =2 m C u , n, m are positive integers, C u is the unit capacitance; Step 2: Sampling and quantization are performed using a split SAR ADC. The split ADC uses two identical SAR ADCs constructed with the aforementioned DAC capacitor array. The sampling and quantization process is identical to that of a traditional SAR ADC. The algorithm of the present invention can perform background correction, tracking the ADC operating status and correcting the output in real time without interrupting normal ADC operation. Step 3: Calculate the difference between the outputs of the two ADCs to obtain diff. In the analog domain, inject the disturbance signal into the two ADCs from opposite directions. That is, the disturbance signal voltage value is added to the input of one ADC and subtracted from the input of the other ADC. The disturbance is injected using the charge redistribution principle of capacitors and a switching strategy. Step 4: Perform Least Mean Square Iteration (LMS) on the output after the disturbance is injected to obtain the weight value w of each capacitor n , n is a positive integer; Step 5: Multiply each capacitance weight obtained by LMS iteration by the corresponding codeword and sum them to obtain the new output values of the two ADCs. Step 6: Repeat steps 3 to 5 until the output difference of the two ADCs is 0. The two channels add opposite disturbances in the analog domain and compensate accordingly in the digital domain. The injection of the reverse dither signal in step 3 will not affect the output. At this time, the weight value obtained by the last LMS iteration is the actual weight value of the final capacitor, and the generated codeword is the output of the ADC after correction.
2. The capacitance mismatch correction method for a high-precision successive approximation analog-to-digital converter according to claim 1, wherein: In step 1, all capacitors are sorted from small to large and numbered 1, 2, ... n. The sorted capacitors are divided into two groups, each with n / 2 capacitors. The group containing the lower capacitors is the LSB, and the group containing the higher capacitors is the MSB. A bridge capacitor C is added between the LSB and MSB. sp and C sn , whose size is a unit capacitor, so the segmented capacitor array is divided into P-end MSB / LSB and N-end MSB / LSB, and grounded quantized capacitors C are added to the four-segment capacitor array respectively. msbp 、C lsbp 、C msbn and C lsbn , add two binary redundant capacitors C to the above MSB capacitor array d , whose capacitance size is the same as the previous capacitance at the insertion position, so as to improve the error tolerance in the subsequent quantization process.
3. The capacitance mismatch correction method for a high-precision successive approximation analog-to-digital converter according to claim 1, wherein: The specific steps of LMS iteration in step 4 are: Calculate the difference between the outputs of A and B. differAB=DoutA-DoutB Among them, DoutA and DoutB are the outputs of the two ADC channels in the analog domain, differAB is the difference between the two channels, and the error signal e is calculated. n 、e dither e(n)=[b A (n)-b B (n)]*diffAB And dither =2*diffAB Among them, b A and b B are the digital code words output by the two ADCs, e dither is the perturbed error signal, and then the weight w is calculated n , and its iterative formula is w(n+1)=w(n)-µ w *e(n) w dither_new =w dither -m w *e dither Among them, μ w is the iteration step, which is a constant, w dither is the weight of the disturbance signal, w dither_new To perturb the new round of weights obtained through iteration, finally, update the weights and calculate the new round of weights w corresponding to each capacitor n_new ,Since the sum of the weights of each capacitor position remains unchanged, there is In n_new =in n +μ w *(e1+...+e n-1 ) Among them, e1~e n-1 is the error signal mentioned above, According to the above steps, a set of capacitance weights w can be obtained after each LMS iteration. n_new .