Successive approximation type analog-to-digital converter applied to bridging capacitor array and calibration method of successive approximation type analog-to-digital converter

Abstract

The invention discloses a successive approximation type analog-to-digital converter applied to a bridge capacitor array and a calibration method thereof, and belongs to the technical field of SAR ADC design. According to the calibration method of the successive approximation type analog-to-digital converter applied to the bridge capacitor array, the capacitor mismatch error of the SAR ADC can be calibrated in cooperation with the bridge capacitor array, and the capacitor mismatch can be calibrated on the premise that the speed of the SAR ADC is not reduced by additionally arranging a calibration digital module behind SAR logic. The gain error caused by the mismatch of the bridging capacitor can be adjusted by adding an additional gain calibration capacitor in the bridging capacitor array, and the range loss of the whole SAR ADC due to the gain error is avoided by compensating the gain error in the analog domain.

Description

Technical Field

[0001] The present invention belongs to the technical field of SAR ADC design, and in particular relates to a successive approximation analog-to-digital converter applied to a bridge capacitor array. Background Art

[0002] To improve the accuracy of SAR ADCs, the present invention proposes a calibration technique that, in conjunction with a bridge capacitor array, can calibrate the switch capacitor mismatch error of the SAR ADC. By adding a calibration digital module after the SAR logic, the switch capacitor mismatch can be calibrated without reducing the SAR ADC speed. Furthermore, by adding additional gain calibration capacitors to the bridge capacitor array, the gain error caused by the bridge capacitor mismatch can be adjusted. By compensating for the gain error in the analog domain, the entire SAR ADC does not lose range due to gain error. Summary of the Invention

[0003] The present invention aims to provide a successive approximation analog-to-digital converter (A / D converter) for a bridge capacitor array and a calibration method thereof. The calibration method, in conjunction with the bridge capacitor array, can calibrate the switch capacitor mismatch error of a SAR ADC. By adding a calibration digital module after the SAR logic, the switch capacitor mismatch can be calibrated without reducing the speed of the SAR ADC. Furthermore, by adding additional gain calibration capacitors to the bridge capacitor array, the gain error caused by the bridge capacitor mismatch can be adjusted. By compensating for the gain error in the analog domain, the entire SAR ADC does not lose range due to the gain error, thereby resolving the problems raised in the aforementioned background art.

[0004] To achieve the above objectives, as one aspect of the present invention, the present invention provides a successive approximation analog-to-digital converter (ADC) for use with a bridge capacitor array. The ADC comprises four components: a switched capacitor array, a comparator, a SAR logic module, and a calibration logic module.

[0005] Among them, the switched capacitor array inputs differential input signals Vip and Vin as input signals, and simultaneously inputs positive and negative reference levels Vrefp and Vrefn as reference levels; the differential output signals Vtp and Vtn of the switched capacitor array are connected to the differential input signal terminals of the comparator; the output of the comparator is connected to the SAR logic module; the SAR logic module outputs the successive approximation control voltage of the switched capacitor array, and outputs the digital output signal Qana to the calibration logic module; the calibration logic module outputs the gain adjustment control signal to the switched capacitor array, and outputs the final output signal Dout of the successive approximation analog-to-digital converter.

[0006] Preferably, the switch capacitor array includes a capacitor array Carray1, a capacitor array Carray2 and a capacitor array Carray3;

[0007] Among them, the capacitor array Carray1 consists of capacitors C a1 -C an A total of n capacitors are composed, and the top plate of the capacitor is connected to the Vtp potential, where Vtp is connected through the top plate switch S tp Connect to the sampled top plate common mode level Vcm_top; C a1 -C an The capacitor bottom plate is connected to the switch S a1 -S an Connect to the positive reference level Vrefp, negative reference level Vrefn, bottom plate input V bi signal; where V bi The signal passes through switch S in Connect to the input signal V in and the capacitor bottom plate common mode level V in_cm At the same time, the switch S of the capacitor array Carray1 a1 -S an Controlled by SAR logic module;

[0008] Capacitor array Carray2 consists of capacitors C b1 -C bm A total of m capacitors are connected together with the top plates of the capacitors, and the bridge capacitor C br1 Connected to the top plate of capacitor array Carray1; C b1 -C bm The capacitor bottom plate is connected to the switch S b1 -S bm Connected to the positive reference level Vrefp, the negative reference level Vrefn; at the same time, the switch S of the capacitor array Carray2 b1 -S bm Controlled by SAR logic;

[0009] Capacitor array Carray3 consists of capacitors C c1 -C ck A total of k capacitors are connected, the top plates of the capacitors are connected together, through the bridge capacitor C br2 Connected to the top plate of capacitor array Carray2; C c1 -C cm The capacitor bottom plate is connected to the switch S c1 -S cm Connected to the positive reference level Vrefp, the negative reference level Vrefn; at the same time, the switch S of the capacitor array Carray3 c1 -S cm Controlled by the calibration logic module.

[0010] Preferably, the capacitor array Carray1 participates in sampling and requires calibration, the capacitor array Carray2 does not require capacitor mismatch calibration, and the capacitor array Carray3 is used for gain compensation and also does not require capacitor mismatch calibration;

[0011] During normal operation, in the sampling state, Vtp passes through the switch S tp Pull the potential to the common mode level Vcm_top, and the input signal Vin passes through the switch S in and S a1 -S an Input to the top plate of the capacitor array Carray1; during sampling, the capacitor array Carray2 is divided into two equal parts, one part of which is connected to the positive reference level Vrefp and the other part is connected to the negative reference level Vrefn, or directly connected to the common mode level V in_cm At the same time, the sampling of the capacitor bottom plate switch control signal of the capacitor array Carray3 is consistent with the conversion time, and no switch control signal change occurs;

[0012] During normal operation, in the switching phase, the capacitor arrays Carray1 and Carray2 connect one bit at a time to the positive reference level Vrefp or the negative reference level Vrefn according to the output result of the comparator.

[0013] As another aspect of the present invention, the present invention provides a calibration method for a successive approximation analog-to-digital converter applied to a bridge capacitor array, the calibration method comprising:

[0014] At the beginning of the calibration phase, the sampling signal of the capacitor array Carray1 is input through the input switch S in From V in Switch to V in_cm , the sampling input signal changes position throughout the calibration process until the calibration is completed input switch S in Just from V in_cm Switch to V in ;

[0015] The capacitor is from the lowest bit C of the capacitor array Carray1 a1 Start calibration, calibration bit cap_num=1; successive approximation conversion stage, polarity flag cap_pn=1, C a1 Set to 1 to convert the C bm Start; after successive approximation conversion, C bm -C b1 The successive approximation results are quantized according to their digital weights to obtain the initial digital output Dini, which is subtracted from C a1The ideal digital weight output is the capacitance error Derr_p; the polarity flag cap_pn=0, C a1 Set to 0, successive approximation conversion from capacitor array Carray2 C bm Start by converting C bm -C b1 The successive approximation results are quantized according to their digital weights to obtain the initial digital output Dini, which is subtracted from C a1 The ideal digital weight output is the capacitance error Derr_n; Derr_p-Derr_n is used to get C a1 The error code Werr(1);

[0016] Calibration digit Cap_num=2, for C a2 Perform calibration; cap_pn=1, C a2 Set to 1 to convert the C a1 Start; after successive approximation conversion, C a1 ,C bm -C b1 The successive approximation results are quantized according to their digital weights to obtain the initial digital output Dini, which is subtracted from C a1 The ideal digital weight output is the capacitance error Derr_p; the polarity flag cap_pn=0, C a2 Set to 0, successive approximation conversion from capacitor array Carray2 C b1 Start by converting C a1 ,C bm -C b1 The successive approximation results are quantized according to their digital weights to obtain the initial digital output Dini. The capacitance error Derr_n is obtained by subtracting the ideal digital weight output of Ca1 from Dini. C is obtained by subtracting Derr_p from Derr_n. a2 Error code Werr(2);

[0017] Use the same calibration method as above until the calibration bit Cap_num=n, and then an Perform calibration; cap_pn=1, C an Set to 1, successive approximation conversion from C array 1 an-1 Start; after successive approximation conversion, C an-1 -C a1 ,C bm -C b1 The successive approximation results are quantized according to their digital weights to obtain the initial digital output Dini, which is subtracted from C anThe ideal digital weight output is the capacitance error Derr_p; the polarity flag cap_pn=0, C a2 Set to 0, successive approximation conversion from C array 2 an Start by converting C an-1 -C a1 ,C bm -C b1 The successive approximation results are quantized according to their digital weights to obtain the initial digital output Dini, which is subtracted from C an The ideal digital weight output is the capacitance error Derr_n; Derr_p-Derr_n is used to get C an The error code Werr(n) is .

[0018] Preferably, the calibration method further comprises:

[0019] In the process of quantizing the initial digital output Dini, if the calibrated capacitor C is included a1 -C an-1， The error code Werr(1)-Werr(n-1) is used for calibration compensation.

[0020] Preferably, the calibration method further comprises:

[0021] After the capacitance calibration of the capacitor array Carray1 is completed, Werr(1) to Werr(n) are added to obtain the gain error coefficient Wtot. If Wtot does not meet the expected indicator Wspec, the capacitor array Carray3 is adjusted by using a step or binary successive approximation, or a successive approximation method less than binary to adjust the value of the capacitor array Carray3. Then, the above capacitance adjustment steps are repeated until Wtot≤Wspec. At this time, the calibration process is completed and enters the normal operation stage.

[0022] Compared with the prior art, the present invention has the following beneficial effects:

[0023] The present invention is a method for successive approximation analog-to-digital conversion calibration applied to a bridge capacitor array. Compared with the traditional solution, the error compensation of the capacitor array is in the digital calibration module. As the process evolves, the area and power consumption of this part will become smaller and smaller, and the compensation of the capacitor error in the digital domain will not affect the analog conversion speed of the SAR ADC, so the sampling rate of the ADC is not reduced while the accuracy is improved. At the same time, the gain error compensation part effectively reduces the gain error of the ADC on the one hand, and on the other hand, it also compensates for the accuracy of the bridge capacitor structure switch capacitor array, because the bridge capacitor is usually affected by the parasitic capacitance before and after, causing the ratio of the bridge capacitor before and after to deviate from the design value, and the deviation of the parasitic capacitance is limited by the accuracy of the capacitor model and the accuracy of the analog layout parameter extraction tool. The actual chip value often deviates from the design value, and the gain calibration scheme of the present invention can compensate for the error caused by the bridge capacitor mismatch, avoiding repeated tape-out iterations due to design tool problems. In addition, the gain compensation used in the present invention is to directly add the gain compensation capacitor Carray3 to the capacitor array and perform compensation directly in the analog domain, so that the ADC can use the full range, with low power consumption and small area. Unlike digital gain compensation solutions, which cause the ADC to lose the range of the highest and lowest code parts and require a bit-calibrated divider to ensure calibration accuracy, traditional gain calibration solutions usually come at the cost of large area and high power consumption for this reason. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 The module block diagram of a successive approximation analog-to-digital converter applied to a bridge capacitor array of the present invention.

[0025] Figure 2 The figure is a schematic diagram of a capacitor array of a successive approximation analog-to-digital converter applied to a bridge capacitor array according to the present invention.

[0026] Figure 3 The present invention is a calibration flow chart of a successive approximation analog-to-digital converter applied to a bridge capacitor array.

[0027] Figure 4 The present invention is a flowchart of the work flow of a successive approximation analog-to-digital converter applied to a bridge capacitor array. DETAILED DESCRIPTION

[0028] The following will be combined with the accompanying drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.

[0029] The present invention proposes a successive approximation analog-to-digital converter for a bridge capacitor array. The entire successive approximation converter consists of four parts: a switched capacitor array, a comparator, a SAR logic module, and a calibration logic module (e.g., Figure 1 As shown). The differential input signals Vip and Vin are connected to the switched capacitor array as input signals, and the positive and negative reference levels Vrefp and Vrefn are input to the switched capacitor array. The differential output signals Vtp and Vtn of the switched capacitor array are connected to the differential input signal terminals of the comparator. The output of the comparator is connected to the SAR logic. The SAR logic outputs the successive approximation control voltage of the switched capacitor array and connects the digital output Qana to the calibration logic module. The calibration logic module outputs the gain adjustment control signal to the switched capacitor array and outputs the final output Dout of the successive approximation analog-to-digital converter. Among the four modules, the switched capacitor array and the calibration logic module are the parts involved in the invention, while the comparator and SAR logic are traditional structures and will not be described in detail.

[0030] Switched capacitor arrays (such as Figure 2 As shown in the figure, it is divided into three parts: Capacitor array Carray1 that participates in sampling and needs to be calibrated; Capacitor array Carray2 that does not require capacitor mismatch calibration; Capacitor array Carray3 that is used for gain compensation and does not require capacitor mismatch calibration. Carray1 consists of capacitor C a1 -C an A total of n capacitors are connected, and the top plate of the capacitor is connected to the Vtp potential, where Vtp is connected to the sampled top plate common mode level Vcm_top through a switch. a1 -C an The capacitor bottom plate is connected to the switch S a1 -S an Connected to "1" (positive reference level Vrefp), "0" (negative reference level Vrefn), bottom plate input V bi signal, where V bi The signal passes through switch S in Connect to the input signal V in and the capacitor bottom plate common mode level V in_cm . Carray1 switch S a1 -S an Controlled by SAR logic. Carray2 is controlled by capacitor C b1 -C bm A total of m capacitors are connected, and the top plates of the capacitors are connected together and connected to the top plate of the Carray1 capacitor through the bridge capacitor Cbr1. b1 -C bm The capacitor bottom plate is connected to the switch S b1 -S bmConnected to "1" (positive reference level Vrefp) and "0" (negative reference level Vrefn). Carray2's switch S b1 -S bm Controlled by SAR logic. Carray3 is controlled by capacitor C c1 -C ck A total of k capacitors are connected, the top plates of the capacitors are connected together, and connected to the top plate of the Carray2 capacitor through the bridge capacitor Cbr2. c1 -C cm The capacitor bottom plate is connected to the switch S c1 -S ck Connected to "1" (positive reference level Vrefp) and "0" (negative reference level Vrefn). Carray2's switch S b1 -S bm Controlled by calibration logic. During normal operation, Vtp is switched on by switch S tp Pull the potential to the common mode level Vcm_top, the input signal Vin passes through the switch Sin and S a1 -S an Input to the top plate of the capacitor of Carray1. When sampling, Carray2 can split the capacitor into two equal parts, one connected to "1" and the other to "0", or directly connect to the common mode level V in_cm The sampling of the capacitor bottom plate switch control signal of the capacitor array Carray3 is consistent with the conversion time, and the switch control signal does not change. During calibration, Vtp pulls the potential to the common mode level Vcm_top through the switch during the sampling phase. The common mode level V in_cm By switching Sin and S a1 -S an The input capacitors to Carray1, Carray2, and Carray3 are the same as in normal operation. During the switching phase, Carray1 and Carray2 are connected to "1" / "0" one bit at a time according to the comparator output.

[0031] Figure 3 The calibration flow chart shows that at the beginning of the calibration phase, the sampling signal of the capacitor array is input from V in Switch to V in_cm The change position of the sampling input signal is the whole calibration process, and the input switch Sin is not changed from V to in_cm Switch to V in The capacitance is from the lowest bit C of Carray1 a1 Start calibration, calibration bit cap_num = 1. Successive approximation conversion stage, polarity flag cap_pn = 1, C a1Set to 1 (in differential conversion mode, the P-side capacitor array C a1 Set to 1, and set Ca1 of the N-end capacitor array to 0. The capacitors involved below are similarly operated and will not be described separately). Successive approximation conversion is performed from C of Carray2 bm After the successive approximation conversion, C bm -C b1 The successive approximation results are quantized according to their digital weights to obtain the initial digital output Dini, which is subtracted from C a1 The ideal digital weight output is the capacitance error Derr_p. The polarity flag cap_pn=0, C a1 Set to 0, successive approximation conversion from C array 2 bm Start by converting C bm -C b1 The successive approximation results are quantized according to their digital weights to obtain the initial digital output Dini, which is subtracted from C a1 The ideal digital weight output is the capacitance error Derr_n. Subtract Derr_p from Derr_n to get C a1 The error code Werr(1). Cap_num=2, for C a2 Calibration.cap_pn=1,C a2 Set to 1, successive approximation conversion from C array 1 a1 At the beginning, after successive approximation conversion, C a1 ,C bm -C b1 The successive approximation results are quantized according to their digital weights to obtain the initial digital output Dini, which is subtracted from C a1 The ideal digital weight output is the capacitance error Derr_p. The polarity flag cap_pn=0, C a2 Set to 0, successive approximation conversion from C array 2 a1 Start by converting C a1 ,C bm -C b1 The successive approximation results are quantized according to their digital weights to obtain the initial digital output Dini, which is subtracted from C a1 The ideal digital weight output is the capacitance error Derr_n. Subtract Derr_p from Derr_n to get C a2 The error code Werr(2) is obtained by using the same calibration method until Cap_num=n. an Calibration. cap_pn=1, Can is set to 1, successive approximation conversion from C of Carray1an-1 At the beginning, after successive approximation conversion, C an-1 -C a1 ,C bm -C b1 The successive approximation results are quantized according to their digital weights to obtain the initial digital output Dini. The capacitance error Derr_p is obtained by subtracting the ideal digital weight output of Can from Dini. a2 Set to 0, successive approximation conversion from C array 2 an Start by converting C an-1 -C a1 ,C bm -C b1 The successive approximation results are quantized according to their digital weights to obtain the initial digital output Dini, which is subtracted from C an The ideal digital weight output is the capacitance error Derr_n. Subtract Derr_p from Derr_n to get C an The error code Werr(n) is obtained by quantizing Dini. Note that if the calibrated capacitor C is included in the above process, a1 -C an-1 The error code Werr(1)-Werr(n-1) should be used for calibration compensation. After the capacitor calibration is completed, Werr(1) to Werr(n) are added to obtain the gain error coefficient Wtot. If Wtot does not meet the expected indicator Wspec, the gain compensation DAC, namely Carray3, should be adjusted. The value of Carray3 can be adjusted using a step or binary successive approximation method, or a successive approximation method less than binary. Then repeat the above capacitor adjustment steps until Wtot ≤ Wspec. The calibration is completed and the normal operation phase begins.

[0032] Figure 4 The following is the SAR ADC workflow diagram. The first stage is to reset the digital weight error, and Werr(1)-Werr(n) are all set to 0. The second stage is the calibration stage. First, the calibration mode is entered. In the sampling stage, the switch Sin is switched from V in Switch to V in_cm , the conversion phase is reflected by the calibration capacitor C ax Set to 1 / 0 and gradually approach the next digit C of the calibrated capacitor ax-1 Start from C a1 -C an Gradually obtain the digital weight error Werr(1)-Werr(n). Obtain the control value of the gain compensation capacitor through iteration; exit the calibration mode, which is reflected in the sampling stage as the switch Sin changes from V in_cmSwitch to V in , the conversion phase resumes from the highest bit C an The third stage is the normal working stage. The value of Carray3 is the calibrated control value. After the normal SAR conversion, Qana is obtained. After the digital module is used to calculate C a1 -C an The error code Werr(1)-Werr(n) is compensated by the digital weights to obtain the final digital output Dout.

[0033] The present invention is a successive approximation analog-to-digital conversion calibration applied to a bridge capacitor array. Compared with the traditional solution, the error compensation of the capacitor array is in the digital calibration module. As the process evolves, the area and power consumption of this part will become smaller and smaller, and the compensation of the capacitor error in the digital domain will not affect the analog conversion speed of the SAR ADC, so the sampling rate of the ADC is not reduced while the accuracy is improved. At the same time, the gain error compensation part effectively reduces the gain error of the ADC on the one hand, and on the other hand, it also compensates for the accuracy of the bridge capacitor structure switch capacitor array, because the bridge capacitor is usually affected by the parasitic capacitance before and after, causing the ratio of the bridge capacitor before and after to deviate from the design value, and the deviation of the parasitic capacitance is limited by the accuracy of the capacitor model and the accuracy of the analog layout parameter extraction tool. The actual chip value often deviates from the design value, and the gain calibration scheme of the present invention can compensate for the error caused by the bridge capacitor mismatch, avoiding repeated tape-out iterations due to design tool problems. In addition, the gain compensation used in the present invention is to directly add the gain compensation capacitor Carray3 to the capacitor array and perform compensation directly in the analog domain, so that the ADC can use the full range, with low power consumption and small area. Unlike digital gain compensation solutions, which cause the ADC to lose the range of the highest and lowest code parts and require a bit-calibrated divider to ensure calibration accuracy, traditional gain calibration solutions usually come at the cost of large area and high power consumption for this reason.

[0034] Although the preferred embodiments of the present invention have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present invention.

[0035] Obviously, those skilled in the art may make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if such changes and modifications fall within the scope of the claims and their equivalents, the present invention is intended to include such changes and modifications.

Claims

1. A successive approximation analog-to-digital converter for a bridge capacitor array, characterized in that: The successive approximation analog-to-digital converter consists of four parts: a switched capacitor array, a comparator, a SAR logic module, and a calibration logic module. Among them, the switched capacitor array inputs differential input signals Vip and Vin as input signals, and simultaneously inputs positive and negative reference levels Vrefp and Vrefn as reference levels; the differential output signals Vtp and Vtn of the switched capacitor array are connected to the differential input signal terminals of the comparator; the output of the comparator is connected to the SAR logic module; the SAR logic module outputs the successive approximation control voltage of the switched capacitor array, and outputs the digital output signal Qana to the calibration logic module; the calibration logic module outputs the gain adjustment control signal to the switched capacitor array, and outputs the final output signal Dout of the successive approximation analog-to-digital converter.

2. The successive approximation analog-to-digital converter for a bridge capacitor array according to claim 1, wherein: The switch capacitor array includes a capacitor array Carray1, a capacitor array Carray2 and a capacitor array Carray3; Among them, the capacitor array Carray1 consists of capacitors C a1 -C an A total of n capacitors are composed, and the top plate of the capacitor is connected to the Vtp potential, where Vtp is connected through the top plate switch S tp Connect to the sampled top plate common mode level Vcm_top; C a1 -C an The capacitor bottom plate is connected to the switch S a1 -S an Connect to the positive reference level Vrefp, negative reference level Vrefn, bottom plate input V bi signal; where V bi The signal passes through switch S in Connect to the input signal V in and the capacitor bottom plate common mode level V in_cm At the same time, the switch S of the capacitor array Carray1 a1 -S an Controlled by SAR logic module; Capacitor array Carray2 consists of capacitors C b1 -C bm A total of m capacitors are connected together with the top plates of the capacitors, and the bridge capacitor C br1 Connected to the top plate of capacitor array Carray1; C b1 -C bm The capacitor bottom plate is connected to the switch S b1 -S bm Connected to the positive reference level Vrefp, the negative reference level Vrefn; at the same time, the switch S of the capacitor array Carray2 b1 -S bm Controlled by SAR logic; Capacitor array Carray3 consists of capacitors C c1 -C ck A total of k capacitors are connected, the top plates of the capacitors are connected together, through the bridge capacitor C br2 Connected to the top plate of capacitor array Carray2; C c1 -C cm The capacitor bottom plate is connected to the switch S c1 -S cm Connected to the positive reference level Vrefp, the negative reference level Vrefn; at the same time, the switch S of the capacitor array Carray3 c1 -S cm Controlled by the calibration logic module.

3. The successive approximation analog-to-digital converter for a bridge capacitor array according to claim 2, wherein: The capacitor array Carray1 participates in sampling and needs to be calibrated, the capacitor array Carray2 does not require capacitor mismatch calibration, and the capacitor array Carray3 is used for gain compensation and also does not require capacitor mismatch calibration; During normal operation, in the sampling state, Vtp passes through the switch S tp The potential is pulled to the common-mode level Vcm_top, and the input signal Vin is input to the top plate of capacitor array Carray1 through switches Sin and Sa1-San. Capacitor array Carray2 splits the capacitor into two equal parts, one of which is connected to the positive reference level Vrefp and the other to the negative reference level Vrefn, or directly to the common-mode level Vin_cm. The switch control signal sampling of the bottom plate of capacitor array Carray3 is consistent with the conversion time, and the switch control signal does not change. During normal operation, in the switching phase, the capacitor arrays Carray1 and Carray2 connect one bit at a time to the positive reference level Vrefp or the negative reference level Vrefn according to the output result of the comparator.

4. A calibration method for a successive approximation analog-to-digital converter applied to any one of 1-3 bridge capacitor arrays, characterized in that: The calibration process includes: At the beginning of the calibration phase, the sampling signal of the capacitor array Carray1 is input through the input switch S in From V in Switch to V in_cm , the sampling input signal changes position throughout the calibration process until the calibration is completed input switch S in Just from V in_cm Switch to V in ; The capacitor is from the lowest bit C of the capacitor array Carray1 a1 Start calibration, calibration bit cap_num=1; successive approximation conversion stage, polarity flag cap_pn=1, C a1 Set to 1 to convert the C bm Start; after successive approximation conversion, C bm -C b1 The successive approximation results are quantized according to their digital weights to obtain the initial digital output Dini, which is subtracted from C a1 The ideal digital weight output is the capacitance error Derr_p; the polarity flag cap_pn=0, C a1 Set to 0, successive approximation conversion from capacitor array Carray2 C bm Start by converting C bm -C b1 The successive approximation results are quantized according to their digital weights to obtain the initial digital output Dini, which is subtracted from C a1 The ideal digital weight output is the capacitance error Derr_n; Derr_p-Derr_n is used to get C a1 The error code Werr(1); Calibration digit Cap_num=2, for C a2 Perform calibration; cap_pn=1, C a2 Set to 1 to convert the C a1 Start; after successive approximation conversion, C a1 ,C bm -C b1 The successive approximation results are quantized according to their digital weights to obtain the initial digital output Dini, which is subtracted from C a1 The ideal digital weight output is the capacitance error Derr_p; the polarity flag cap_pn=0, C a2 Set to 0, successive approximation conversion from capacitor array Carray2 C b1 Start by converting C a1 ,C bm -C b1 The successive approximation results are quantized according to their digital weights to obtain the initial digital output Dini. The capacitance error Derr_n is obtained by subtracting the ideal digital weight output of Ca1 from Dini. C is obtained by subtracting Derr_p from Derr_n. a2 Error code Werr(2); Use the same calibration method as above until the calibration bit Cap_num=n, and then an Perform calibration; cap_pn=1, C an Set to 1, successive approximation conversion from C array 1 an-1 Start; after successive approximation conversion, C an-1 -C a1 ,C bm -C b1 The successive approximation results are quantized according to their digital weights to obtain the initial digital output Dini, which is subtracted from C an The ideal digital weight output is the capacitance error Derr_p; the polarity flag cap_pn=0, C a2 Set to 0, successive approximation conversion from C array 2 an Start by converting C an-1 -C a1 ,C bm -C b1 The successive approximation results are quantized according to their digital weights to obtain the initial digital output Dini, which is subtracted from C an The ideal digital weight output is the capacitance error Derr_n; Derr_p-Derr_n is used to get C an The error code Werr(n) is .

5. The calibration method of a successive approximation analog-to-digital converter of a bridge capacitor array according to claim 4, wherein: The calibration process also includes: In the process of quantizing the initial digital output Dini, if the calibrated capacitor C is included a1 -C an-1， The error code Werr(1)-Werr(n-1) is used for calibration compensation.

6. The calibration method of a successive approximation analog-to-digital converter of a bridge capacitor array according to claim 5, wherein: The calibration process also includes: After the capacitance calibration of the capacitor array Carray1 is completed, Werr(1) to Werr(n) are added to obtain the gain error coefficient Wtot. If Wtot does not meet the expected indicator Wspec, the capacitor array Carray3 is adjusted by using a step or binary successive approximation, or a successive approximation method less than binary to adjust the value of the capacitor array Carray3. Then, the above capacitance adjustment steps are repeated until Wtot≤Wspec. At this time, the calibration process is completed and enters the normal operation stage.

Images