Successive approximation register type analog-to-digital conversion system for brain-computer interface

Abstract

The invention relates to a successive approximation register type analog-to-digital conversion system for a brain-computer interface, which is characterized in that a P-end input and an N-end input are respectively connected with two bootstrap sampling switch modules to form a differential signal acquisition channel, and the two bootstrap sampling switch modules are symmetrically designed to suppress common-mode noise; the two bootstrap sampling switch modules are respectively connected to the two segmented CDAC array modules, the segmented CDAC array modules are divided into a high-segment capacitor bank and a low-segment capacitor bank, and the high-segment capacitor bank and the low-segment capacitor bank are connected through a bridging capacitor; the output end of the segmented CDAC array module is connected to the differential input end of the dynamic comparator module, and a comparison result is output to the SAR logic module; the SAR logic module is based on event-driven dynamic logic control, outputs 12-bit digital codes, feeds back control signals to the segmented CDAC array module at the same time, and adjusts a capacitor switching strategy. Compared with the prior art, the invention has the advantages of high precision, low energy consumption, miniaturization and the like.

Description

Technical Field

[0001] The present invention relates to the technical field of analog-to-digital converter integrated circuits, and in particular to a successive approximation register type analog-to-digital conversion system for a brain-computer interface. Background Art

[0002] In brain-computer interface (BCI) systems, the analog-to-digital converter (ADC) is a core module in the signal acquisition chain. Its performance directly determines the accuracy of neural signal conversion and system reliability. Currently, mainstream ADC architectures include successive approximation register (SAR), delta-sigma modulators, and pipeline architectures. While these technologies demonstrate advantages in various scenarios, they still face significant challenges in meeting the stringent BCI system requirements for high precision, ultra-low power consumption, and a wide input range.

[0003] While traditional SAR ADCs offer low power consumption, their effective resolution is limited by comparator metastability and capacitor matching errors, making them inadequate for high-precision neural signal acquisition. ΔΣ modulators can achieve higher resolution through oversampling, but their multi-stage active integrator design significantly increases power consumption, making them incapable of meeting the ultra-low energy requirements of long-term implantable devices. Pipeline ADCs, while offering a balance between speed and accuracy, rely on complex digital calibration circuitry, significantly increasing chip area and limiting their application in highly integrated scenarios. Furthermore, neural signals are characterized by extremely low amplitude and wide bandwidth, while also needing to accommodate wide input fluctuations caused by electrode offset. Existing ADC designs commonly suffer from insufficient input dynamic range and limited noise rejection, making it difficult to balance low-amplitude signal acquisition with high offset tolerance. For example, the input range of traditional SAR ADCs often cannot cover the dynamic requirements of neural signals, and capacitor array switching noise further impacts multichannel signal integrity. These limitations make it difficult for existing ADC technology to achieve both high resolution and a wide input range while maintaining low power consumption, severely hindering the performance and clinical application potential of BCI systems.

[0004] Chinese patent application CN115987231A utilizes chopping and subthreshold technologies, employing a 12-bit SAR ADC to convert analog signals into digital signals to achieve low power consumption. A fully differential chopping instrumentation amplifier circuit serves as the first stage of the front-end amplification module. However, this application relies on static subthreshold technology and does not introduce active power consumption control methods such as dynamic logic architecture or segmented CDAC. This makes it difficult to further reduce static power consumption under complex operating conditions. Furthermore, for general biosignal acquisition, such as electrocardiogram and blood pressure, the bandwidth and sampling rate are not optimized for the wide-bandwidth characteristics of neural signals, potentially leading to high-frequency signal attenuation or aliasing. Therefore, achieving an optimal balance between key performance parameters of the SAR ADC to meet the comprehensive requirements of brain-computer interface systems for high precision, low power consumption, and strong environmental adaptability is a technical problem that needs to be solved. Summary of the Invention

[0005] The purpose of the present invention is to overcome the defects of the above-mentioned prior art and to provide a successive approximation register type analog-to-digital conversion system for brain-computer interface. Through the dynamic gate bias control technology of the bootstrap sampling switch module, the gate-source voltage of the MOS switch tube is fixed, the influence of the input signal amplitude change on the on-resistance is eliminated, and the accuracy of the collected signal is improved.

[0006] The purpose of the present invention can be achieved by the following technical solutions:

[0007] According to one aspect of the present invention, there is provided a successive approximation register type analog-to-digital conversion system for a brain-computer interface, comprising: a bootstrap sampling switch module, a segmented CDAC array module, a dynamic comparator module, and a SAR logic module;

[0008] The P-terminal input and N-terminal input are respectively connected to two bootstrap sampling switch modules to form a differential signal acquisition channel. The two bootstrap sampling switch modules are symmetrically designed to suppress common-mode noise. The two bootstrap sampling switch modules are respectively connected to two segmented CDAC array modules. The segmented CDAC array modules are divided into high-segment capacitor groups and low-segment capacitor groups, which are connected through bridge capacitors, and one redundant bit is inserted in each segment. The output of the segmented CDAC array module is connected to the differential input of the dynamic comparator module, and the comparison result is output to the SAR logic module. The SAR logic module is based on event-driven dynamic logic control, outputs a 12-bit digital code, and simultaneously feeds back control signals to the segmented CDAC array module to adjust the capacitor switching strategy.

[0009] Furthermore, the bootstrap sampling switch module includes a bootstrap capacitor and several MOS transistors; dynamic gate bias control logic is implemented by connecting clock signals to the gates of the first MOS transistor, the gates of the third MOS transistor, the gates of the fourth MOS transistor, the gates of the eighth MOS transistor, and the gates of the ninth MOS transistor. When in the reset phase, the dynamic gate bias control logic controls the charging path of the bootstrap capacitor, connecting the two ends of the bootstrap capacitor to the power supply VDD and the ground, respectively. When in the sampling phase, the control logic is switched, connecting one end of the bootstrap capacitor to the input signal Vin, and the other end of the bootstrap capacitor to the gate of the first MOS transistor, so that the gate voltage of the first MOS transistor is constant at VDD.

[0010] Furthermore, the specific connection method of the bootstrap sampling switch module includes: the source of the second MOS tube, the source of the third MOS tube, the gate of the seventh MOS tube, and the source of the eighth MOS tube are connected to VDD; the gate of the first MOS tube, the gate of the third MOS tube, the gate of the fourth MOS tube, the gate of the eighth MOS tube, and the gate of the ninth MOS tube are connected to the clock signal; the gate of the second MOS tube is connected to the drain of the fifth MOS tube and the source of the seventh MOS tube; the drain of the third MOS tube is connected to the source of the fourth MOS tube, the gate of the fifth MOS tube, and the drain of the sixth MOS tube The source of the fourth MOS transistor is connected to the source of the sixth MOS transistor and the drain of the tenth MOS transistor; the drain of the second MOS transistor is connected to the source of the fifth MOS transistor; the gate of the sixth MOS transistor is connected to the source of the seventh MOS transistor, the gate of the tenth MOS transistor, and the gate of the eleventh MOS transistor; the source of the tenth MOS transistor and the source of the eleventh MOS transistor are connected to the input signal Vin; the drain of the seventh MOS transistor is connected to the drain of the eighth MOS transistor and the source of the ninth MOS transistor; the drain of the eleventh MOS transistor is the output signal Vout; the source of the first MOS transistor and the drain of the ninth MOS transistor are grounded.

[0011] Furthermore, the segmented CDAC array module includes a high-segment capacitor group, a low-segment capacitor group and a bridging capacitor; in the sampling stage, the bottom plates of the capacitors are all connected to the common-mode voltage VCM; in the conversion stage, according to the feedback control signal of the SAR logic module, the bottom plates of the capacitors are switched to VDD or GND, and the high-segment capacitor group is switched first. During the conversion process, the switching of the high-segment capacitor group transfers charge to the low-segment capacitor group through the bridging capacitor, so that the charge distribution ratio between the high and low segments accurately matches the binary weight.

[0012] Furthermore, the high-segment capacitor group includes a first capacitor, a second capacitor, a third capacitor, a fourth capacitor, a fifth capacitor, a sixth capacitor and a seventh capacitor, wherein the seventh capacitor is a high-segment redundant capacitor, the top plates of the capacitors of the high-segment capacitor group are connected in parallel and jointly linked to the common-mode voltage VCM, and the bottom plates of each capacitor of the high-segment capacitor group are independently controlled by the signal sent by the SAR logic module; the low-segment capacitor group includes an eighth capacitor, a ninth capacitor, a tenth capacitor, an eleventh capacitor, a twelfth capacitor, a thirteenth capacitor and a fourteenth capacitor, wherein the eighth capacitor is a low-segment redundant capacitor, the top plates of the capacitors of the low-segment capacitor group are connected in parallel and jointly linked to the output voltage VOUT, and the bottom plates of each capacitor of the low-segment capacitor group are independently controlled by the signal sent by the SAR logic module.

[0013] Furthermore, the bridging capacitor is arranged between the high-segment capacitor group and the low-segment capacitor group to compensate for the difference in parasitic capacitance. When redistributing charge, it ensures that the charge transfer ratio from the high-segment capacitor group to the low-segment capacitor group accurately matches the binary weight, thereby avoiding nonlinear errors caused by inter-segment mismatch.

[0014] Furthermore, the dynamic comparator module includes a pre-amplification stage and a dynamic latch stage;

[0015] The pre-amplifier stage includes an input differential pair, a cascode load, and a dynamic bias unit; the input differential pair includes a twelfth MOS transistor and a thirteenth MOS transistor, the gate of the twelfth MOS transistor is connected to the input signal Vip, and the drain is connected to the drain of the fourteenth MOS transistor, the gate of the thirteenth MOS transistor is connected to the input signal Vin, and the drain is connected to the drain of the fifteenth MOS transistor; the cascode load includes a fourteenth MOS transistor and a fifteenth MOS transistor with a common gate, and the drains are both connected to the dynamic bias unit; the dynamic bias unit includes a first bias and a second bias, the first bias includes the sixteenth MOS transistor and the seventeenth MOS transistor, the second bias includes the eighteenth MOS transistor and the nineteenth MOS transistor, and the gates of the sixteenth MOS transistor and the nineteenth MOS transistor are connected to the clock signal;

[0016] The dynamic latch stage includes a cross-coupled MOS transistor and a reset switch; the cross-coupled MOS transistor includes a 20th MOS transistor and a 21st MOS transistor, the gate of the 20th MOS transistor is connected to the drain of the 12th MOS transistor, and the gate of the 21st MOS transistor is connected to the drain of the 13th MOS transistor; the reset switch includes a 22nd MOS transistor and a 23rd MOS transistor.

[0017] Furthermore, in the reset phase, the clock signal is 1, the sixteenth and seventeenth MOS transistors are turned on, and the pre-amplifier stage output is pulled down to GND; the twenty-second and twenty-third MOS transistors are turned on, and the output signal nodes Voutp and Voutn are reset to GND; the eighteenth and nineteenth MOS transistors are turned off, cutting off the pre-amplifier stage pull-up path, and the twentieth and twenty-first MOS transistors are pre-charged to VDD; in the evaluation phase, the clock signal is 0, the input differential signal modulates the pre-amplifier stage output, the sixteenth and seventeenth MOS transistors are turned off, and the eighteenth and nineteenth MOS transistors are turned on; the input differential signal modulates the current through the twelfth and thirteenth MOS transistors, resulting in a voltage difference at the output node of the pre-amplifier stage, and the voltage difference is transmitted to the output signal nodes Voutp and Voutn; in the regeneration phase, the clock signal remains 0, and the cross-coupled MOS transistors amplify the difference through positive feedback based on the voltage difference between the output signal nodes Voutp and Voutn.

[0018] Furthermore, the SAR logic module includes a clock control module, a dynamic latch, and a drive circuit. Based on event-driven dynamic logic control, it outputs a 12-bit digital code and simultaneously feeds back a control signal to the segmented CDAC array module to adjust the capacitor switching strategy. The clock control module controls non-overlapping clock signals to obtain a pre-charge phase, a latch phase, and a switching phase, and drives the switching of each capacitor in the segmented CDAC array module. The dynamic latch includes a cross-coupled inverter and a reset switch, which are cross-connected to form a positive feedback loop through the cross-coupled inverters. The drive circuit generates a segmented CDAC array module control signal D.

[0019] Furthermore, in the pre-charging stage, the clock signal is 1, Pi and Ni are charged to a high level through VDD, Outp and Outn are reset to GND, and the Valid signal is set low; in the latching stage, the logic path is cut off, the result of the dynamic comparator module is stored in the dynamic latch, and the differential signals Pi and Ni output by the dynamic comparator are transmitted to the dynamic node. The cross-coupled inverter quickly adjusts the output signals Outp and Outn according to the voltage difference between Pi and Ni; in the switching stage, the levels of the output signals Outp and Outn are transmitted to the D signal line to generate specific segmented CDAC array module control signals.

[0020] Compared with the prior art, the present invention has the following beneficial effects:

[0021] (1) High-precision signal acquisition: Through the dynamic gate bias control technology of the bootstrap sampling switch module, the gate-source voltage of the MOS switch tube is fixed, the influence of the input signal amplitude change on the on-resistance is eliminated, the harmonic distortion is significantly suppressed, the sampling linearity is improved, and the high-precision acquisition requirements of the brain-computer interface for weak neural signals are met. The charge pump bootstrap circuit ensures that the on-resistance remains unchanged during the change of the input signal, and tubes with different width-to-length ratios are designed for each different driving capability.

[0022] (2) High fault tolerance and conversion accuracy: The segmented CDAC array module adopts redundant bit design and bridge capacitor compensation mechanism. The redundant bits absorb comparator noise and timing errors by overlapping code values. The bridge capacitors accurately match the parasitic capacitance differences between high and low segments, ensuring the monotonicity and continuity of the charge redistribution process, effectively avoiding nonlinear errors and improving the overall conversion accuracy.

[0023] (3) Low-power operation: The dynamic comparator module adopts a fully dynamic latch structure, which consumes energy only briefly during the regeneration phase and has no static current path; the SAR logic module is based on event-driven control, and strictly isolates the pre-charging, latching and switching phases through non-overlapping clocks, and triggers dynamic node operations only when the state changes, significantly reducing the total power consumption of the system, which is suitable for long-term low-energy operation of implantable devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 This is a framework diagram of a successive approximation register-based analog-to-digital conversion system for brain-computer interface;

[0025] Figure 2 Circuit diagram of the bootstrap sampling switch module;

[0026] Figure 3 is a circuit diagram of a segmented CDAC array module;

[0027] Figure 4 This is the circuit diagram of the dynamic comparator module;

[0028] Figure 5 This is the circuit diagram of the SAR logic module;

[0029] Figure 6 Graph showing the output spectrum in the embodiment. DETAILED DESCRIPTION

[0030] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are part of the embodiments of the present invention, not all of them. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts should fall within the scope of protection of the present invention.

[0031] like Figure 1 Figure 1 shows a successive approximation register (SAR) analog-to-digital conversion system for brain-computer interfaces (BCIs). The system includes a bootstrap sampling switch module, a segmented CDAC array module, a dynamic comparator module, and a SAR logic module. The P- and N-terminal inputs are connected to two bootstrap sampling switch modules, forming a differential signal acquisition channel. The two bootstrap sampling switch modules are symmetrically designed to suppress common-mode noise. The two bootstrap sampling switch modules are connected to two segmented CDAC array modules, each divided into a high-segment capacitor group and a low-segment capacitor group connected via bridge capacitors, with one redundant bit inserted in each segment. The outputs of the segmented CDAC array modules are connected to the differential inputs of the dynamic comparator module, and the comparison results are output to the SAR logic module. The SAR logic module is event-driven and dynamically controlled, outputting a 12-bit digital code and simultaneously feeding back control signals to the segmented CDAC array module to adjust the capacitor switching strategy.

[0032] like Figure 2 As shown, the bootstrap sampling switch module includes a bootstrap capacitor and several MOS transistors. Dynamic gate bias control logic is implemented by connecting clock signals to the gates of the first MOS transistor, the gates of the third MOS transistor, the gates of the fourth MOS transistor, the gates of the eighth MOS transistor, and the gates of the ninth MOS transistor. When in the reset phase, the dynamic gate bias control logic controls the charging path of the bootstrap capacitor, connecting the two ends of the bootstrap capacitor to the power supply VDD and the ground respectively. When in the sampling phase, the control logic is switched to connect one end of the bootstrap capacitor to the input signal Vin and the other end of the bootstrap capacitor to the gate of the first MOS transistor, so that the gate voltage of the first MOS transistor is constant at VDD.

[0033] The specific connection method of the bootstrap sampling switch module includes: the source of the second MOS tube, the source of the third MOS tube, the gate of the seventh MOS tube and the source of the eighth MOS tube are connected to VDD; the gate of the first MOS tube, the gate of the third MOS tube, the gate of the fourth MOS tube, the gate of the eighth MOS tube and the gate of the ninth MOS tube are connected to the clock signal; the gate of the second MOS tube is connected to the drain of the fifth MOS tube and the source of the seventh MOS tube; the drain of the third MOS tube is connected to the source of the fourth MOS tube, the gate of the fifth MOS tube and the drain of the sixth MOS tube; the fourth The source of the MOS transistor is connected to the source of the sixth MOS transistor and the drain of the tenth MOS transistor; the drain of the second MOS transistor is connected to the source of the fifth MOS transistor; the gate of the sixth MOS transistor is connected to the source of the seventh MOS transistor, the gate of the tenth MOS transistor, and the gate of the eleventh MOS transistor; the source of the tenth MOS transistor and the source of the eleventh MOS transistor are connected to the input signal Vin; the drain of the seventh MOS transistor is connected to the drain of the eighth MOS transistor and the source of the ninth MOS transistor; the drain of the eleventh MOS transistor is the output signal Vout; the source of the first MOS transistor and the drain of the ninth MOS transistor are grounded.

[0034] like Figure 3 As shown in the figure, the segmented CDAC array module includes a high-segment capacitor group, a low-segment capacitor group and a bridge capacitor; in the sampling phase, the bottom plates of the capacitors are connected to the common-mode voltage VCM; in the conversion phase, according to the feedback control signal of the SAR logic module, the bottom plates of the capacitors are switched to VDD or GND, and the high-segment capacitor group is switched first. During the conversion process, the switching of the high-segment capacitor group transfers charge to the low-segment capacitor group through the bridge capacitor, so that the charge distribution ratio between the high and low segments accurately matches the binary weight.

[0035] The high-segment capacitor group includes a first capacitor, a second capacitor, a third capacitor, a fourth capacitor, a fifth capacitor, a sixth capacitor and a seventh capacitor, wherein the seventh capacitor is a high-segment redundant capacitor, the top plates of the capacitors of the high-segment capacitor group are connected in parallel and jointly linked to the common-mode voltage VCM, and the bottom plates of each capacitor of the high-segment capacitor group are independently controlled by the signal sent by the SAR logic module; the low-segment capacitor group includes an eighth capacitor, a ninth capacitor, a tenth capacitor, an eleventh capacitor, a twelfth capacitor, a thirteenth capacitor and a fourteenth capacitor, wherein the eighth capacitor is a low-segment redundant capacitor, the top plates of the capacitors of the low-segment capacitor group are connected in parallel and jointly linked to the output voltage VOUT, and the bottom plates of each capacitor of the low-segment capacitor group are independently controlled by the signal sent by the SAR logic module.

[0036] The bridging capacitor is set between the high-segment capacitor group and the low-segment capacitor group to compensate for the difference in parasitic capacitance. During charge redistribution, it ensures that the charge transfer ratio from the high-segment capacitor group to the low-segment capacitor group accurately matches the binary weight, avoiding nonlinear errors caused by inter-segment mismatch.

[0037] like Figure 4 As shown, the dynamic comparator module includes a pre-amplifier stage and a dynamic latch stage. The pre-amplifier stage includes an input differential pair, a cascode load, and a dynamic bias unit. The input differential pair includes a twelfth MOS transistor and a thirteenth MOS transistor. The gate of the twelfth MOS transistor is connected to the input signal Vip, and the drain is connected to the drain of the fourteenth MOS transistor. The gate of the thirteenth MOS transistor is connected to the input signal Vin, and the drain is connected to the drain of the fifteenth MOS transistor. The cascode load includes the fourteenth and fifteenth MOS transistors with a common gate, and the drains are both connected to the dynamic bias unit. The dynamic bias unit includes a first bias and a second bias. The first bias includes the sixteenth and seventeenth MOS transistors, and the second bias includes the eighteenth and nineteenth MOS transistors. The gates of the sixteenth and nineteenth MOS transistors are connected to the clock signal.

[0038] The dynamic latch stage includes a cross-coupled MOS transistor and a reset switch; the cross-coupled MOS transistor includes a 20th MOS transistor and a 21st MOS transistor, the gate of the 20th MOS transistor is connected to the drain of the 12th MOS transistor, and the gate of the 21st MOS transistor is connected to the drain of the 13th MOS transistor; the reset switch includes the 22nd MOS transistor and the 23rd MOS transistor.

[0039] In the reset phase, the clock signal is 1, the sixteenth and seventeenth MOS transistors are turned on, and the pre-amplifier stage output is pulled down to GND; the twenty-second and twenty-third MOS transistors are turned on, and the output signal nodes Voutp and Voutn are reset to GND; the eighteenth and nineteenth MOS transistors are turned off, cutting off the pre-amplifier stage pull-up path, and the twentieth and twenty-first MOS transistors are pre-charged to VDD; in the evaluation phase, the clock signal is 0, the input differential signal modulates the pre-amplifier stage output, the sixteenth and seventeenth MOS transistors are turned off, and the eighteenth and nineteenth MOS transistors are turned on; the input differential signal modulates the current through the twelfth and thirteenth MOS transistors, resulting in a voltage difference at the pre-amplifier stage output node, which is transmitted to the output signal nodes Voutp and Voutn; in the regeneration phase, the clock signal remains 0, and the cross-coupled MOS transistors amplify the difference through positive feedback based on the voltage difference between the output signal nodes Voutp and Voutn.

[0040] like Figure 5 As shown, the SAR logic module includes a clock control module, a dynamic latch, and a drive circuit. Based on event-driven dynamic logic control, it outputs a 12-bit digital code and simultaneously feeds back a control signal to the segmented CDAC array module to adjust the capacitor switching strategy. The clock control module controls the non-overlapping clock signal to obtain the pre-charge phase, latch phase, and switching phase, and drives the switching of each capacitor in the segmented CDAC array module. The dynamic latch includes a cross-coupled inverter and a reset switch, which are cross-connected to form a positive feedback loop through the cross-coupled inverters. The drive circuit generates the segmented CDAC array module control signal D.

[0041] In the pre-charge phase, the clock signal is 1, Pi and Ni are charged to a high level through VDD, Outp and Outn are reset to GND, and the Valid signal is set low; in the latch phase, the logic path is cut off, the result of the dynamic comparator module is stored in the dynamic latch, and the differential signals Pi and Ni output by the dynamic comparator are transmitted to the dynamic node. The cross-coupled inverter quickly adjusts the output signals Outp and Outn according to the voltage difference between Pi and Ni; in the switching phase, the levels of the output signals Outp and Outn are transmitted to the D signal line to generate specific segmented CDAC array module control signals.

[0042] Using the analog-to-digital conversion system in this embodiment, at a sampling rate of 320 kS / s, the output spectrum is as follows: Figure 6 As shown, the signal-to-noise-distortion ratio is 81.94dB and the spurious-free dynamic range is 91.69dBc. The analog-to-digital conversion system in this embodiment supports ±500mV input, adapting to the electrode offset requirements of neural signals. The total power consumption is 27.9μW, which is more than 31% lower than similar designs, meeting the long-term operation requirements of implantable devices. Its core area is 0.2475mm 2 , with symmetrical layout and optimized parasitic parameters, supporting high-density integration, 10kHz bandwidth covering the AP / EEG spectrum (0.1-10kHz), and redundant bits and noise suppression adapted to low SNR environments. The performance comparison of the analog-to-digital conversion system in this embodiment and the existing technology is shown in Table 1. The system of this embodiment has an effective number of bits of 13.44 bits, with a resolution exceeding that of traditional SAR ADCs, and a core area of 0.2475mm 2 , the layout is symmetrical and the parasitic parameters are optimized, supporting high-density integration; suitable for brain-computer interface scenarios, the ±500mV input range is compatible with neural signal offset, the 10kHz bandwidth covers the AP / EEG spectrum (0.1-10kHz), and the redundant bits and noise suppression adapt to low SNR environments.

[0043] Table 1 Performance comparison

[0044]

[0045]

[0046] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in the present invention, and such modifications or substitutions are intended to be within the scope of protection of the present invention. Therefore, the scope of protection of the present invention shall be subject to the scope of protection of the claims.

Claims

1. A successive approximation register type analog-to-digital conversion system for brain-computer interface, characterized in that: include: Bootstrap sampling switch module, segmented CDAC array module, dynamic comparator module and SAR logic module; The P-end input and N-end input are respectively connected to two bootstrap sampling switch modules to form a differential signal acquisition channel. The two bootstrap sampling switch modules are symmetrically designed to suppress common-mode noise; The two bootstrap sampling switch modules are respectively connected to two segmented CDAC array modules. The segmented CDAC array module is divided into a high-segment capacitor group and a low-segment capacitor group, which are connected through a bridge capacitor, and a redundant bit is inserted in each segment. The output of the segmented CDAC array module is connected to the differential input of the dynamic comparator module, and the comparison result is output to the SAR logic module; the SAR logic module is based on event-driven dynamic logic control, outputs a 12-bit digital code, and simultaneously feeds back a control signal to the segmented CDAC array module to adjust the capacitor switching strategy.

2. The successive approximation register type analog-to-digital conversion system for brain-computer interface according to claim 1, characterized in that: The bootstrap sampling switch module includes a bootstrap capacitor and several MOS transistors. Dynamic gate bias control logic is implemented by connecting clock signals to the gates of the first MOS transistor, the gates of the third MOS transistor, the gates of the fourth MOS transistor, the gates of the eighth MOS transistor, and the gates of the ninth MOS transistor. During a reset phase, the dynamic gate bias control logic controls the charging path of the bootstrap capacitor, connecting the two ends of the bootstrap capacitor to a power supply VDD and ground, respectively. During a sampling phase, the control logic is switched to connect one end of the bootstrap capacitor to the input signal Vin and the other end of the bootstrap capacitor to the gate of the first MOS transistor, so that the gate voltage of the first MOS transistor is constant at VDD.

3. The successive approximation register type analog-to-digital conversion system for brain-computer interface according to claim 2, characterized in that: The specific connection method of the bootstrap sampling switch module includes: the source of the second MOS tube, the source of the third MOS tube, the gate of the seventh MOS tube and the source of the eighth MOS tube are connected to VDD; the gate of the first MOS tube, the gate of the third MOS tube, the gate of the fourth MOS tube, the gate of the eighth MOS tube and the gate of the ninth MOS tube are connected to the clock signal; the gate of the second MOS tube is connected to the drain of the fifth MOS tube and the source of the seventh MOS tube; the drain of the third MOS tube is connected to the source of the fourth MOS tube, the gate of the fifth MOS tube and the drain of the sixth MOS tube; The sources of the four MOS transistors are connected to the source of the sixth MOS transistor and the drain of the tenth MOS transistor; the drain of the second MOS transistor is connected to the source of the fifth MOS transistor; the gate of the sixth MOS transistor is connected to the source of the seventh MOS transistor, the gate of the tenth MOS transistor, and the gate of the eleventh MOS transistor; the source of the tenth MOS transistor and the source of the eleventh MOS transistor are connected to the input signal Vin; the drain of the seventh MOS transistor is connected to the drain of the eighth MOS transistor and the source of the ninth MOS transistor; the drain of the eleventh MOS transistor is the output signal Vout; the source of the first MOS transistor and the drain of the ninth MOS transistor are grounded.

4. The successive approximation register type analog-to-digital conversion system for brain-computer interface according to claim 1, characterized in that: The segmented CDAC array module includes a high-segment capacitor group, a low-segment capacitor group, and a bridge capacitor. During the sampling phase, the bottom plates of the capacitors are connected to the common-mode voltage VCM. During the conversion phase, the bottom plates of the capacitors are switched to VDD or GND according to the feedback control signal of the SAR logic module, with the high-segment capacitor group being switched first. During the conversion process, the switching of the high-segment capacitor group transfers charge to the low-segment capacitor group through the bridge capacitor, so that the charge distribution ratio between the high and low segments accurately matches the binary weight.

5. The successive approximation register type analog-to-digital conversion system for brain-computer interface according to claim 4, characterized in that: The high-segment capacitor group includes a first capacitor, a second capacitor, a third capacitor, a fourth capacitor, a fifth capacitor, a sixth capacitor and a seventh capacitor, wherein the seventh capacitor is a high-segment redundant capacitor, the top plates of the capacitors of the high-segment capacitor group are connected in parallel and jointly linked to the common-mode voltage VCM, and the bottom plates of the capacitors of the high-segment capacitor group are independently controlled by signals sent by the SAR logic module; the low-segment capacitor group includes an eighth capacitor, a ninth capacitor, a tenth capacitor, an eleventh capacitor, a twelfth capacitor, a thirteenth capacitor and a fourteenth capacitor, wherein the eighth capacitor is a low-segment redundant capacitor, the top plates of the capacitors of the low-segment capacitor group are connected in parallel and jointly linked to the output voltage VOUT, and the bottom plates of the capacitors of the low-segment capacitor group are independently controlled by signals sent by the SAR logic module.

6. The successive approximation register type analog-to-digital conversion system for brain-computer interface according to claim 4, characterized in that: The bridging capacitor is arranged between the high-segment capacitor group and the low-segment capacitor group to compensate for the difference in parasitic capacitance. When redistributing charge, it ensures that the charge transfer ratio from the high-segment capacitor group to the low-segment capacitor group accurately matches the binary weight, thereby avoiding nonlinear errors caused by inter-segment mismatch.

7. The successive approximation register type analog-to-digital conversion system for brain-computer interface according to claim 1, characterized in that: The dynamic comparator module includes a pre-amplification stage and a dynamic latch stage; The pre-amplifier stage includes an input differential pair, a cascode load, and a dynamic bias unit; the input differential pair includes a twelfth MOS transistor and a thirteenth MOS transistor, the gate of the twelfth MOS transistor is connected to the input signal Vip, and the drain is connected to the drain of the fourteenth MOS transistor, the gate of the thirteenth MOS transistor is connected to the input signal Vin, and the drain is connected to the drain of the fifteenth MOS transistor; the cascode load includes a fourteenth MOS transistor and a fifteenth MOS transistor with a common gate, and the drains are both connected to the dynamic bias unit; the dynamic bias unit includes a first bias and a second bias, the first bias includes the sixteenth MOS transistor and the seventeenth MOS transistor, the second bias includes the eighteenth MOS transistor and the nineteenth MOS transistor, and the gates of the sixteenth MOS transistor and the nineteenth MOS transistor are connected to the clock signal; The dynamic latch stage includes a cross-coupled MOS transistor and a reset switch; the cross-coupled MOS transistor includes a 20th MOS transistor and a 21st MOS transistor, the gate of the 20th MOS transistor is connected to the drain of the 12th MOS transistor, and the gate of the 21st MOS transistor is connected to the drain of the 13th MOS transistor; the reset switch includes a 22nd MOS transistor and a 23rd MOS transistor.

8. The successive approximation register type analog-to-digital conversion system for brain-computer interface according to claim 7, characterized in that: In the reset phase, the clock signal is 1, the sixteenth and seventeenth MOS transistors are turned on, and the pre-amplifier stage output is pulled down to GND; the twenty-second and twenty-third MOS transistors are turned on, and the output signal nodes Voutp and Voutn are reset to GND; the eighteenth and nineteenth MOS transistors are turned off, cutting off the pre-amplifier stage pull-up path, and the twentieth and twenty-first MOS transistors are pre-charged to VDD; in the evaluation phase, the clock signal is 0, the input differential signal modulates the pre-amplifier stage output, the sixteenth and seventeenth MOS transistors are turned off, and the eighteenth and nineteenth MOS transistors are turned on; the input differential signal modulates the current through the twelfth and thirteenth MOS transistors, resulting in a voltage difference at the output node of the pre-amplifier stage, and the voltage difference is transmitted to the output signal nodes Voutp and Voutn; In the regeneration phase, the clock signal remains at 0, and the cross-coupled MOS transistor amplifies the voltage difference between the output signal nodes Voutp and Voutn through positive feedback.

9. The successive approximation register type analog-to-digital conversion system for brain-computer interface according to claim 1, characterized in that: The SAR logic module includes a clock control module, a dynamic latch, and a drive circuit. Based on event-driven dynamic logic control, it outputs a 12-bit digital code and simultaneously feeds back a control signal to the segmented CDAC array module to adjust the capacitor switching strategy. The clock control module controls non-overlapping clock signals to obtain a precharge phase, a latch phase, and a switching phase, and drives the switching of each capacitor in the segmented CDAC array module. The dynamic latch includes a cross-coupled inverter and a reset switch, which are cross-connected to form a positive feedback loop through the cross-coupled inverters. The drive circuit generates a control signal D for the segmented CDAC array module.

10. The successive approximation register type analog-to-digital conversion system for brain-computer interface according to claim 9, characterized in that: In the pre-charge phase, the clock signal is 1, Pi and Ni are charged to a high level through VDD, Outp and Outn are reset to GND, and the Valid signal is set low; in the latch phase, the logic path is cut off, the result of the dynamic comparator module is stored in the dynamic latch, and the differential signals Pi and Ni output by the dynamic comparator are transmitted to the dynamic node. The cross-coupled inverter quickly adjusts the output signals Outp and Outn according to the voltage difference between Pi and Ni; in the switching phase, the levels of the output signals Outp and Outn are transmitted to the D signal line to generate specific segmented CDAC array module control signals.

Images