A high-speed and high-reliability CAN communication to fiber-optic communication system

Abstract

The present invention relates to the technical field of communication transmission, and discloses a high-speed and high-reliability CAN communication to optical fiber communication system. The system comprises: a communication processor comprising a communication unit and a power supply unit, the communication unit and the power supply unit being connected, the power supply unit being used to power the communication unit, the communication unit comprising an FPGA module, an optical fiber interface module, and a CAN interface module, the FPGA module sampling in parallel, and embedding clock information into a data frame based on Manchester encoding and 8B10B encoding, the optical fiber interface module of each communication processor being connected to the optical fiber interface module of a communication processor by optical fiber point-to-point, optical fiber cascade, or optical fiber ring network, the optical fiber interface module comprising a Fiber1 interface and a Fiber2 interface, and the present invention ensures the stability and reliability of communication transmission through the FPGA module, the optical fiber interface module, and the CAN interface module.

Description

Technical Field

[0001] The present invention relates to the field of communication transmission technology, and in particular to a high-speed and high-reliability CAN communication to optical fiber communication system. Background Art

[0002] In modern industrial automation, intelligent transportation, automotive electronics and other fields, the Controller Area Network (CAN) bus has become an important way of data communication between devices due to its advantages such as real-time performance, anti-interference ability, and multi-master communication.

[0003] However, CAN communication has significant limitations in practical applications. First, due to the electrical characteristics of the physical layer, CAN bus communication cannot meet the needs of long-distance data transmission, restricting the construction and deployment of large-scale distributed systems such as industrial monitoring and smart grids. Second, in complex electromagnetic environments, such as industrial production workshops and substations, electromagnetic interference generated by numerous electrical devices can affect the transmission quality of CAN signals, leading to data loss and increased bit error rates, resulting in communication interruptions and reduced reliability and stability of the communication system. Third, Chinese Patent Publication No. CN110034987A discloses an FPGA-based CAN communication controller. Its main technical features are: it includes an interface management logic module, an object layer module, and a transport layer module, which are encapsulated in the FPGA. The interface management logic module, object layer module, and transport layer module are sequentially connected. The interface management logic module is externally connected to a microcontroller, and the transport layer module is externally connected to CAN devices and CAN clock signals. Therefore, FPGAs do not address parallel processing or how to ensure the synchronization of clock and data signals.

[0004] Therefore, it is necessary to design a high-speed and high-reliability CAN communication to fiber optic communication system to solve the problems existing in current technology. Summary of the Invention

[0005] In view of this, the present invention proposes a high-speed and high-reliability CAN communication to fiber-optic communication system, which aims to solve the problem that CAN bus communication cannot meet the long-distance data transmission requirements, electromagnetic interference will affect the transmission quality of CAN signals, resulting in data packet loss and increased bit error rate, thereby causing communication interruption, reducing the reliability and stability of the communication system, and how to ensure the synchronization relationship between clock signals and data signals.

[0006] The present invention proposes a high-speed and high-reliability CAN communication to optical fiber communication system, comprising:

[0007] a plurality of communication processors, each of the communication processors being connected to a communication processor, the communication processors comprising a communication unit and a power supply unit, the communication unit being connected to the power supply unit, the power supply unit being used to supply power to the communication unit;

[0008] The communication unit includes an FPGA module, an optical fiber interface module and a CAN interface module;

[0009] The FPGA module is used to control the conversion between CAN signals and optical fiber signals, link management and data transmission. The FPGA module performs parallel sampling and embeds clock information into the data frame based on Manchester encoding and 8B10B encoding.

[0010] The optical fiber interface module is connected to the FPGA module, and the optical fiber interface module of each communication processor is connected to the optical fiber interface module of a communication processor using optical fiber point-to-point, optical fiber cascade, or optical fiber ring network. The optical fiber interface module includes a Fiber1 interface and a Fiber2 interface, and each of the Fiber1 interface and the Fiber2 interface includes an optical fiber output end TX and an optical fiber input end RX;

[0011] The CAN interface module is connected to the FPGA module, and the CAN interface module includes a CAN1 interface and a CAN2 interface. The CAN1 interface and the CAN2 interface are used to isolate data mapping and control logic. The CAN1 interface and the CAN2 interface are each provided with an L interface, an H interface and a G interface. The L interface and the H interface are used to connect the signal line, and the G interface is used for grounding.

[0012] Furthermore, the power supply unit includes:

[0013] V- interface, V+ interface and Earth interface;

[0014] Two V-interfaces are provided, and the V-interfaces are used to connect to the negative pole of the direct power supply;

[0015] Two V+ interfaces are provided, and the V+ interfaces are used to connect to the positive electrode of the direct power supply;

[0016] One Earth interface is provided, and the Earth interface is used for grounding.

[0017] Furthermore, the communication unit also includes an RS232 module;

[0018] The RS232 module is connected to the FPGA module, and is used to connect to a serial port debugging tool and send configuration commands or read the working status of the communication processor.

[0019] Furthermore, the communication unit also includes an indicator light module;

[0020] The indicator light module is connected to the FPGA module, and is used to indicate the working status of the FPGA module, the optical fiber interface module, the CAN interface module and the power supply unit.

[0021] Furthermore, when the optical fiber interface module of each communication processor is connected to the optical fiber interface module of a communication processor using optical fiber point-to-point, optical fiber cascade, or optical fiber ring network, the method includes:

[0022] The optical fiber interface module of each communication processor is cross-connected with the optical fiber interface module of a communication processor using optical fibers;

[0023] When the optical fiber interface module of each communication processor is connected to the optical fiber interface module of a communication processor using an optical fiber ring network, the optical fiber output end TX of the Fiber1 interface of each communication processor is connected to the optical fiber input end RX of the Fiber2 interface of a communication processor, and the optical fiber input end RX of the Fiber1 interface of each communication processor is connected to the optical fiber output end TX of the Fiber2 interface of a communication processor.

[0024] Furthermore, in the high-speed and high-reliability CAN communication to fiber-optic communication system, the communication unit sets a dual-ring self-healing algorithm and performs initialization when powered on. The Fiber1 interface sends a network traversal command, the Fiber2 interface receives network status information, and determines the master devices of several communication processors, and the master device controls the communication link of the entire network.

[0025] Furthermore, when determining the master devices of several communication processors and the master devices controlling the communication links of the entire network, the process includes:

[0026] There is one master device, and the remaining communication processors are recorded as sub-devices;

[0027] The master device periodically sends a network status command, and the slave device is used to obtain the network status information of all devices on the network and determine the control status of the master device according to the link status of the communication link of the entire network.

[0028] Furthermore, when determining the control state of the master device according to the link state of the whole network communication link, it includes:

[0029] If the link status of the whole network communication link is abnormal, the master device will re-control the sending and receiving status of each interface module of each sub-device;

[0030] If the main device is offline, each sub-device restarts the initialization.

[0031] Furthermore, when the FPGA module performs parallel sampling, the method includes:

[0032] The FPGA module acquires 8 groups of parallel CAN signals, and the sampling moments of the parallel CAN signals differ by 1 / 8 bit time.

[0033] Furthermore, when clock information is embedded into a data frame based on Manchester encoding and 8B10B encoding, the following steps are included:

[0034] The FPGA module superimposes clock information on data bits based on Manchester encoding and 8B10B encoding and sends the data bits. The receiving end is used to receive the data signal with the clock information superimposed on the data bits and recover the clock signal.

[0035] Compared with the prior art, the present invention has the following advantages: it realizes remote transmission of CAN communication signals through the optical fiber interface module, effectively extending the CAN communication distance and realizing optical fiber transmission of CAN signals, thereby extending the communication distance; and optical fiber is not affected by electromagnetic waves, ensuring stable data transmission in complex environments, avoiding bit errors or communication interruptions caused by interference on the CAN bus, thereby improving the overall reliability and data integrity of the communication system; the FPGA module can realize conversion between CAN signals and optical fiber signals and has parallel sampling capability, effectively improving the efficiency of data communication transmission; at the same time, the FPGA module adopts Manchester encoding and 8B10B encoding to embed clock information into the data frame, and can achieve data and clock synchronization recovery at the receiving end, ensuring the real-time and accuracy of data communication transmission, and avoiding the risk of data misalignment and packet loss caused by clock asynchrony. The optical fiber interface module supports flexible networking modes such as point-to-point, cascade, and ring network, which can meet both simple two-point connections and build complex distributed communication systems, realizing communication fault tolerance, link backup, and rapid recovery of the link, and improving the flexibility and stability of the system. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Various other advantages and benefits will become apparent to those skilled in the art upon reading the detailed description of the preferred embodiment below. The accompanying drawings are for illustration purposes only and are not to be considered as limiting the present invention. The same reference symbols are used throughout the drawings to represent the same components. In the drawings:

[0037] Figure 1 A structural block diagram of a high-speed and high-reliability CAN communication to optical fiber communication system provided by an embodiment of the present invention;

[0038] Figure 2 A schematic diagram of a communication processor provided by an embodiment of the present invention;

[0039] Figure 3Schematic diagram of the interface between the optical fiber interface module and the CAN interface module of the communication processor provided in an embodiment of the present invention;

[0040] Figure 4 This is a schematic diagram of the interface between the power supply unit and the RS232 module provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0041] Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although exemplary embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the embodiments set forth herein. On the contrary, these embodiments are provided to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art. It should be noted that, unless there is a conflict, the embodiments of the present disclosure and the features in the embodiments can be combined with each other. The present invention will be described in detail below with reference to the accompanying drawings and in conjunction with the embodiments.

[0042] In some embodiments of the present application, see Figure 1-4 As shown, a high-speed and high-reliability CAN communication to optical fiber communication system includes: a plurality of communication processors, each communication processor is connected to a communication processor, the communication processor includes a communication unit and a power supply unit, the communication unit and the power supply unit are connected, the power supply unit is used to power the communication unit, the communication unit includes an FPGA module, an optical fiber interface module and a CAN interface module, the FPGA module is used to control the conversion between CAN signals and optical fiber signals, link management and data transmission, the FPGA module is sampled in parallel, and the clock information is embedded in the data frame based on Manchester encoding and 8B10B encoding, the optical fiber interface module is connected to the FPGA module, and each communication processor The optical fiber interface module of the device is connected to the optical fiber interface module of a communication processor using optical fiber point-to-point or optical fiber cascade or optical fiber ring network. The optical fiber interface module includes a Fiber1 interface and a Fiber2 interface. The Fiber1 interface and the Fiber2 interface each include an optical fiber output end TX and an optical fiber input end RX. The CAN interface module is connected to the FPGA module. The CAN interface module includes a CAN1 interface and a CAN2 interface. The CAN1 interface and the CAN2 interface are used for data mapping and control logic isolation. The CAN1 interface and the CAN2 interface are each provided with an L interface, an H interface and a G interface. The L interface and the H interface are used to connect the signal line, and the G interface is used for grounding.

[0043] Specifically, the system consists of several communication processors, each of which integrates a communication unit and a power supply unit. It can be adjusted according to the actual communication length during application. The communication processor uses two electrically isolated CAN channels, factory-configured terminal resistors and four fiber channels to support fiber point-to-point, fiber cascade and fiber ring network structures. It is suitable for 50 / 125um, 62.5 / 125um and 200um multimode optical fibers, and comes standard with an ST dual-fiber interface. The CAN baud rate is 5K~1Mbps, in compliance with CAN2.0A and CAN2.0B specifications and ISO11898 standards, and the operating temperature is -40℃~+85℃. Humidity: ≤95%, the required power supply voltage is DC24V, the input voltage fluctuation range is allowed: DC9V~36V, MTBF is greater than 260000h, and each communication processor includes a communication unit and a power supply unit. The communication unit is the core of the entire data processing and conversion, including FPGA module, optical fiber interface module and CAN interface module. The FPGA module is responsible for the real-time conversion between CAN signals and optical fiber signals, and performs link management and data transmission control. The parallel processing architecture inside the FPGA module can process multiple CAN signal channels at the same time, realize high-speed data forwarding and error checking, and improve transmission efficiency. The FPGA module is based on the self-timer. The clock encoding method ensures that the receiving end (referring to another communication processor communicating with this communication processor) can extract the clock signal from the data stream, thereby effectively recovering the clock signal, thereby ensuring the synchronization relationship between the clock signal and the data signal, improving transmission synchronization and anti-interference ability. The CAN interface module realizes the acquisition and output of CAN signals, and performs logical isolation and data mapping through the CAN1 and CAN2 interfaces to enhance security and redundancy. The power supply unit provides a stable power supply for the communication unit to ensure the operation of the entire system. The optical fiber interface module has two groups of interfaces, Fiber1 and Fiber2, which respectively include the optical fiber output terminal TX and the optical fiber input terminal R X, to support bidirectional data transmission and reception, to support fiber optic point-to-point, fiber optic cascade and fiber optic ring network structures, and thus adapt to the needs of various industrial deployments. During data transmission, the external CAN device transmits data to the FPGA module through the CAN interface module. The FPGA module uses parallel sampling to receive CAN signals, then verifies the data frame, and performs Manchester encoding and 8B10B encoding on the data frame, embeds the clock information into it, and sends the encoded data to the remote communication processor through the fiber optic interface module. The remote communication processor performs data decoding and synchronization through its FPGA module, thereby realizing the complete CAN communication cross-fiber relay process.

[0044] It is understandable that the traditional CAN bus is limited by its electrical characteristics, and CAN bus communication cannot meet the needs of long-distance data transmission. By converting CAN electrical signals into optical signals and then restoring the optical signals to CAN electrical signals, remote transmission of CAN communication signals is achieved, effectively extending the CAN communication distance, and effectively reducing the impact of environmental electromagnetic interference on CAN signal transmission, thereby improving the stability and anti-interference performance of the communication link. The optical fiber interface module supports flexible networking methods such as point-to-point, cascade, and ring networks, which can meet both simple two-point connections and build complex distributed communication systems, achieving link communication fault tolerance, link backup, and rapid recovery. The dual CAN interfaces (CAN1 and CAN2) and the independent data mapping logic of the FPGA module achieve logical isolation, preventing the failure of a single communication processor from affecting the overall network, thereby improving the stability and reliability of communication.

[0045] In some embodiments of the present application, the power supply unit includes: a V-interface, a V+ interface and an Earth interface, two V-interfaces are set, and the V-interface is used to connect to the negative pole of the direct power supply; two V+ interfaces are set, and the V+ interface is used to connect to the positive pole of the direct power supply; one Earth interface is set, and the Earth interface is used for grounding.

[0046] In some embodiments of the present application, the communication unit further includes an RS232 module, which is connected to the FPGA module. The RS232 module is used to connect to a serial port debugging tool and send configuration commands or read the working status of the communication processor.

[0047] Specifically, the power supply unit is used to connect a direct power supply to provide stable power supply for each module of the communication processor. The two V+ interfaces and two V- interfaces improve the redundancy and reliability of the power input. The Earth grounding interface is used for grounding to enhance anti-interference capability and prevent static electricity and noise from affecting the normal operation of the communication unit, ensuring the stability and reliability of the system. The RS232 module of the communication unit is connected to the FPGA module. The RS232 module can be connected to the PC or serial debugging tool through the serial port to send configuration commands or read the operating status of the communication processor. The RS232 module uses the RS232 protocol to provide stable, low-speed and reliable asynchronous serial communication, allowing users to modify the configuration parameters of the internal logic of the FPGA module (such as encoding mode, etc.) in real time. On the other hand, the RS232 module supports debugging and operation and maintenance operations, which facilitates troubleshooting, status monitoring and remote maintenance, and improves the adaptability and operation and maintenance efficiency of the system.

[0048] In some embodiments of the present application, the communication unit also includes an indicator light module, which is connected to the FPGA module and is used to indicate the working status of the FPGA module, the optical fiber interface module, the CAN interface module and the power supply unit.

[0049] Specifically, the indicator light module includes the ACT (FiBer1 interface status light) and FAU (FiBer1 interface fault light) on FiBer1, the ACT (FiBer2 interface status light) and FAU (FiBer2 interface fault light) on FiBer2, the CAN1 (CAN1 interface status light), the CAN2 (CAN2 interface status light), the SYS (system status light), and the PWR (power supply unit status light). When the ACT light on FiBer1 is solid green, the channel connection on FiBer1 is normal. A blinking green light indicates data is being sent or received. The FAU light on FiBer1 is off by default. When the FAU light on FiBer1 flashes red, a communication fault has occurred on the FiBer1 interface. When the ACT light on FiBer2 is solid green, the channel connection on FiBer2 is normal. A blinking green light indicates data is being sent or received. The FAU light on FiBer2 is off by default. A blinking red light indicates a communication fault has occurred on the FiBer2 interface. When the CAN1 light is solid green, the CAN1 channel is initialized normally. When the CAN1 light flashes green, data is being sent or received on the CAN1 channel. When the CAN2 light is solid green, the CAN2 channel is initialized normally. When the CAN2 light flashes green, data is being sent or received on the CAN2 channel. When the SYS light flashes green, the system is operating normally. When the SYS light is off, the system is not operating. When the PWR light is solid red, the power supply is normal; otherwise, the power supply is abnormal. By observing the on / off and flashing status of each light, you can quickly determine the operating status of each module, shortening troubleshooting time, improving system maintenance efficiency, reducing maintenance costs, and ensuring communication stability and reliability.

[0050] In some embodiments of the present application, when the fiber optic interface module of each communication processor is connected to the fiber optic interface module of a communication processor using fiber optic point-to-point, fiber optic cascade, or fiber optic ring network, it includes: the fiber optic interface module of each communication processor is connected to the fiber optic interface module of a communication processor using fiber optic cross-connection; when the fiber optic interface module of each communication processor is connected to the fiber optic interface module of a communication processor using fiber optic ring network, the fiber optic output end TX of the Fiber1 interface of each communication processor is connected to the fiber optic input end RX of the Fiber2 interface of a communication processor, and the fiber optic input end RX of the Fiber1 interface of each communication processor is connected to the fiber optic output end TX of the Fiber2 interface of a communication processor.

[0051] Specifically, the fiber optic interface module of each communication processor is cross-connected to the fiber optic interface module of another communication processor using optical fiber. When the fiber optic interface module of a communication processor is connected to the fiber optic interface module of another communication processor using optical fiber point-to-point connection, indicating the presence of two communication processors, the optical fiber output terminal TX of the Fiber1 interface of one communication processor is connected to the optical fiber input terminal RX of the Fiber2 interface of the other communication processor, and the optical fiber input terminal RX of the Fiber1 interface of one communication processor is connected to the optical fiber output terminal TX of the Fiber2 interface of the other communication processor. When the optical fiber interface module of a communication processor is connected to the optical fiber interface module of another communication processor by optical fiber cascade connection, it means that there are at least two communication processors. Then, the optical fiber output end TX of the Fiber2 interface of the first communication processor (indicating the starting point of the connection) is connected to the optical fiber input end RX of the Fiber1 interface of the next communication processor (the second communication processor), and the optical fiber input end RX of the Fiber2 interface of the first communication processor is connected to the optical fiber output end TX of the Fiber1 interface of the next communication processor, and the Fiber2 interface of the second communication processor is connected to the Fiber1 interface of the next communication processor, and so on. When the last communication processor (indicating the end point of the connection) is connected, the Fiber1 interface of the first communication processor and the Fiber1 interface of the last communication processor are connected. The Fiber2 interface of the communication processor is not connected, and when the fiber optic interface module of the communication processor is connected to the fiber optic interface module of another communication processor using a fiber optic ring network, the fiber optic output end TX of the Fiber1 interface of each communication processor is connected to the fiber optic input end RX of the Fiber2 interface of a communication processor, the fiber optic input end RX of the Fiber1 interface of each communication processor is connected to the fiber optic output end TX of the Fiber2 interface of a communication processor, the Fiber1 interface of the first communication processor is connected to the Fiber2 interface of the last communication processor, thereby forming a ring network structure, and the fiber optic interface module of each communication processor is connected to the fiber optic interface module of a communication processor using fiber optic point-to-point or fiber optic cascade or fiber optic ring network, which ensures the reliability and stability of the communication system.

[0052] In some embodiments of the present application, the communication unit sets a dual-ring self-healing algorithm and performs initialization when powered on. The Fiber1 interface sends a network traversal command, the Fiber2 interface receives network status information, and determines the master device of several communication processors, and the master device controls the communication link of the entire network.

[0053] In some embodiments of the present application, when the master device of several communication processors is determined and the master device controls the communication link of the entire network, it includes: there is one master device, and the remaining communication processors are recorded as sub-devices. The master device periodically sends network status commands, and the sub-devices are used to obtain network status information of all devices on the network, and determine the control status of the master device according to the link status of the communication link of the entire network.

[0054] In some embodiments of the present application, when determining the control state of the main device based on the link state of the entire network communication link, it includes: if there is an abnormality in the link state of the entire network communication link, the main device re-controls the receiving and sending state of each interface module of each sub-device; if the main device is offline, each sub-device restarts and initializes.

[0055] Specifically, the communication unit of the communication processor is equipped with two fiber optic interfaces (Fiber1 and Fiber2), which have a fiber optic output end TX and a fiber optic input end RX respectively. When the system is powered on, the Fiber1 interface actively sends a network traversal command and broadcasts the network initialization information to other communication processors in the network. At the same time, the Fiber2 interface receives status information from other communication processors to form the reverse link of the network loop, thereby realizing bidirectional link management. During the initialization phase, the communication unit will determine a communication processor as the master device (Master) and the remaining communication processors as slave devices (Slave) based on rules such as link response delay, device number and priority. The master device is responsible for scheduling and monitoring the entire network link and periodically sends network status commands through the Fiber interface. After receiving the command, the slave device uploads its own status information (such as whether the link is interrupted, CAN module status, FPGA abnormal status, etc.). The master device determines whether the communication link of the entire network is normal based on the link information reported by the slave device. If there is an abnormality in the link status of the communication link of the entire network (the connection is interrupted or disconnected somewhere), the master device will re-issue the control command to dynamically configure the transmit and receive status of each interface module of each slave device, thereby reconstructing The communication path is used to ensure uninterrupted communication of the entire network. If the main device itself is offline or the communication fails, the restart initialization of the sub-device is triggered to ensure the management capability of the network. Through the dual-loop self-healing algorithm, when any single-point link or communication processor fails, the system can quickly switch to the backup path, improving the system's fault tolerance and data transmission continuity. The main device has network status perception and link regulation functions, and can actively monitor the communication status of the entire network. It automatically intervenes and adjusts the link topology when anomalies occur, avoiding the problem of "dumb devices" in traditional CAN bus communications being difficult to respond to network anomalies, improving the stability and dynamic adaptability of the network, thereby achieving high-speed, high-reliability and intelligent adaptive communication, and meeting the security, stability and maintainability requirements of modern industrial communication systems.

[0056] In some embodiments of the present application, when the FPGA module performs parallel sampling, it includes: the FPGA module obtains 8 groups of parallel CAN signals, and the sampling moments of the parallel CAN signals differ by 1 / 8 bit time.

[0057] In some embodiments of the present application, when clock information is embedded in a data frame based on Manchester encoding and 8B10B encoding, it includes: the FPGA module superimposes the clock information on the data bit based on Manchester encoding and 8B10B encoding and sends it, and the receiving end is used to receive the data signal with the clock information superimposed on the data bit and recover the clock signal.

[0058] Specifically, traditional CAN signal sampling is limited to serial sampling, which can easily lead to misjudgment during high-speed communication or when there is signal edge jitter. The FPGA module, however, synchronously receives eight parallel CAN signals from the CAN interface module. The sampling instant of each CAN signal is delayed by 1 / 8 of a bit time relative to the previous signal, creating time interpolation. Through time-interleaved sampling, the FPGA module accurately acquires multiple sampling points within a data bit period, selecting the optimal waveform edge or midpoint for subsequent stable decoding. A data bit refers to the digital data output from the CAN bus or within the FPGA module, representing the raw CAN message data bits or the digital information stream to be transmitted over an optical fiber link. The receiving end represents the receiving communications processor when transmitting data to this communications processor. CAN signals are originally non-return-to-zero (NRZ) coded and do not contain explicit clock information. Direct transmission over optical fiber can cause clock drift at the receiving end due to a lack of synchronization, making accurate data recovery difficult. Therefore, the FPGA module performs double encoding before sending the signal. Manchester encoding converts each bit of data (0 or 1) into a two-level signal with an intermediate flip, that is, "0" becomes "10" and "1" becomes "01". This ensures that there is a level jump in each bit period, which facilitates the receiving end to perform bit synchronization based on the jump point. 8B10B encoding converts 8 bits of original data into 10 bits of transmission code, while achieving DC balance (DC balance) and sufficient code word jump frequency, further improving the stability of clock recovery. The encoded data stream is transmitted to the optical interface module of the remote communication processor through the optical interface module, and then the embedded data and synchronization clock are extracted through the decoding logic of the FPGA module to achieve synchronous restoration.

[0059] As can be understood, the interleaving of eight parallel sampling groups with a 1 / 8-bit time difference enables the FPGA module to observe signals from multiple time-domain perspectives during high-speed signal sampling, improving fault tolerance and effectively addressing issues such as edge jitter and waveform distortion in CAN signals. This reduces the sampling bit error rate (BER) and enhances the stability of the communication system. The combination of Manchester encoding and 8B10B encoding embeds clock information within the data frame, enabling non-return-to-zero signals in optical fiber links, which typically cannot carry clocks, to be correctly restored at the receiving end. This ensures that clock and data remain synchronized over long distances, preventing frame loss and errors caused by clock drift in CAN. 8B10B encoding exhibits excellent DC balance, resulting in a stable average level of the encoded bit stream. It also reduces low-frequency noise and inter-symbol interference (ISI) during transmission. The combined effect of 8B10B and Manchester encoding ensures reliable communication despite electromagnetic interference or optical link degradation, ensuring the synchronization of clock and data signals.

[0060] In summary, the beneficial effects of the present invention are: communication through the optical fiber interface module realizes the remote transmission of CAN communication signals, effectively extending the CAN communication distance, realizing the optical fiber transmission of CAN signals, thereby extending the communication distance, and the optical fiber is not affected by electromagnetic waves, ensuring the stable transmission of data in complex environments, avoiding the interference of the CAN bus causing errors or communication interruptions, thereby improving the overall reliability and data integrity of the communication system, the FPGA module can realize the conversion between CAN signals and optical fiber signals, and has parallel sampling capabilities, effectively improving the efficiency of data communication transmission, at the same time, the FPGA module adopts Manchester encoding and 8B10B encoding to embed clock information into the data frame, and can realize data and clock synchronization recovery at the receiving end, ensuring the real-time and accuracy of data communication transmission, avoiding the risk of data misalignment and packet loss caused by clock asynchrony. The optical fiber interface module supports flexible networking modes of point-to-point, cascade and ring network, which can meet both simple two-point connections and build complex distributed communication systems, realize link communication fault tolerance, link backup and rapid recovery, and improve the flexibility and stability of the system.

[0061] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, systems, or computer program products. Therefore, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment combining software and hardware. Furthermore, the present application may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to magnetic disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0062] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems) and computer program products according to the embodiments of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 a process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0063] These computer program instructions may also be stored in a computer readable memory that can direct a computer or other programmable data processing device to work in a specific manner, so that the instructions stored in the computer readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 a process or multiple processes and / or boxes Figure 1 The function specified in one or more boxes.

[0064] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operational steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing the instructions executed on the computer or other programmable device for implementing the process. Figure 1 a process or multiple processes and / or boxes Figure 1 A step that specifies a function in one or more boxes.

[0065] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and not to limit it. Although the present invention has been described in detail with reference to the above embodiments, ordinary technicians in the field should understand that the specific implementation methods of the present invention can still be modified or replaced by equivalents. Any modification or equivalent replacement that does not depart from the spirit and scope of the present invention should be covered by the scope of protection of the claims of the present invention.

Claims

1. A high-speed and high-reliability CAN communication to optical fiber communication system, characterized in that: include: a plurality of communication processors, each of the communication processors being connected to a communication processor, the communication processors comprising a communication unit and a power supply unit, the communication unit being connected to the power supply unit, the power supply unit being used to supply power to the communication unit; The communication unit includes an FPGA module, an optical fiber interface module and a CAN interface module; The FPGA module is used to control the conversion between CAN signals and optical fiber signals, link management and data transmission. The FPGA module performs parallel sampling and embeds clock information into the data frame based on Manchester encoding and 8B10B encoding. The optical fiber interface module is connected to the FPGA module, and the optical fiber interface module of each communication processor is connected to the optical fiber interface module of a communication processor using optical fiber point-to-point, optical fiber cascade, or optical fiber ring network. The optical fiber interface module includes a Fiber1 interface and a Fiber2 interface, and each of the Fiber1 interface and the Fiber2 interface includes an optical fiber output end TX and an optical fiber input end RX; The CAN interface module is connected to the FPGA module, and the CAN interface module includes a CAN1 interface and a CAN2 interface. The CAN1 interface and the CAN2 interface are used to isolate data mapping and control logic. The CAN1 interface and the CAN2 interface are each provided with an L interface, an H interface and a G interface. The L interface and the H interface are used to connect the signal line, and the G interface is used for grounding.

2. The high-speed and high-reliability CAN communication to optical fiber communication system according to claim 1, characterized in that: The power supply unit comprises: V- interface, V+ interface and Earth interface; Two V-interfaces are provided, and the V-interfaces are used to connect to the negative pole of the direct power supply; Two V+ interfaces are provided, and the V+ interfaces are used to connect to the positive electrode of the direct power supply; One Earth interface is provided, and the Earth interface is used for grounding.

3. The high-speed and high-reliability CAN communication to optical fiber communication system according to claim 2, characterized in that: The communication unit also includes an RS232 module; The RS232 module is connected to the FPGA module, and is used to connect to a serial port debugging tool and send configuration commands or read the working status of the communication processor.

4. The high-speed and high-reliability CAN communication to optical fiber communication system according to claim 3, characterized in that: The communication unit also includes an indicator light module; The indicator light module is connected to the FPGA module, and is used to indicate the working status of the FPGA module, the optical fiber interface module, the CAN interface module and the power supply unit.

5. The high-speed and high-reliability CAN communication to optical fiber communication system according to claim 4, characterized in that: When the optical fiber interface module of each communication processor is connected to the optical fiber interface module of a communication processor by using optical fiber point-to-point, optical fiber cascade, or optical fiber ring network, the method includes: The optical fiber interface module of each communication processor is cross-connected with the optical fiber interface module of a communication processor using optical fibers; When the optical fiber interface module of each communication processor is connected to the optical fiber interface module of a communication processor using an optical fiber ring network, the optical fiber output end TX of the Fiber1 interface of each communication processor is connected to the optical fiber input end RX of the Fiber2 interface of a communication processor, and the optical fiber input end RX of the Fiber1 interface of each communication processor is connected to the optical fiber output end TX of the Fiber2 interface of a communication processor.

6. The high-speed and high-reliability CAN communication to optical fiber communication system according to claim 5, characterized in that: The communication unit sets a dual-ring self-healing algorithm and performs initialization when powered on. The Fiber1 interface sends a network traversal command, the Fiber2 interface receives network status information, and determines the master device of several communication processors, and the master device controls the communication link of the entire network.

7. The high-speed and high-reliability CAN communication to optical fiber communication system according to claim 6, characterized in that: When a master device of several communication processors is determined and the master device controls the communication link of the entire network, the method includes: There is one master device, and the remaining communication processors are recorded as sub-devices; The master device periodically sends a network status command, and the slave device is used to obtain the network status information of all devices on the network and determine the control status of the master device according to the link status of the communication link of the entire network.

8. The high-speed and high-reliability CAN communication to optical fiber communication system according to claim 7, characterized in that: When determining the control state of the master device according to the link state of the whole network communication link, it includes: If the link status of the whole network communication link is abnormal, the master device will re-control the sending and receiving status of each interface module of each sub-device; If the main device is offline, each sub-device restarts the initialization.

9. The high-speed and high-reliability CAN communication to optical fiber communication system according to claim 8, characterized in that: When the FPGA module performs parallel sampling, it includes: The FPGA module acquires 8 groups of parallel CAN signals, and the sampling moments of the parallel CAN signals differ by 1 / 8 bit time.

10. The high-speed and high-reliability CAN communication to optical fiber communication system according to claim 9, characterized in that: When clock information is embedded in a data frame based on Manchester encoding and 8B10B encoding, it includes: The FPGA module superimposes clock information on data bits based on Manchester encoding and 8B10B encoding and sends the data bits. The receiving end is used to receive the data signal with the clock information superimposed on the data bits and recover the clock signal.

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