Substrate layout structure for improving conversion efficiency of power supply module

Abstract

The invention discloses a substrate layout structure for improving the conversion efficiency of a power supply module, which comprises a PCB (Printed Circuit Board), a circuit with four channels which are linearly arranged is adopted by a top layer bonding pad of the PCB, CLKIN and CLKOUT pins are arranged in two channels and are connected with each other, and corresponding devices of the circuit of the same channel are arranged in a centralized manner. By adopting a large number of through holes and via holes and a copper coating mode, the utilization rate of the substrate is optimal, and the loss and interference between wires and between wires and holes are reduced; the electrical connection of the product is realized, and the conversion efficiency of the product is improved.

Description

Technical Field

[0001] The invention relates to a substrate layout structure for improving the conversion efficiency of a power module, and belongs to the technical field of power modules. Background Art

[0002] The XEC4644BS is a standalone, quad-output, non-isolated, switch-mode DC / DC power supply module. It features four independent channels, each capable of delivering up to 4A of continuous output current while requiring minimal external input and output capacitors. Each regulator provides a precisely adjustable output voltage from 0.6V to 5.5V over an input voltage range of 4V to 14V via a single external resistor. With an external bias voltage, the module can operate at a low voltage of 2.375V.

[0003] The XEC4644BS integrates four independent constant-frequency valley current-mode controllers, power MOSFETs, an inductor, and other discrete components. The typical switching frequency is set to 1MHz. For applications sensitive to switching noise, the power module can be synchronized to an external clock with a frequency range of 700kHz to 1.3MHz.

[0004] The XEC4644BS module uses current mode control with built-in feedback loop compensation, providing ample stability margin and good transient performance. It also operates over a wide range of output capacitance values, even when all output capacitors are ceramic. It also exhibits good loop stability and transient performance.

[0005] Current-mode control provides flexible paralleling of individual channels with precise current sharing. The XEC4644BS features built-in clock interleaving between every two channels, making it easy to implement 2+2, 3+1, or 4-channel parallel operation, providing flexibility in multi-rail POL applications like FPGAs. Furthermore, the XEC4644BS features CLKIN and CLKOUT pins for frequency synchronization or synchronizing multiple devices, allowing up to eight phases to operate simultaneously in cascade.

[0006] Current-mode control also provides fast, cycle-by-cycle current monitoring. Foldback current limiting is provided during overcurrent conditions, reducing the inductor valley current to approximately 40% of its original value as VFB decreases. If the output feedback voltage falls outside the ±10% window around the regulation point, an internal overvoltage or undervoltage comparator pulls the open-drain PGOOD pin low. Continuous conduction mode (CCM) operation is forced during overvoltage or undervoltage conditions, except during startup when the TRACK pin voltage rises to 0.6V.

[0007] Pulling the RUN pin below 1.1V shuts down the controller, turning off the MOSFET and most of the internal control circuitry. At light load currents, discontinuous conduction mode (DCM) can be enabled by setting the MODE pin to SGND, which offers higher efficiency than continuous conduction mode (CCM). The TRACK / SS pin is used for tracking and soft-start settings.

[0008] However, unreasonable circuit layout will affect the conversion efficiency of the power module. Summary of the Invention

[0009] The technical problem to be solved by the present invention is to provide a substrate layout structure that improves the conversion efficiency of a power module, so as to solve the problems existing in the above-mentioned prior art.

[0010] The technical solution adopted by the present invention is: a substrate layout structure for improving the conversion efficiency of a power module, including a PCB board, the top pad of the PCB board adopts a circuit with four channels arranged linearly, the CLKIN and CLKOUT pins of two channels are interconnected, and the corresponding devices of the same channel circuit are placed together.

[0011] Preferably, the soldering position of the top layer device in the above PCB board corresponds to the bottom layer pin area.

[0012] Preferably, the chip pads on the PCB are connected to the substrate pads via gold wires.

[0013] Preferably, the top layer pads correspond to the channel positions of the bottom layer pin pads respectively, the inductor device package is 3mm*3mm, the length and width dimensions of the product are: 9mm*15mm, and the size of the four inductors is 12mm.

[0014] Preferably, the same signals in the signal connection layers of the substrate are connected by copper cladding, and the signal layers are connected by vias.

[0015] Preferably, vias and through holes are used at the connection between the PCB board and the GND layer.

[0016] Beneficial effects of the present invention: Compared with the existing technology, the present invention optimizes the utilization rate of the substrate by adopting a large number of through holes, vias, and copper cladding, reducing the loss and interference between wires and between wires and holes; while achieving electrical connection of the product, it improves the conversion efficiency of the product. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 This is the 5V input efficiency curve;

[0018] Figure 2 This is the 12V input efficiency curve;

[0019] Figure 3 It is a circuit schematic;

[0020] Figure 4 This is the product pin diagram;

[0021] Figure 5 It is the chip pad layout diagram;

[0022] Figure 6 This is the front connection diagram of the chip gold wire;

[0023] Figure 7 This is the connection diagram of the gold wire on the back of the chip;

[0024] Figure 8 This is a schematic diagram of the device distribution of channel 1;

[0025] Figure 9 It is the layout diagram of the top pad of the channel;

[0026] Figure 10 This is a schematic diagram of the signal layer 1 connection;

[0027] Figure 11 This is a schematic diagram of the signal layer 2 connection;

[0028] Figure 12 This is the GND 1 layer layout diagram;

[0029] Figure 13 This is a schematic diagram of the GND 2 layer layout;

[0030] Figure 14 This is a schematic diagram of the bottom layer layout;

[0031] Figure 15 It is a schematic diagram of the product pin pad;

[0032] Figure 16 This is a 3D schematic diagram of the substrate. DETAILED DESCRIPTION

[0033] The present invention will be further described below with reference to the accompanying drawings and specific embodiments.

[0034] Example 1: Figure 1-11 As shown, a substrate layout structure for improving the conversion efficiency of a power module includes a PCB board. The top pad of the PCB board adopts a linear arrangement of four-channel circuits. The CLKIN and CLKOUT pins of two channels are interconnected. The corresponding components of the same channel circuit are placed together. The welding position of the top component of the PCB board corresponds to the pin area of the bottom layer. The chip pad on the PCB board is connected to the substrate pad by gold wire.

[0035] From the circuit connection

[0036] From the schematic diagram, the module has four channels, each channel is independent and arranged linearly, and only the CLKIN and CLKOUT pins are connected to each other. Therefore, in the substrate layout, the corresponding devices of the same channel should be placed together as much as possible to reduce mutual interference between channels.

[0037] 2. Device packaging

[0038] According to the device BOM table, only the chip and inductor packages are large, thus occupying more space on the substrate. When considering the substrate layout, it is necessary to give priority to the location of the chip and inductor. Then, according to the device connection situation and device package, a reasonable layout should be made, effectively utilizing the substrate layout, enhancing space utilization, reducing device interference, and improving module efficiency.

[0039] 3. Product pins

[0040] According to the pin pad on the bottom of the product Figure 4 , starting from the 1-pin mark point downwards, they correspond to the pin pads of channels 1, 2, 3, and 4 in turn. In order to shorten the wiring path and reduce the loss caused by too long lines, the welding position of the top-layer device should be matched with the bottom-layer pin area as much as possible to avoid excessive damage and interference between channels caused by wiring across the area.

[0041] Table 1 Pin description table

[0042]

[0043] VOUT1 (A1, A2, A3), VOUT2 (C1, D1, D2), VOUT3 (F1, G1, G2), VOUT4 (J1, K1, K2): Power output pins. Apply output loads between these pins and GND, and place output decoupling capacitors between these pins and GND.

[0044] GND (A4-A5, B1-B2, C5, D3-D5, E1-E2, F5, G3-G5, H1-H2, J5, K3-K4, L1-L2): Power ground pins. Use a large area of PCB copper to connect all GND pins together.

[0045] VIN1 (B3, B4), VIN2 (E3, E4), VIN3 (H3, H4), VIN4 (L3, L4): Power supply input pins. Connect to the drain of the upper power MOSFET within each channel. Apply input voltage between these pins and GND. It is recommended to place an input decoupling capacitor between each VIN pin and GND.

[0046] PGOOD1, PGOOD2, PGOOD3, PGOOD4 (C3, C2, F2, J2): Power supply output good indication, open-drain logic output pins. When the voltage on the FB pin is not within ±10% (typical) of the internal 0.6V reference voltage, PGOOD is pulled low to GND.

[0047] CLKOUT (J3): Clock output pin. Used to output a multi-phase clock signal. CLKOUT is set to a phase of 180° relative to CLKIN. The peak-to-peak value of CLKOUT is the value between INTVCC and GND. This pin is an output; do not drive it.

[0048] INTVCC1, INTVCC2, INTVCC3, INTVCC4 (C4, F4, J4, K5): Internal power supply output pins. The internal power driver and control circuits are powered by this voltage. Each pin uses an internal 2.2μF low-ESR ceramic capacitor to GND as a decoupling capacitor.

[0049] SVIN1, SVIN2, SVIN3, SVIN4 (B5, E5, H5, L5): Bias input voltage. This is the input voltage for the internal 3.3V regulator, which controls each channel. In most applications, connect this pin to the VIN pin. The SVIN input voltage should be greater than 4V and higher than the output voltage.

[0050] TRACK / SS1, TRACK / SS2, TRACK / SS3, TRACK / SS4 (A6, D6, G6, K6): Output tracking and soft-start pins. These pins allow the user to control the output voltage rise time. Applying a voltage below 0.6V to these pins bypasses the internal reference input of the error amplifier and sets the FB pin to the TRACK voltage. Above 0.6V, tracking stops and the internal reference resumes control of the error amplifier. INTVCC on these pins has an internal pull-up current of typically 2.5μA, so placing a capacitor here provides soft-start functionality. This pin cannot be left floating.

[0051] MODE1, MODE2, MODE3, MODE4 (B6, E6, H6, L6): Operating mode select pins. Connecting this pin to INTVCC forces all outputs to operate in CCM mode; connecting it to SGND enables DCM mode operation at light loads. This pin should not be left floating. DCM mode increases ripple; CCM mode is recommended.

[0052] RUN1, RUN2, RUN3, RUN4 (C6, F6, J6, K7): Enable input pins. Connecting the RUN pin to 1.6V or higher enables the regulator. Pulling it below 0.8V disables the corresponding regulator channel. This pin should not be left floating.

[0053] FB1, FB2, FB3, FB4 (A7, D7, G7, J7): Feedback pins (negative input pins of the error amplifier). Internally, the XEC4644BS connects these pins to VOUT for each channel through 60.4kΩ precision resistors. Different output voltages can be achieved by connecting different external resistors between the FB and SGND pins. For multi-phase parallel operation, connect the FB pins together for parallel operation.

[0054] COMP1, COMP2, COMP3, COMP4 (B7, E7, H7, L7): Current threshold control and stability compensation pins. The internal current comparator threshold is proportional to this voltage. Connecting the COMP pins together enables parallel operation and internal compensation.

[0055] CLKIN (C7): External Clock Input. This pin is used to input the external clock to the internal phase-locked loop (PLL). This pin is internally terminated with 20kΩ to SGND. The PLL forces the Channel 1 turn-on signal to synchronize with the rising edge of the CLKIN signal. Channels 2, 3, and 4 also synchronize with the rising edge of the CLKIN signal, with a programmed phase shift.

[0056] SGND (F7): Signal ground pin. SGND connects to the internal signal GND. Use a separate SGND ground copper area for the feedback resistor ground and other signal grounds. A second connection between the PGND and SGND planes on the bottom PCB layer is recommended.

[0057] TEMP (F3): Temperature detection pin. Used to monitor the change of VBE junction voltage with temperature.

[0058] The chip is the main component of the product. The chip pad needs to be connected to the substrate pad through gold wire to achieve circuit connection. The chip pad is located around the chip. Figure 5 The chips are arranged in a distributed manner, so the chip position needs to be fixed first. The placement of surrounding components needs to be determined according to the chip placement direction. The circuit connection of the chip is as follows:

[0059] Table 2 Chip pad position and gold wire quantity

[0060]

[0061]

[0062]

[0063] Top-level layout: According to the above layout requirements and chip connection scheme, the top-level pad layout should be arranged linearly according to the channel, corresponding to the channel position of the bottom-level pin pad. The inductor device package is 3mm*3mm, the length and width of the product are: 9mm*15mm, and the size of the four inductors is 12mm. The inductor placement position can only be sorted in the direction of the product length dimension; after determining the chip position and direction, the connecting devices corresponding to the chip pin pads should be placed nearby to reduce losses.

[0064] Therefore, the corresponding device placement area should be arranged according to the chip gold wire connection area, such as Figure 7 As shown, the inductor is arranged in parallel with the chip, which improves substrate utilization and shortens the connection distance between the chip and each device, reducing losses. The layout of each channel is arranged linearly according to the channel, and the top pad layout of the substrate is determined.

[0065] Signal layer layout: The signal connection layer of the substrate is mainly used to realize the circuit connection between various devices. The connection line is short based on the connection distance and the interference between lines is small. In addition to the signal circuit connection, the same signals are connected by copper cladding to enhance the stability of the connection between the same signals. The signal layers are connected by vias to effectively utilize the space and reduce interference.

[0066] GND layer layout: The module is a power device. When working, each device will generate a lot of heat. If this heat cannot be dissipated effectively, it will increase the module loss and have a great impact on the module's conversion efficiency. In addition to being conducted to the module surface through the plastic packaging material and then dissipated through subsequent heat dissipation measures, this heat can also be dissipated through the layout design of the substrate, increasing the layout area of the substrate GND layer, and using more vias and through-holes to dissipate the heat through a large area of copper cladding. The heat is then conducted to the entire board through the module pins for diffusion. Bottom layer layout: The module bottom layer pad layout should correspond to the module pin pad. The same pads should also be covered with copper to increase the connection area.

[0067] The overall substrate uses a large number of through holes, vias, and copper cladding to optimize the utilization of the substrate, reducing the loss and interference between lines and between lines and holes; while achieving electrical connection of the product, it also improves the conversion efficiency of the product.

[0068] The above description is only a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any technician familiar with the technical field can easily think of changes or replacements within the technical scope disclosed by the present invention, which should be included in the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be based on the scope of protection of the claims.

Claims

1. A substrate layout structure for improving the conversion efficiency of a power module, characterized by: Including a PCB board, the top pad of the PCB board adopts a linear arrangement of four-channel circuits, two channels have CLKIN and CLKOUT pins connected to each other, and corresponding devices of the same channel circuit are placed together.

2. The substrate layout structure for improving power module conversion efficiency according to claim 1, characterized in that: The soldering position of the top layer device in the PCB board corresponds to the pin area of the bottom layer.

3. The substrate layout structure for improving power module conversion efficiency according to claim 1, characterized in that: The chip pads on the PCB are connected to the substrate pads through gold wires.

4. The substrate layout structure for improving power module conversion efficiency according to claim 1, characterized in that: The top pads correspond to the channel positions of the bottom pin pads. The inductor device package is 3mm*3mm, the length and width of the product are: 9mm*15mm, and the size of the four inductors is 12mm.

5. The substrate layout structure for improving power module conversion efficiency according to claim 1, characterized in that: The same signals in the signal connection layer of the substrate are connected by copper cladding, and the signal layers are connected by vias.

6. The substrate layout structure for improving power module conversion efficiency according to claim 1, characterized in that: Vias and through holes are used to connect the PCB board to the GND layer.

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