Semiconductor device and method for manufacturing semiconductor device

Abstract

The invention relates to a semiconductor device and a manufacturing method of the semiconductor device. A semiconductor device may include: a gate structure including stacked conductive layers and an insulating region disposed between the conductive layers; a channel layer extending through the gate structure; data storage patterns respectively surrounding the channel layers and disposed between the channel layers and the conductive layers; oxidation patterns respectively surrounding the channel layers and disposed between the channel layers and the insulating regions; and a barrier layer surrounding the data storage pattern and the oxide pattern and including a recess disposed corresponding to the insulating region.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to electronic devices, and more particularly, to a semiconductor device and a method for manufacturing the semiconductor device. Background Art

[0002] The integration level of a semiconductor device is primarily determined by the area occupied by a unit memory cell. Recently, as improvements in the integration level of semiconductor devices that form memory cells in a single layer on a substrate have reached their limits, three-dimensional semiconductor devices that stack memory cells on a substrate have been proposed. Furthermore, various structures and manufacturing methods have been developed to improve the operational reliability of such semiconductor devices. Summary of the Invention

[0003] In an embodiment of the present disclosure, a semiconductor device may include: a gate structure including stacked conductive layers and an insulating region arranged between the conductive layers; a channel layer extending through the gate structure; data storage patterns respectively surrounding the channel layer and arranged between the channel layer and the conductive layer; oxidation patterns respectively surrounding the channel layer and arranged between the channel layer and the insulating region; and a blocking layer surrounding the data storage pattern and the oxidation pattern and including a recess arranged corresponding to the insulating region.

[0004] In an embodiment of the present disclosure, a semiconductor device may include: a gate structure including stacked gate lines; a channel layer extending through the gate structure; a tunneling structure surrounding the channel layer and including protruding portions arranged between the gate lines; data storage patterns respectively surrounding the tunneling structures and arranged between the protruding portions; a barrier layer surrounding the data storage pattern and the tunneling structure; and a sealing layer extending through the gate structure and defining air gaps arranged between the gate lines, wherein each air gap may protrude into the barrier layer and the sealing layer.

[0005] In an embodiment of the present disclosure, a method for manufacturing a semiconductor device may include the following steps: forming a stack including alternately stacked first material layers and second material layers; forming a first opening extending through the stack; forming a barrier layer within the first opening; forming a data storage layer within the barrier layer; forming a slit extending through the stack; forming a second opening by etching the second material layer through the slit, the second opening exposing the barrier layer; forming a recess on a surface of the barrier layer by etching the barrier layer exposed through the second opening; and oxidizing the data storage layer through the recess of the barrier layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figures 1A to 1C is a diagram illustrating a structure of a semiconductor device according to an embodiment of the present disclosure.

[0007] Figure 2is a diagram illustrating a structure of a semiconductor device according to an embodiment of the present disclosure.

[0008] Figure 3 is a diagram illustrating a structure of a semiconductor device according to an embodiment of the present disclosure.

[0009] Figures 4A to 4E 1 is a diagram for describing a method for manufacturing a semiconductor device according to an embodiment of the present disclosure.

[0010] Figures 5A to 5C 1 is a diagram for describing a method for manufacturing a semiconductor device according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0011] Various embodiments of the present disclosure are directed to a semiconductor device having a stable structure and improved characteristics and a method of manufacturing the semiconductor device.

[0012] By three-dimensionally stacking memory cells, the integration density of a semiconductor device can be improved, and a semiconductor device having a stable structure and improved reliability can also be provided.

[0013] Hereinafter, embodiments according to the technical scope of the present disclosure will be described with reference to the accompanying drawings.

[0014] Figures 1A to 1C is a diagram illustrating a structure of a semiconductor device according to an embodiment of the present disclosure.

[0015] Reference Figure 1A The semiconductor device may include a gate structure GST, a channel layer 16, a data storage pattern 14, and a barrier layer 13. The semiconductor device may further include at least one of a tunneling structure TS and an insulating core 17.

[0016] The gate structure GST may include stacked conductive layers 11 and insulating regions disposed between the conductive layers 11. For example, the insulating regions may include air gaps AG. Along the stacking direction, the conductive layers 11 and the air gaps AG may be alternately disposed. For example, the conductive layer 11 may be a gate line such as a select line or a word line. The conductive layer 11 may include a conductive material such as polysilicon or a metal. For example, the conductive layer 11 may include a barrier layer 11A and a metal layer 11B disposed within the barrier layer 11A. The barrier layer 11A may surround the metal layer 11B that defines the outer boundary of the conductive layer 11. The barrier layer 11A may include, for example, a metal nitride, and the metal layer 11B may include, for example, tungsten (W), molybdenum (Mo), etc. The air gaps AG may be empty spaces between the conductive layers 11 and may electrically insulate the conductive layers 11 from each other.

[0017] The channel layer 16 may extend through the gate structure GST. The channel layer 16 may extend through the entire gate structure GST, i.e., from the front surface to the rear surface of the gate structure GST. The front surface and rear surface of the gate structure GST may also be referred to as the top surface and bottom surface of the gate structure GST, respectively. For example, the channel layer 16 may include a semiconductor material such as silicon or germanium. An insulating core 17 may be disposed within the channel layer 16 and may include an insulating material such as, for example, an oxide or a nitride, and may include voids therein.

[0018] The tunnel structure TS may surround the channel layer 16 and may include a protruding portion (see oxidation pattern 18) disposed between the conductive layers 11. The protruding portion may be disposed vertically between the data storage patterns 14. For example, the tunnel structure TS may include a tunnel layer 15 and an oxidation pattern 18. The tunnel layer 15 may surround the sidewalls of the channel layer 16. The tunnel layer 15 may be disposed between the channel layer 16 and the conductive layer 11 and between the channel layer 16 and the air gap AG. The oxidation pattern 18 may protrude from the tunnel layer 15 toward the air gap AG. The oxidation pattern 18 may be disposed between the channel layer 16 and the air gap AG, respectively. The oxidation pattern 18 may be disposed between the data storage patterns 14, respectively, and may separate the data storage patterns 14 from each other.

[0019] The oxidation patterns 18 may be formed by oxidizing the data storage layer. For example, the tunneling layer 15 may be an oxide layer formed by a deposition process, and the oxidation patterns 18 may each be an oxide layer formed by an oxidation process. An interface may or may not exist between the oxidation patterns 18 and the tunneling layer 15.

[0020] The data storage patterns 14 may surround a portion of the tunnel structure TS and may be respectively disposed between protruding portions of the tunnel structure TS. For example, the data storage patterns 14 may surround the channel layer 16 with the tunnel layer 15 interposed therebetween. The data storage patterns 14 may be disposed between the channel layer 16 and the conductive layer 11 and may be separated from each other by the oxide pattern 18. The data storage patterns 14 may each include a floating gate, polysilicon, a charge trapping material, a nitride, a variable resistance material, or the like.

[0021] The barrier layer 13 may surround the data storage pattern 14 and the oxidation pattern 18. The barrier layer 13 may have a shape continuously extending along the sidewall of the channel layer 16. The barrier layer 13 may be disposed between the data storage pattern 14 and the conductive layer 11, and may also be disposed between the oxidation pattern 18 and the air gap AG.

[0022] The barrier layer 13 may have different thicknesses depending on the region. The barrier layer 13 may include a first portion 13_P1 surrounding the data storage pattern 14 and a second portion 13_P2 surrounding the oxidation pattern 18. The first portion 13_P1 and the second portion 13_P2 may have different thicknesses. The thickness of the second portion 13_P2 may be smaller than that of the first portion 13_P1. The air gap AG may protrude toward the barrier layer 13, and as the air gap AG protrudes, the thickness of the second portion 13_P2 may be smaller than that of the first portion 13_P1.

[0023] The barrier layer 13 may include a recessed portion CP. The recessed portion CP may be provided on the outer wall of the barrier layer 13 and may be provided corresponding to the air gap AG. The recessed portion CP may be provided in the second portion 13_P2. Each recessed portion CP may include a center C and an edge E, and the thickness of the barrier layer 13 at the center C may be less than the thickness at the edge E. Each recessed portion CP may have a circular surface, and the circular surface may be exposed through the air gap AG.

[0024] Reference Figure 1B , each oxidized pattern 18 may include a first sidewall SW1 facing the tunneling layer 15 and a second sidewall SW2 facing the barrier layer 13. The first sidewall SW1 may include a curved surface. In a cross section, for example, Figure 1B As shown, the second sidewall SW2 may be flat. The oxidation pattern 18 may protrude into the tunneling layer 15. The data storage pattern 14 may include a sidewall facing the oxidation pattern 18, and the sidewall may include a curved surface. In a cross section, for example, as shown in FIG. Figure 1B As shown, the data storage pattern 14 may have a trapezoidal shape, wherein respective base sides of the trapezoid are oriented vertically (ie, in the stacking direction).

[0025] The barrier layer 13 may include a high-k material, such as hafnium oxide or aluminum oxide. When the barrier layer 13 includes a low-k material, a sufficient bias may not be applied to the tunneling layer 15 due to the gate coupling ratio. Conversely, when the barrier layer 13 includes a high-k material, the bias applied to the tunneling layer 15 can be increased, and the operation of the memory cell can be improved.

[0026] Reference Figure 1C The barrier layer 13 of the semiconductor device may be a multilayer structure. The barrier layer 13 may include a first barrier layer 13A and a second barrier layer 13B. The second barrier layer 13B may surround the data storage pattern 14 and the oxidation pattern 18. The first barrier layer 13A may surround the second barrier layer 13B. The second barrier layer 13B may be disposed between the oxidation pattern 18 and the first barrier layer 13A and between the data storage pattern 14 and the first barrier layer 13A. The second barrier layer 13B may have a thickness of 5 nm or less (e.g., 5 nm to 1 nm or 5 nm to 0.5 nm).

[0027] First barrier layer 13A and second barrier layer 13B may include materials having different dielectric constants. For example, first barrier layer 13A may include a material having a higher dielectric constant than second barrier layer 13B. First barrier layer 13A may include a high-k material such as hafnium oxide or aluminum oxide, and second barrier layer 13B may include a low-k material such as silicon oxide or silicon nitride. Therefore, even if leakage current increases due to first barrier layer 13A including a high-k material, the addition of second barrier layer 13B may reduce leakage current to a lesser extent.

[0028] According to the above structure, memory cells or selection transistors can be provided in the region where the channel layer 16 and the conductive layer 11 intersect each other. The data storage patterns 14 can be separated from each other by the oxidation pattern 18, and the memory cells can each include the data storage pattern 14. Therefore, the data retention characteristics of the semiconductor device can be improved.

[0029] Air gap AG may be provided between stacked conductive layers 11 and may reduce capacitance between stacked conductive layers 11. Because barrier layer 13 includes recessed portion CP, capacitance between conductive layer 11 and channel layer 16 may be reduced. Consequently, RC delay of the semiconductor device may be improved, and programming speed may be improved.

[0030] Figure 2 1 is a diagram illustrating a structure of a semiconductor device according to an embodiment of the present disclosure.

[0031] Reference Figure 2 The semiconductor device may include a gate structure GST and a channel structure CH. The semiconductor device may further include at least one of a sealing layer 20 and a source contact structure 29 .

[0032] The gate structure GST may include a conductive layer 21 and an air gap AG. Each conductive layer 21 may include a barrier layer 21A and a metal layer 21B. The channel structure CH may extend through the gate structure GST. The channel structure CH may include a channel layer 26 and may further include at least one of a barrier layer 23, a data storage pattern 24, a tunneling layer 25, an oxidation pattern 28, and an insulating core 27. The barrier layer 23 may include a recessed portion CP.

[0033] The source contact structure 29 may extend through the gate structure GST. For example, the source structure may be disposed below the gate structure GST, and the channel structure CH may extend through the gate structure GST into the source structure. The source contact structure 29 may penetrate the gate structure GST and may be electrically connected to the source structure. For reference, the semiconductor device may also include a gapfill layer instead of the source contact structure 29. The gapfill layer may include an insulating material, a semiconductor material, or the like.

[0034] Sealing layer 20 may surround the sidewalls of source contact structure 29. Sealing layer 20 may include first portions 20_P1 and second portions 20_P2 alternating along the stacking direction. First portion 20_P1 may be disposed between source contact structure 29 and conductive layer 21. Second portion 20_P2 may be disposed between source contact structure 29 and air gap AG. The thickness of second portion 20_P2 may be less than that of first portion 20_P1. Air gap AG may protrude into sealing layer 20, and each second portion 20_P2 may include a groove G. The groove G may be disposed corresponding to the air gap AG, i.e., one groove G may be formed next to each air gap AG.

[0035] The sealing layer 20 may be an oxide layer formed by a chemical vapor deposition (CVD) method. The sealing layer 20 may be formed by depositing a sealing material with poor step coverage. An air gap AG disposed between the conductive layers 21 may be defined by the barrier layer 23 and the sealing layer 20. The air gap AG may protrude into the barrier layer 23 and the sealing layer 20.

[0036] According to the above structure, the capacitance between the conductive layers 21 can be reduced by the air gap AG. In addition, the capacitance between the channel layer 26 and the conductive layer 21 can be reduced by the recess CP. Therefore, the RC delay of the semiconductor device can be improved, and the programming operation speed can be improved.

[0037] Figure 3 1 is a diagram illustrating a structure of a semiconductor device according to an embodiment of the present disclosure.

[0038] Reference Figure 3 The semiconductor device may include a gate structure GST and a channel structure CH. The semiconductor device may further include at least one of a sealing layer 30 and a source contact structure 39 .

[0039] The gate structure GST may include a conductive layer 31 and an air gap AG. Each conductive layer 31 may include a barrier layer 31A and a metal layer 31B. The channel structure CH may extend through the gate structure GST. The channel structure CH may include a channel layer 36 and may further include at least one of a barrier layer 33, a data storage pattern 34, a tunneling layer 35, an oxidation pattern 38, and an insulating core 37. The barrier layer 33 may include a recessed portion CP.

[0040] The sealing layer 30 may include a penetration portion 30A and an extension portion 30B. The penetration portion 30A may extend through the gate structure GST. The penetration portion 30A may include a groove G on its inner wall and / or outer wall. The extension portion 30B may protrude from the penetration portion 30A and may extend into the gate structure GST along the sidewall of the conductive layer 21. The extension portion 30B may extend along the recess CP of the barrier layer 33, and air gaps AG may be respectively provided in the extension portion 30B. Depending on the step coverage of the deposition process for forming the sealing layer 30, the sealing layer 30 may or may not include the extension portion 30B. In addition, the thickness of the extension portion 30B may be adjusted to be large or small according to the step coverage.

[0041] According to the above structure, air gap AG and extension portion 30B can be provided between stacked conductive layers 31. Therefore, the capacitance between stacked conductive layers 31 can be reduced by air gap AG. Extension portion 30B is provided between conductive layers 31, so the capacitance between conductive layers 31 can be reduced to a small extent. However, the magnitude of the bias applied to tunneling layer 35 can be increased by extension portion 30B. Therefore, whether to form extension portion 30B and the thickness of extension portion 30B can be adjusted depending on the change in capacitance between air gap AG and extension portion 30B.

[0042] Figures 4A to 4E 1 is a diagram for describing a method for manufacturing a semiconductor device according to an embodiment of the present disclosure.

[0043] Reference Figure 4A , a stack ST including alternately stacked first material layers 41 and second material layers 42 can be formed. The first material layers 41 can each include a material having a high etching selectivity relative to the second material layers 42. The first material layers 41 can be used to form gate lines. For example, the first material layers 41 can each include a sacrificial material such as nitride or a conductive material such as polysilicon or metal. The second material layers 42 can be used to form air gaps. For example, the second material layers 42 can each include a sacrificial material such as oxide.

[0044] Subsequently, a first opening OP1 extending through the stack ST may be formed, and a channel structure CH may be formed within the first opening OP1. The channel structure CH may include at least one of a barrier layer 43, a data storage layer 44, a tunneling layer 45, a channel layer 46, and an insulating core 47. For example, the barrier layer 43 may be conformally formed on the sidewall surfaces of the first opening within the first opening OP1. The data storage layer 44 may then be conformally formed on the barrier layer 43 to cover the exposed sidewall surfaces of the barrier layer 43. Similarly, the tunneling layer 45 may then be conformally formed on the data storage layer 44 to cover the exposed sidewalls of the data storage layer 44, and the channel layer 46 may be conformally formed on the tunneling layer 45 to cover the exposed sidewall surfaces of the tunneling layer 45. The insulating core 47 may be formed within the channel layer 46. Conformally forming one layer on another means that the newly formed layer follows the contours and topography of the underlying layer without leaving gaps or voids. This conformal deposition results in the formation of a layer of uniform thickness and ensures proper performance of the semiconductor device.

[0045] Barrier layer 43 may include a material having a high etch selectivity relative to second material layer 42. For example, second material layers 32 may each include an insulating material such as silicon oxide or silicon nitride, and barrier layer 33 may include a high-k material such as hafnium oxide or aluminum oxide.

[0046] Reference Figure 4B , a slit SL may be formed to extend through the stack ST along the stacking direction. Subsequently, a second opening OP2 may be formed by removing the first material layer 41 through the slit SL. Subsequently, a third material layer 49 may be formed within each of the second openings OP2. For example, the third material layer 49 may be used to form a gate line. For example, a barrier layer 49A may be formed within the second opening OP2, and a metal layer 49B may be formed within the barrier layer 49A. Thus, a gate structure GST including alternately stacked second material layers 42 and third material layers 49 may be formed.

[0047] For reference, when the first material layers 41 each include a conductive material, the process of forming the third material layer 49 may be omitted. In this case, the first material layers 41 may serve as a gate line, and the stack ST may serve as a gate structure GST.

[0048] Reference Figure 4C , the second material layer 42 and the barrier layer 43 can be etched through the slit SL. For example, the third opening OP3 exposing the barrier layer 43 can be formed by etching the second material layer 42 through the slit SL. In this case, the etching process can be performed under a condition where the etching selectivity of the second material layer 42 relative to the barrier layer 43 is high. For example, the etching selectivity between the barrier layer 43 and the second material layer 42 can be 100:1 to 500:1. Therefore, during the process of etching the second material layer 42, the data storage layer 44 can be protected by the barrier layer 43.

[0049] When the second material layer 42 is etched under a condition where the etching selectivity of the second material layer 42 relative to the barrier layer 43 is high, the barrier layer 43 may be partially etched during the process of etching the second material layer 42. The surface of the barrier layer 43 exposed by the third opening OP3 may be partially deeply etched, and recesses CP may be formed on the surface of the barrier layer 43. Each recess CP may have a circular surface. Therefore, the barrier layer 43A including the recesses CP may be formed without performing a separate etching process for etching the barrier layer 43.

[0050] Reference Figure 4D , the data storage layer 44 may be oxidized by the recess CP of the barrier layer 43A. For example, the data storage layer 44 may be oxidized using a thermal oxidation process or a plasma oxidation process. Through the oxidation process, the data storage layer 44 may be partially oxidized and separated into data storage patterns 44A. Portions of the data storage layer 44 adjacent to the recess CP (i.e., those portions corresponding to the recess CP) are oxidized, and oxidation patterns 44B are formed. Portions of the data storage layer 44 next to the third material layer 49 are not oxidized. The portions of the data storage layer 44 that remain unoxidized become data storage patterns 44A. Each pair of consecutive data storage patterns 44A is therefore separated from each other by oxidation patterns 44B.

[0051] Because the data storage layer 44 is oxidized through the recessed portion CP, the data storage layer 44 can be uniformly oxidized. When the oxidation process is performed while the data storage layer 44 is exposed, the degree of oxidation of the data storage layer 44 may vary depending on the distance from the slit SL, and the size and shape of the data storage patterns 44A may be uneven. As the data storage layer 44 gets closer to the slit, the data storage layer 44 may be more oxidized, and the size of the data storage patterns 44A may decrease. In contrast, when the data storage layer 44 is oxidized without the barrier layer 43A being etched at all, the data storage layer 44 may not be fully oxidized, and the data storage patterns 44A may not be separated from each other. In addition, when an over-oxidation process is performed to fully oxidize the data storage layer 44, surrounding layers may be damaged. According to embodiments of the present disclosure, the data storage layer 44 can be oxidized through the recessed portion CP. Because the data storage layer 44 is oxidized through the relatively thin recessed portion CP, the data storage layer 44 can be uniformly oxidized regardless of its location. In addition, the data storage layer 44 can be fully oxidized so that the data storage patterns 44A are separated from each other.

[0052] Reference Figure 4E, a sealing layer 48 can be formed within the slit SL. The sealing layer 48 can be formed by depositing a sealing material with poor step coverage. For example, the sealing layer 48 may include carbon or an oxide. The sealing material can be deposited on the sidewalls of the third material layer 49 exposed by the slit SL and can define an air gap AG by sealing the third opening OP3. Depending on the deposition conditions, the area where the sealing material is deposited can be adjusted. When the sealing material is deposited under conditions of poor step coverage, the sealing material may not be deposited or may be minimally deposited within the third opening OP3. As a result, the size of the air gap AG can be increased.

[0053] Subsequently, a source contact structure 50 may be formed within the slit SL. The source contact structure 50 may include a conductive material such as, for example, polysilicon, tungsten, or molybdenum. For reference, a gap-filling layer may be formed instead of the source contact structure 50, and the gap-filling layer may include an insulating material, a semiconductor material, or the like.

[0054] According to the above manufacturing method, the barrier layer 43A including the concave portion CP may be formed, and the data storage layer 44 may be partially oxidized through the concave portion CP. Thus, the data storage layer 44 may be separated into the data storage pattern 44A, and data retention characteristics may be improved.

[0055] Since the air gap AG is formed between the stacked third material layers 49, the capacitance between the stacked third material layers 49 may be reduced. In addition, since the barrier layer 43A includes the concave portion CP, the capacitance between the third material layer 49 and the channel layer 46 may be reduced.

[0056] Figures 5A to 5C 1 is a diagram for describing a method for manufacturing a semiconductor device according to an embodiment of the present disclosure. Any description made earlier may not be repeated.

[0057] Reference Figure 5A , a stack ST is formed to include alternately stacked first material layers 51 and second material layers 52. Subsequently, a channel structure CH is formed that extends through the stack ST in a stacking direction and may include at least one of a barrier layer 53, a data storage layer 54, a tunneling layer 55, a channel layer 56, and an insulating core 57. In this embodiment, the barrier layer 53 includes a first barrier layer 53A and a second barrier layer 53B.

[0058] The first barrier layer 53A and the second barrier layer 53B may include materials having different dielectric constants. For example, the first barrier layer 53A may include a material having a higher dielectric constant than the second barrier layer 53B. The first barrier layer 53A may include a high-k material such as, for example, hafnium oxide or aluminum oxide, and the second barrier layer 53B may include a low-k material such as, for example, silicon oxide or silicon nitride.

[0059] Reference Figure 5B, a slit SL may be formed extending through the stack ST along the stacking direction. Then, the first material layer 51 may be replaced with a third material layer 59 through the slit SL. For example, the third material layer 59 may be used to form a gate line. For example, the metal layer 59B may be formed after forming the barrier layer 59A. Thus, a gate structure GST including the alternately stacked second material layers 52 and third material layers 59 may be formed.

[0060] Subsequently, the second material layer 52 and the barrier layer 53 may be etched through the slit SL. For example, the opening OP exposing the first barrier layer 53A may be formed by etching the second material layer 52 through the slit SL. In this case, the etching process may be performed under conditions where the etching selectivity of the second material layer 52 relative to the first barrier layer 53A is high. For example, the etching selectivity between the first barrier layer 53A and the second material layer 52 may be 100:1 to 500:1. Therefore, during the etching process of the second material layer 52, the second barrier layer 53B and the data storage layer 54 may be protected by the first barrier layer 53A.

[0061] In the process of etching the second material layer 52, the first barrier layer 53A may be partially etched. The surface of the first barrier layer 53A exposed by the opening OP may be partially deeply etched, and a concave portion CP may be formed on the surface of the first barrier layer 53A. Thus, a first barrier layer 53AA including the concave portion CP may be formed. The first barrier layer 53AA may have a continuously connected shape.

[0062] According to etching conditions, the first barrier layer 53A may be etched to expose the second barrier layer 53B. In this case, the second barrier layer 53B may be partially etched, and a concave portion CP may be formed on the surface of the second barrier layer 53B.

[0063] Reference Figure 5C , the data storage layer 54 may be oxidized through the concave portion CP of the barrier layer 53. The data storage layer 54 may be oxidized through the first barrier layer 53A and the second barrier layer 53B or through the second barrier layer 53B. Thus, a data storage pattern 54A and an oxidation pattern 54B may be formed. For reference, when the data storage layer 54 is oxidized through the first barrier layer 53A and the second barrier layer 53B, the second barrier layer 53B may be formed to have a thickness of 5 nm or less so that the data storage layer 54 is sufficiently oxidized.

[0064] Subsequently, a sealing layer 58 may be formed within the slit SL. The sealing layer 58 may be formed by depositing a sealing material within the slit SL. In this case, the sealing material may also be deposited within the opening OP. The thickness of the deposited sealing material may be adjusted by adjusting the deposition recipe in consideration of the step coverage. Thus, a sealing layer 58 including a penetrating portion 58A and an extending portion 58B may be formed. The portion formed within the slit SL may be the penetrating portion 58A, and the portion formed within the opening OP may be the extending portion 58B. Subsequently, a source contact structure 60 or a gap-fill layer may be formed within the slit SL.

[0065] According to the above-described manufacturing method, barrier layer 53 can be formed into multiple layers. By forming barrier layer 53 into multiple layers, the increase in leakage current can be improved while reducing capacitance. In addition, by forming extension portion 58B within opening OP, the reduction in electric field strength caused by air gap AG can be compensated.

[0066] Although embodiments according to the technical concepts of the present disclosure have been described above with reference to the accompanying drawings, this is merely for the purpose of describing embodiments according to the concepts of the present disclosure, and the present disclosure is not limited to the aforementioned embodiments. Without departing from the technical concepts of the present disclosure as defined in the following claims, those skilled in the art may make various substitutions, modifications, changes, and combinations of the embodiments, and such substitutions, modifications, changes, and combinations should be construed as falling within the scope of the present disclosure. Furthermore, these embodiments may be combined to form additional embodiments.

[0067] CROSS-REFERENCE TO RELATED APPLICATIONS

[0068] This application claims priority from Korean Patent Application No. 10-2024-0018091, filed on February 6, 2024, which is hereby incorporated by reference herein in its entirety.

Claims

1. A semiconductor device, comprising: a gate structure comprising stacked conductive layers and an insulating region disposed between the conductive layers; a channel layer extending through the gate structure; data storage patterns, the data storage patterns respectively surrounding the channel layers and being disposed between the channel layers and the conductive layer; oxidation patterns, each of which surrounds the channel layer and is disposed between the channel layer and the insulating region; as well as A barrier layer surrounds the data storage pattern and the oxidation pattern and includes a recessed portion corresponding to the insulating region.

2. The semiconductor device according to claim 1, wherein Each of the insulating regions includes an air gap.

3. The semiconductor device according to claim 1, wherein The barrier layer includes a first portion surrounding the data storage pattern and a second portion surrounding the oxidation pattern, and a thickness of the second portion is smaller than a thickness of the first portion.

4. The semiconductor device according to claim 1, wherein The recess is provided on the outer wall of the barrier layer.

5. The semiconductor device according to claim 1, wherein Each of the recesses has a circular surface. The semiconductor device according to claim 1 , wherein: Each of the recesses includes a center and an edge, and a thickness of the barrier layer at the center is smaller than a thickness at the edge.

7. The semiconductor device according to claim 1, wherein A sidewall of the data storage pattern facing the oxidation pattern includes a curved surface.

8. The semiconductor device according to claim 1, further comprising: a source contact structure extending through the gate structure; as well as A sealing layer surrounds the sidewall of the source contact structure.

9. The semiconductor device according to claim 8, wherein The sealing layer includes a groove corresponding to the insulating area.

10. The semiconductor device according to claim 8, wherein The sealing layer includes a first portion disposed between the conductive layer and the source contact structure and a second portion disposed between the insulating region and the source contact structure, and a thickness of the second portion is smaller than a thickness of the first portion.

11. The semiconductor device according to claim 8, wherein The sealing layer comprises: a penetrating portion extending through the gate structure; and An extension portion extends along a surface of the conductive layer into the gate structure.

12. The semiconductor device according to claim 11, wherein The extending portion extends along the recessed portion of the barrier layer.

13. The semiconductor device according to claim 11, wherein The insulating region is disposed within the extending portion.

14. The semiconductor device according to claim 1, wherein The barrier layer includes a high-k material.

15. The semiconductor device according to claim 1, wherein The barrier layer comprises: a first barrier layer including the recess; and A second barrier layer is disposed between the data storage pattern and the first barrier layer and between the oxidation pattern and the first barrier layer.

16. The semiconductor device according to claim 15, wherein The first barrier layer includes a high-k material, and the second barrier layer includes a low-k material.

17. A semiconductor device comprising: a gate structure comprising stacked gate lines; a channel layer extending through the gate structure; a tunneling structure surrounding the channel layer and including a protruding portion disposed between the gate lines; data storage patterns, the data storage patterns respectively surrounding the tunnel structures and disposed between the protruding portions; a barrier layer surrounding the data storage pattern and the tunneling structure; as well as a sealing layer extending through the gate structure and defining an air gap disposed between the gate lines, The air gaps each protrude into the barrier layer and the sealing layer.

18. The semiconductor device according to claim 17, wherein The tunneling structure comprises: a tunneling layer surrounding a sidewall of the channel layer; and Oxidation patterns respectively surround the tunneling layers and are disposed between the data storage patterns.

19. The semiconductor device according to claim 17, wherein The barrier layer comprises: a second barrier layer surrounding the data storage pattern and the tunneling structure; and A first barrier layer surrounds the second barrier layer and includes a recess.

20. The semiconductor device according to claim 17, wherein The sealing layer comprises: a penetrating portion extending through the gate structure; and An extension portion extends along a surface of the gate line into the gate structure.

21. A method for manufacturing a semiconductor device, the method comprising the following steps: forming a laminate including alternately stacked first and second material layers; forming a first opening extending through the stack; forming a barrier layer in the first opening; forming a data storage layer within the barrier layer; forming a slit extending through the stack; forming a second opening by etching the second material layer through the slit, the second opening exposing the barrier layer; forming a recess on a surface of the barrier layer by etching the barrier layer exposed through the second opening; as well as The data storage layer is oxidized through the recessed portion of the barrier layer.

22. The manufacturing method according to claim 21, wherein When the second opening is formed, the data storage layer is protected by the barrier layer.

23. The manufacturing method according to claim 21, wherein: In the process of etching the second material layer, the barrier layer is partially etched to form the recess.

24. The manufacturing method according to claim 21, wherein The barrier layer includes a material having a high etching selectivity with respect to the second material layer.

25. The manufacturing method according to claim 21, wherein The barrier layer includes a material having a higher dielectric constant than that of the second material layer.

26. The manufacturing method according to claim 21, wherein Each of the recesses has a circular surface.

27. The manufacturing method according to claim 21, wherein In the step of oxidizing the data storage layer, the data storage layer is partially oxidized and separated into data storage patterns.

28. The manufacturing method according to claim 21, wherein The step of forming the barrier layer comprises the following steps: forming a first barrier layer in the first opening; forming a second barrier layer within the first barrier layer, and The data storage layer is oxidized by the second barrier layer.

29. The manufacturing method according to claim 28, wherein: The first barrier layer includes a high-k material, and the second barrier layer includes a low-k material.

30. The manufacturing method according to claim 21, further comprising the following steps: forming a tunneling layer in the data storage layer; as well as A channel layer is formed in the tunnel layer.

31. The manufacturing method according to claim 21, further comprising the following steps: The first material layer is replaced with a third material layer through the slit.

32. The manufacturing method according to claim 21, further comprising the following steps: A sealing layer is formed in the slit to define an air gap in the second opening.

33. The manufacturing method according to claim 32, further comprising the following steps: A source contact structure is formed in the slit.

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