Semiconductor device

Abstract

The invention provides a semiconductor device. The semiconductor device comprises a substrate, an epitaxial layer, a plurality of semiconductor cells, a dielectric layer, a metal conductive layer and a passivation layer. Wherein the epitaxial layer is arranged on one side of the substrate, and the epitaxial layer comprises an active region and a terminal region surrounding the active region; the plurality of semiconductor cells are arranged in the active region; the dielectric layer is arranged between two adjacent semiconductor cells and on a part of the semiconductor cells, and extends to cover the terminal region from the part of the semiconductor cell closest to the terminal region; the metal conductive layer is arranged above the dielectric layer; wherein the metal conductive layer is provided with an opening, and the dielectric layer comprises an exposed part exposed from the opening; the passivation layer is located in the opening and covers the exposed portion. Specifically, compared with an existing mode of covering the whole passivation layer, the passivation layer is arranged in the opening, so that the risk of cracking of a passivation medium is greatly reduced after subsequent packaging and reliability testing, the moisture resistance of the device is ensured, and the reliability of the device is improved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a semiconductor device. Background Art

[0002] Power semiconductor devices, as core components in power electronics systems, have always been important electronic components that are indispensable to modern life. They are widely used in consumer electronic devices, automotive electronic systems, smart grids, various industrial equipment, power locomotives, aerospace, and ship systems.

[0003] Taking SiC MOSFET (silicon carbide metal oxide semiconductor field effect transistor) devices as an example, SiC MOSFET devices have become the mainstream devices in the development of high voltage and high frequency fields due to their high input impedance, good temperature stability, excellent high frequency and high voltage performance, and large safe operating area.

[0004] The SiC MOSFET manufacturing process involves both device fabrication and packaging. At the end of the device fabrication process, a passivation layer is placed above the dielectric and metal layers to block external moisture intrusion and improve device stability. The packaging process involves filling the device with plastic encapsulation compound and encapsulating it into a housing to create a packaged device.

[0005] However, during the packaging process of silicon carbide power devices, the packaged devices need to undergo reliability tests such as TCT (temperature cycling) / TS (thermal shock). Due to the mismatch in linear expansion coefficients between different material layers, such as the mismatch in linear expansion coefficients between the plastic packaging material / dielectric layer / metal layer, excessive stress can cause cracks or deformation in the passivation layer structure, thereby affecting the long-term reliability of the device. Summary of the Invention

[0006] In order to solve the above problems, the present application provides a semiconductor device that can solve the problem of cracks or deformation in the passivation layer structure.

[0007] To solve the above problems, the first technical solution provided by this application is to provide a semiconductor device, comprising:

[0008] substrate;

[0009] an epitaxial layer, disposed on one side of the substrate, the epitaxial layer comprising an active region and a terminal region surrounding the active region;

[0010] a plurality of semiconductor cells disposed in the active region and extending from the first surface of the epitaxial layer toward the substrate; wherein the first surface of the epitaxial layer is a surface of the epitaxial layer facing away from the substrate;

[0011] a dielectric layer, disposed between two adjacent semiconductor cells and on a portion of the semiconductor cells, and extending from a portion of the semiconductor cells closest to the terminal region to cover the terminal region;

[0012] a metal conductive layer disposed above the dielectric layer; wherein the metal conductive layer has an opening, and the dielectric layer includes an exposed portion exposed from the opening;

[0013] The passivation layer is located in the opening and covers the exposed portion.

[0014] To solve the above problems, the second technical solution provided by this application is to provide a semiconductor device, comprising:

[0015] substrate;

[0016] an epitaxial layer disposed on one side of the substrate, the epitaxial layer comprising an active region and a terminal region surrounding the active region; the epitaxial layer and the substrate both having a first conductivity type;

[0017] a plurality of spaced-apart first doped regions disposed within the active region and extending from a first surface of the epitaxial layer toward the substrate; wherein the first surface of the epitaxial layer is a surface of the epitaxial layer facing away from the substrate; and the first doped regions have a second conductivity type;

[0018] a plurality of second doped regions, disposed one by one in the plurality of first doped regions and extending from the first surface of the epitaxial layer toward the substrate; the second doped regions have a first conductivity type;

[0019] a plurality of third doped regions, disposed one by one in the plurality of first doped regions and connected to the second doped regions, and extending from the first surface of the epitaxial layer toward the substrate; the third doped regions have a second conductivity type;

[0020] a dielectric layer, disposed between two adjacent first doping regions and on the second doping region, and extending from a portion of the first doping region closest to the terminal region to cover the terminal region;

[0021] A metal conductive layer is disposed above the dielectric layer; wherein the metal conductive layer includes a source metal pad and a gate metal pad, and a gap is formed between the source metal pad and the gate metal pad;

[0022] The passivation layer is disposed in the gap and covers the area of the dielectric layer exposed from the gap.

[0023] The beneficial effect of the present application is that, unlike the prior art, the semiconductor device provided by the present application includes a substrate, an epitaxial layer, a plurality of semiconductor cells, a dielectric layer, a metal conductive layer, and a passivation layer. The epitaxial layer is disposed on one side of the substrate, and the epitaxial layer includes an active region and a terminal region surrounding the active region; the plurality of semiconductor cells are disposed in the active region and extend from the first surface of the epitaxial layer toward the substrate; the first surface of the epitaxial layer is the surface of the epitaxial layer facing away from the substrate; the dielectric layer is disposed between two adjacent semiconductor cells and on a portion of the semiconductor cells, and extends from the portion of the semiconductor cells closest to the terminal region to cover the terminal region; the metal conductive layer is disposed above the dielectric layer; the metal conductive layer has an opening, and the dielectric layer includes an exposed portion exposed from the opening; the passivation layer is located in the opening and covers the exposed portion. Specifically, compared with the existing method of covering the entire passivation layer, the present application sets the passivation layer within the opening, thereby effectively reducing the stress between the passivation layer and the metal layer. Such a structure greatly reduces the risk of cracking of the passivation medium after subsequent packaging and reliability testing, ensures the moisture resistance of the device, and improves the reliability of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for describing the embodiments. Obviously, the drawings described below are only some embodiments of the present application. Those skilled in the art can also derive other drawings based on these drawings without inventive work, among which:

[0025] Figure 1 A top view of the structure of a semiconductor device provided in one embodiment of the present application after removing the protective layer and the passivation layer;

[0026] Figure 2 The semiconductor device provided in one embodiment of the present application is as follows Figure 1 Cross-sectional view of line BB in FIG;

[0027] Figure 3 A semiconductor device provided in another embodiment of the present application is as follows Figure 1 Cross-sectional view of line BB in FIG;

[0028] Figure 4 A semiconductor device provided in another embodiment of the present application is as follows Figure 1 Cross-sectional view of line BB in FIG;

[0029] Figure 5 A top view of the structure of a semiconductor device provided in another embodiment of the present application after removing the protective layer and the passivation layer.

[0030] Description of labels:

[0031] Substrate 10; epitaxial layer 20; semiconductor cells 30; first doped region 31; second doped region 32; third doped region 33; dielectric layer 40; exposed portion 41; metal conductive layer 50; source metal pad 51; gate metal pad 52; passivation layer 60; first portion 61; second portion 62; field oxide layer 70; gate layer 80; gate 81; gate bus 82; protective layer 90; back metal layer 100;

[0032] Opening-A; Gap-A1; Notch-A2. DETAILED DESCRIPTION

[0033] The following will be combined with the drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0034] The terms "first," "second," and "third" in this application are used only for descriptive purposes and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first," "second," or "third" may explicitly or implicitly include at least one of such features. In the description of this application, "multiple" means at least two, for example, two, three, etc., unless otherwise specifically defined. All directional indications in the embodiments of this application (such as up, down, left, right, front, back...) are only used to explain the relative positional relationship, movement, etc. between the components under a specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indications also change accordingly. In addition, the terms "including" and "having," as well as any variations thereof, are intended to cover non-exclusive inclusions. For example, a process, method, system, product, or device that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units that are not listed, or may optionally include other steps or units that are inherent to these processes, methods, products, or devices.

[0035] References herein to "embodiments" mean that a particular feature, structure, or characteristic described in connection with the embodiments may be included in at least one embodiment of the present application. The appearance of this phrase in various places in the specification does not necessarily refer to the same embodiment, nor does it constitute an independent or alternative embodiment that is mutually exclusive of other embodiments. It is understood, both explicitly and implicitly, by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0036] In the description of the embodiments of this application, the term "and / or" is simply a description of the association relationship between associated objects, indicating that three relationships can exist. For example, A and / or B can represent the following three situations: A exists alone, A and B exist simultaneously, and B exists alone. In addition, the character " / " in this document generally indicates that the associated objects are in an "or" relationship.

[0037] In the description of the embodiments of the present application, the term "multiple" refers to more than two (including two). Similarly, "multiple groups" refers to more than two groups (including two groups), and "multiple pieces" refers to more than two pieces (including two pieces).

[0038] In the description of the embodiments of the present application, unless otherwise expressly specified or limited, technical terms such as "installed," "connected," "connected," and "fixed" should be understood in a broad sense. For example, they can refer to fixed connections, detachable connections, or integration; mechanical connections or electrical connections; direct connections or indirect connections through an intermediate medium; internal connections between two components or interactions between two components. Those skilled in the art can understand the specific meanings of the above terms in the embodiments of the present application based on specific circumstances.

[0039] See also Figure 1 and Figure 2 , Figure 1 A top view of the structure of a semiconductor device provided in one embodiment of the present application after removing the protective layer and the passivation layer; Figure 2 The semiconductor device provided in one embodiment of the present application is as follows Figure 1 Cross-sectional view of line BB in.

[0040] The present application provides a semiconductor device, including a substrate 10 , an epitaxial layer 20 , a plurality of semiconductor cells 30 , a dielectric layer 40 , a metal conductive layer 50 , and a passivation layer 60 .

[0041] The substrate 10 and the epitaxial layer 20 have a first conductivity type. One of the first conductivity type and the second conductivity type described below is P-type, and the other is N-type. For example, in this application, the first conductivity type is N-type and the second conductivity type is P-type.

[0042] The epitaxial layer 20 is disposed on one side of the substrate 10 and includes an active region and a termination region. The active region and termination region of the present application can have the same structure and function as those of conventional semiconductor devices and are not described in detail here. In the embodiment of the present application, the termination region is disposed around the active region.

[0043] Several semiconductor cells 30 are disposed within the active region and extend from the first surface of the epitaxial layer 20 toward the substrate 10. The first surface of the epitaxial layer 20 is the surface of the epitaxial layer 20 facing away from the substrate 10. The shape of the semiconductor cells 30 is not limited and can be a strip, square, or hexagonal. Multiple semiconductor cells 30 can be arranged in a one-dimensional array or a two-dimensional array.

[0044] In one embodiment, if Figure 2 As shown, each semiconductor cell 30 includes a first doping region 31, a second doping region 32, and a third doping region 33. Specifically, the first doping region 31 is disposed in the active region and extends from the first surface of the epitaxial layer 20 toward the substrate 10; the second doping region 32 is disposed in the first doping region 31 and extends from the first surface of the epitaxial layer 20 toward the substrate 10; the second doping region 32 has a first conductivity type; the third doping region 33 is disposed in the first doping region 31 and is connected to the second doping region 32, and the third doping region 33 extends from the first surface of the epitaxial layer 20 toward the substrate 10.

[0045] In other words, the semiconductor cells 30 include a plurality of first doping regions 31, a plurality of second doping regions 32, and a plurality of third doping regions 33. The second doping regions 32 are disposed one-to-one in the first doping regions 31, and the third doping regions 33 are disposed one-to-one in the first doping regions 31 and connected to the second doping regions 32.

[0046] The first doping region 31 and the third doping region 33 have the second conductivity type; the second doping region 32 has the first conductivity type.

[0047] The dielectric layer 40 is located above the epitaxial layer 20 , and is disposed between two adjacent semiconductor cells 30 and on a portion of the semiconductor cells 30 , and extends from the portion of the semiconductor cells 30 closest to the terminal region to cover the terminal region.

[0048] In one embodiment, the dielectric layer 40 is disposed between two adjacent first doped regions 31 and on the second doped region 32 , and extends from a portion of the first doped region 31 closest to the terminal region to cover the terminal region.

[0049] Specifically, the dielectric layer 40 is used to provide electrical insulation, electric field modulation, physical protection, etc. within the device. In some embodiments, the material of the dielectric layer 40 includes but is not limited to silicon dioxide, silicon nitride, aluminum oxide, polyimide, etc.

[0050] In this application, “above” refers to the direction from the substrate 10 to the epitaxial layer 20 .

[0051] The metal conductive layer 50 is disposed above the dielectric layer 40 , and the metal conductive layer 50 forms a pad structure for electrical connection with an external circuit.

[0052] In the embodiment of the present application, the metal conductive layer 50 has an opening A, the dielectric layer 40 includes an exposed portion 41 exposed from the opening A, and the passivation layer 60 is located in the opening A and covers the exposed portion 41 to block the intrusion of external water vapor and improve the stability of the device. The exposed portion 41 is exposed through the opening A relative to the metal conductive layer 50 covering the entire surface of the dielectric layer 40. For example, after the metal conductive layer 50 covers the entire surface of the dielectric layer 40, the opening A will be formed by removing part of the metal conductive layer 50. The opening A can include a through hole inside the metal conductive layer 50, a notch (groove) at the edge of the metal conductive layer 50, or a missing portion between the metal conductive layer 50 and the edge of the dielectric layer 40.

[0053] The metal conductive layer 50 has a first side surface surrounding the opening A. Side surfaces of the metal conductive layer 50 not related to the opening A are collectively referred to as the second side surfaces of the metal conductive layer 50. The passivation layer 60 being located within the opening A means that the passivation layer 60 is located on the region of the dielectric layer 40 exposed by the opening A and / or on the first side surface of the metal conductive layer 50 (hereinafter referred to as the sidewall of the opening A). In other words, the surface of the metal conductive layer 50 away from the substrate 10 is free of the passivation layer 60, and the thickness of the passivation layer 60 is less than the depth of the opening A (the thickness of the metal conductive layer 50). The passivation layer 60 covering the exposed portion 41 means that the passivation layer 60 at least covers the region of the dielectric layer 40 exposed by the opening A.

[0054] Specifically, compared with the existing method of covering the entire passivation layer, the present application sets the passivation layer 60 within the opening A, thereby effectively reducing the stress between the passivation layer 60 and the metal conductive layer 50, thereby greatly reducing the risk of cracking of the passivation medium after subsequent packaging and reliability testing, and reducing the deformation of the metal conductive layer 50 caused by stress, thereby ensuring the moisture resistance of the device and improving the reliability of the device.

[0055] In addition, compared with the existing passivation layer full layer coverage method, the structure of the passivation layer 60 of the present application only requires an additional etching process to pattern the passivation layer 60, and the design change is small, which does not affect the reliability of other projects.

[0056] It should be noted that, in the embodiment of the present application, the passivation layer 60 is not provided on the surface of the metal conductive layer 50 away from the substrate 10 , and only the passivation layer 60 in the opening A is retained.

[0057] Specifically, the passivation layer 60 covers the entire layer, and the passivation layer 60 on the surface of the metal conductive layer 50 away from the substrate 10 is removed by adding an etching process. This can reduce the risk of cracking of the passivation medium due to mismatch in linear expansion coefficients between different material layers after subsequent packaging and reliability testing, and reduce the deformation of the metal conductive layer 50 due to stress, thereby improving the reliability of the device.

[0058] In the present application, the metal conductive layer 50 includes a source metal pad 51 and a gate metal pad 52 that are insulated.

[0059] In one embodiment, the opening A includes a gap A1 between the source metal pad 51 and the gate metal pad 52, wherein the gap A1 insulates and separates the source metal pad 51 and the gate metal pad 52. The passivation layer 60 is disposed in the gap A1 and covers the area of the dielectric layer 40 exposed from the gap A1.

[0060] Source metal pad 51 has a side surface forming gap A1 and a top surface facing away from substrate 10, and the side surface of source metal pad 51 is connected to the top surface of source metal pad 51. Gate metal pad 52 has a side surface forming gap A1 and a top surface facing away from substrate 10, and the side surface of gate metal pad 52 is connected to the top surface of gate metal pad 52. The first side surface of metal conductive layer 50 includes the side surface of source metal pad 51 forming gap A1 and the side surface of gate metal pad 52 forming gap A1.

[0061] In another embodiment, the opening A includes a gap A2 between the edge of the metal conductive layer 50 and the edge of the terminal region. The passivation layer 60 is disposed in the gap A2 and covers the area of the dielectric layer 40 exposed by the gap A2.

[0062] In another embodiment, the opening A includes a gap A1 between the source metal pad 51 and the gate metal pad 52, and a notch A2 between the edge of the metal conductive layer 50 and the edge of the terminal region. The passivation layer 60 is disposed in the gap A1 and the notch A2, and covers the area of the dielectric layer 40 exposed from the gap A1 and the notch A2.

[0063] Specifically, by setting the passivation layer 60 only in the gap A1 and / or the notch A2, the stress between the passivation layer 60 and the metal conductive layer 50 can be effectively reduced, and the deformation of the metal conductive layer 50 caused by stress can be reduced, thereby greatly reducing the risk of cracking of the passivation medium after subsequent packaging and reliability testing, ensuring the moisture resistance of the device, and improving the reliability of the device.

[0064] In one embodiment, combining Figure 1 and Figure 2The passivation layer 60 covers the exposed portion 41 and does not extend to cover the sidewalls of the opening A. That is, the passivation layer 60 covers the surface of the dielectric layer 40 exposed by the opening A, and the passivation layer 60 does not extend from the sidewalls of the opening A toward the surface of the metal conductive layer 50 away from the substrate 10.

[0065] However, it should be noted that when the passivation layer 60 is only provided on the exposed portion 41 , the side surface of the passivation layer 60 may contact the side surface of the metal conductive layer 50 , but does not extend toward the side wall of the opening A to form a certain area of the passivation layer 60 .

[0066] In this application, the surface of the metal conductive layer 50 facing away from the substrate 10 is defined as the top surface of the metal conductive layer. The surface of the source metal pad 51 facing away from the substrate 10 is defined as the top surface of the source metal pad 51, and the surface of the gate metal pad 52 facing away from the substrate 10 is defined as the top surface of the gate metal pad 52.

[0067] Specifically, by setting the passivation layer 60 only on the exposed portion 41, the contact between the passivation layer 60 and the metal conductive layer 50 is reduced, and the stress between the passivation layer 60 and the metal conductive layer 50 can be effectively reduced, thereby greatly reducing the risk of cracking of the passivation medium after subsequent packaging and reliability testing, and reducing the deformation of the metal conductive layer 50 caused by stress, thereby ensuring the moisture resistance of the device and improving the reliability of the device.

[0068] In another embodiment, combined Figure 1 and Figure 3 , Figure 3 A semiconductor device provided in another embodiment of the present application is as follows Figure 1 In the cross-sectional view along line BB in FIG. 4 , the passivation layer 60 includes a first portion 61 disposed on the surface of the exposed portion 41 and a second portion 62 extending to the sidewall of the opening A.

[0069] That is, within the opening A, the passivation layer 60 also extends from the surface of the exposed portion 41 along the sidewalls of the opening A toward the top surface of the metal conductive layer 50 .

[0070] Specifically, providing the passivation layer 60 with a first portion 61 and a second portion 62 can improve the coverage of the passivation layer 60, ensure the moisture resistance of the device, and improve the reliability of the device. It can also reduce the difficulty of the process. It is understood that due to patterning process limitations, retaining only the passivation layer 60 on the surface of the exposed portion 41 requires relatively high mask accuracy and etching speed, resulting in higher costs.

[0071] Furthermore, the second portion 62 covers 5-50% of the height of the sidewall of the opening A. For example, the second portion 62 may cover 5% of the height of the sidewall of the opening A. For another example, the second portion 62 may cover 15% of the height of the sidewall of the opening A. For another example, the second portion 62 may cover 30% of the height of the sidewall of the opening A. For another example, the second portion 62 may cover 50% of the height of the sidewall of the opening A. The specific design can be based on actual conditions and is not limited here. It can be understood that the second portion 62 covering 5-50% of the height of the sidewall of the opening A can not only reduce the difficulty of the patterning process for preparing the passivation layer 60, but also retain as little passivation layer 60 as possible on the sidewall of the opening A, thereby greatly reducing the risk of cracking of the passivation medium after subsequent packaging and reliability testing, ensuring the moisture resistance of the device, and improving the reliability of the device.

[0072] The height direction refers to the direction from the substrate 10 to the epitaxial layer 20 .

[0073] It should be noted that, see Figure 3 , the sidewalls of the opening A may be inclined relative to the surface of the substrate 10, thereby reducing the mask accuracy requirements for forming the opening A. Alternatively, see Figure 4 , Figure 4 A semiconductor device provided in another embodiment of the present application is as follows Figure 1 In the cross-sectional view along line BB in FIG, the sidewall of the opening A may be perpendicular to the surface where the substrate 10 is located.

[0074] In the embodiment of the present application, the angle between the sidewall of the opening A and the substrate 10 is greater than or equal to 90° and less than or equal to 150°.

[0075] For example, the angle between the sidewall of the opening A and the substrate 10 is equal to 90°. That is, the sidewall of the opening A is perpendicular to the substrate 10 .

[0076] For another example, the angle between the sidewall of the opening A and the substrate 10 may also be 110°, 120°, 140°, or 150°. That is, the sidewall of the opening A is inclined relative to the substrate 10.

[0077] Among them, such as Figure 3 As shown, the sidewall of the opening A is set to be inclined relative to the substrate 10, and the passivation layer 60 includes a first part 61 and a second part 62. The first part 61 ensures the integrity of the passivation layer 60 at the bottom of the opening A (that is, completely covers the exposed part 41), and the second part 62 can provide process margin, reduce the difficulty of aligning the patterned mask, and thus improve the product yield.

[0078] In some embodiments, the thickness of the passivation layer 60 is less than that of the metal conductive layer 50, as long as it can meet the water vapor resistance requirements of the device. Moreover, setting the thickness of the passivation layer to be relatively small is conducive to miniaturization of the device.

[0079] The thickness of the passivation layer 60 may be 0.1-0.5 times the thickness of the metal conductive layer 50 . For example, the thickness of the passivation layer 60 may be 0.1, 0.3 or 0.5 times the thickness of the metal conductive layer 50 , which is not limited here.

[0080] In some embodiments, the thickness of the passivation layer 60 is 2000 Å-2 μm. For example, the thickness of the passivation layer 60 can be 2000 Å, 6000 Å, 1 μm, 1.4 μm, 1.8 μm, or 2 μm, etc., which is not limited here.

[0081] In some embodiments, the material of the passivation layer 60 includes, but is not limited to, at least one of silicon oxide, silicon nitride, and silicon oxynitride.

[0082] In some embodiments, the passivation layer 60 may be a single-layer structure or a multi-layer stacked structure.

[0083] Specifically, the passivation layer 60 with a single film layer structure has a simple manufacturing process and good uniformity; the passivation layer 60 with a multi-film layer stacked structure can provide better water vapor erosion resistance and stress management capabilities.

[0084] In some embodiments, the terminal region may be disposed around the active region, or may be disposed on one side of the active region, without limitation, and may be designed based on actual conditions.

[0085] like Figure 1 As shown, the terminal region is disposed around the active region, and the opening A is only disposed in the terminal region.

[0086] And as Figure 5 As shown, Figure 5 This is a top view of the structure of a semiconductor device provided by another embodiment of the present application after removing the protective layer and the passivation layer. The terminal region is arranged around the active region, and the gap A1 in the opening A is arranged in the active region.

[0087] Of course, in other embodiments, according to the requirements of the structural design of the metal conductive layer 50 , the opening A may also be provided in the active area, which is not limited here.

[0088] In some embodiments, see Figure 2 The semiconductor device further includes a field oxide layer 70 , a gate electrode layer 80 , a protective layer 90 and a back metal layer 100 .

[0089] The field oxide layer 70 is disposed between the gate electrode layer 80 and the epitaxial layer 20 to adjust the electric field distribution and achieve device isolation.

[0090] The gate electrode layer 80 is disposed on the semiconductor cell 30 and surrounded by the dielectric layer 40. The gate electrode layer 80 includes a plurality of gates 81 disposed in the active region and a gate bus 82 extending from the terminal region to the active region. Specifically, the gate metal pad 52 penetrates the dielectric layer 40 and is connected to the gate bus 82, which in turn connects to the plurality of gates 81 through the gate bus 82. The gate electrode layer 80 may be a doped polysilicon layer.

[0091] The opening A is located on a portion of the gate electrode layer 80 (ie, the gate bus 82 ) and a portion of the dielectric layer 40 in the terminal region.

[0092] Specifically, the present application prevents the passivation layer 60 from breaking or cracking at the corner where the passivation layer 60 is connected between the first side surface and the top surface of the metal conductive layer 50, thereby preventing the cracks in the passivation layer 60 from extending toward the side of the bottom epitaxial layer 20. In this way, the passivation layer 60 can isolate the conductive path between the source metal pad 51 and the gate electrode layer 80 under the exposed portion 41, thereby preventing the source metal pad 51 and the gate electrode layer 80 from contacting through the cracks in the passivation layer 60 and causing leakage.

[0093] In addition, the source metal pad 51 penetrates the dielectric layer 40 and is connected to the plurality of semiconductor cells 30 by ohmic contact.

[0094] The protective layer 90 is provided in the terminal region and covers the passivation layer 60 and the metal conductive layer 50. Specifically, the protective layer 90 can improve the insulation, dust and pollution prevention, and mechanical protection performance of the device.

[0095] In one embodiment, the protection layer 90 covers the side surfaces of the metal conductive layer 50 , extends to cover the corners where the side surfaces of the metal conductive layer 50 connect to the top surface of the metal conductive layer 50 , and a portion of the top surface of the metal conductive layer 50 , and contacts the metal conductive layer 50 .

[0096] For example, the protective layer 90 covers the corners of the connection between the side surface of the source metal pad 51 and the top surface of the source metal pad 51 and a portion of the top surface of the source metal pad 51, and covers the corners of the connection between the side surface of the gate metal pad 52 and the top surface of the gate metal pad 52 and a portion of the top surface of the gate metal pad 52; and the protective layer 90 is in contact with the source metal pad 51 and the gate metal pad 52.

[0097] Specifically, the protective layer 90 is disposed in contact with the corners of the metal conductive layer 50 (source metal pad 51 and gate metal pad 52). That is, the passivation layer 60 is not disposed at the corners of the metal conductive layer 50. This prevents the passivation layer from cracking at the corners of the metal conductive layer 50, thereby affecting device reliability. Furthermore, because the protective layer 90 is thicker at the corners of the metal conductive layer 50, cracking is essentially nonexistent, thereby not affecting the function of the protective layer 90.

[0098] The back metal layer 100 is disposed on a side of the substrate 10 away from the epitaxial layer 20 and serves as a drain of the device.

[0099] The above is only an implementation method of the present application and does not limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made using the contents of the description and drawings of this application, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. A semiconductor device, characterized in that: include: substrate; an epitaxial layer, disposed on one side of the substrate, the epitaxial layer comprising an active region and a terminal region surrounding the active region; a plurality of semiconductor cells disposed in the active region and extending from the first surface of the epitaxial layer toward the substrate; wherein the first surface of the epitaxial layer is a surface of the epitaxial layer facing away from the substrate; a dielectric layer, disposed between two adjacent semiconductor cells and on a portion of the semiconductor cells, and extending from a portion of the semiconductor cells closest to the terminal region to cover the terminal region; a metal conductive layer disposed above the dielectric layer; wherein the metal conductive layer has an opening, and the dielectric layer includes an exposed portion exposed from the opening; The passivation layer is located in the opening and covers the exposed portion.

2. The semiconductor device according to claim 1, wherein The metal conductive layer has a first side surface surrounding the opening. The passivation layer covers the exposed portion and does not extend to cover the first side surface of the metal conductive layer.

3. The semiconductor device according to claim 1, wherein The metal conductive layer has a first side surface surrounding the opening, and the passivation layer includes a first portion disposed on a surface of the exposed portion and a second portion extending to the first side surface of the metal conductive layer.

4. The semiconductor device according to claim 3, wherein The second portion covers 5-50% of the height of the first side surface of the metal conductive layer.

5. The semiconductor device according to claim 3, wherein The metal conductive layer further includes a top surface facing away from the substrate, wherein the top surface is connected to the first side surface; the semiconductor device further includes a protective layer; The protection layer covers the first side surface of the metal conductive layer and extends to cover a corner where the first side surface of the metal conductive layer is connected to the top surface of the metal conductive layer and a portion of the top surface of the metal conductive layer.

6. The semiconductor device according to any one of claims 2 to 5, characterized in that: An included angle between the first side surface of the metal conductive layer and the substrate is greater than or equal to 90° and less than or equal to 150°.

7. The semiconductor device according to any one of claims 1 to 5, wherein: The metal conductive layer includes a source metal pad and a gate metal pad; The opening includes a gap between the source metal pad and the gate metal pad; and / or The opening includes a gap between an edge of the metal conductive layer and an edge of the terminal region.

8. The semiconductor device according to any one of claims 1 to 5, wherein: The opening is provided in the terminal region; the semiconductor device further comprises: The protection layer is disposed in the terminal region and covers the passivation layer and the metal conductive layer.

9. The semiconductor device according to any one of claims 1 to 5, characterized in that: The thickness of the passivation layer is less than the thickness of the metal conductive layer; and the thickness of the passivation layer is 0.1-0.5 times the thickness of the metal conductive layer; The passivation layer is a single-layer structure; Or the passivation layer is a multi-layer stacked structure.

10. The semiconductor device according to claim 1, wherein The semiconductor device further includes: a gate electrode layer, the gate electrode layer being disposed on the semiconductor cell and surrounded by the dielectric layer; The opening is located on a portion of the gate electrode layer and a portion of the dielectric layer in the terminal region.

11. A semiconductor device, characterized in that: include: substrate; an epitaxial layer, disposed on one side of the substrate, the epitaxial layer comprising an active region and a terminal region surrounding the active region; The epitaxial layer and the substrate both have a first conductivity type; a plurality of spaced-apart first doped regions disposed within the active region and extending from a first surface of the epitaxial layer toward the substrate; wherein the first surface of the epitaxial layer is a surface of the epitaxial layer facing away from the substrate; and the first doped regions have a second conductivity type; a plurality of second doped regions, disposed one by one in the plurality of first doped regions and extending from the first surface of the epitaxial layer toward the substrate; the second doped regions have a first conductivity type; a plurality of third doped regions, disposed one by one in the plurality of first doped regions and connected to the second doped regions, and extending from the first surface of the epitaxial layer toward the substrate; the third doped regions have a second conductivity type; a dielectric layer, disposed between two adjacent first doping regions and on the second doping region, and extending from a portion of the first doping region closest to the terminal region to cover the terminal region; A metal conductive layer is disposed above the dielectric layer; wherein the metal conductive layer includes a source metal pad and a gate metal pad, and a gap is formed between the source metal pad and the gate metal pad; A passivation layer is disposed in the gap and covers the region of the dielectric layer exposed from the gap.

12. The semiconductor device according to claim 11, wherein The passivation layer does not extend to cover the side surfaces of the source metal pad and the gate metal pad.

13. The semiconductor device according to claim 11, wherein The passivation layer includes a first portion disposed on a surface of the dielectric layer in an area exposed from the gap, and a second portion extending to a side surface of the source metal pad and a side surface of the gate metal pad.

14. The semiconductor device according to claim 13, wherein: The source metal pad includes a side surface forming the gap and a top surface facing away from the substrate; the gate metal pad includes a side surface forming the gap and a top surface facing away from the substrate; The semiconductor device also includes a protective layer; the protective layer covers the corners of the connection between the side surface of the source metal pad and the top surface of the source metal pad and a portion of the top surface of the source metal pad, and covers the corners of the connection between the side surface of the gate metal pad and the top surface of the gate metal pad and a portion of the top surface of the gate metal pad; and the protective layer is in contact with the source metal pad and the gate metal pad.

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