Silicon carbide MOSFET structure with high short circuit capability and preparation method thereof
By introducing back-to-back bench type P-well and self-aligned ion implantation process into the SiC MOSFET structure, the bottlenecks in short-circuit reliability and conduction performance of SiC MOSFETs are solved, and the compatibility of high short-circuit capability and low on-resistance is improved, which is suitable for large-scale production.
Patent Information
- Application Number
- CN202510823691.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-06-18
- Publication Date
- 2025-08-12
AI Technical Summary
The existing silicon carbide MOSFET structures have bottlenecks in terms of short-circuit reliability and conduction performance. The traditional structure has a large saturation current in the short-circuit conditions and is prone to overheating failure. Complex processes or new masking steps lead to poor compatibility with mainstream preparation processes and high production costs.
The high-short-circuit capability silicon carbide MOSFET structure is adopted, including multiple periodically repeated back-to-back bench type P wells to form a narrow lower and wide JFET structure, and is realized through a self-aligned ion implantation process without increasing the number of mask plates. The device design is optimized by combining the MOS structure and interlayer dielectric isolation.
It significantly improves the short circuit capability of the device, reduces saturation current, extends the safe working time of short circuit, reduces on-resistance, maintains the dynamic resistance characteristics of high voltage, high resistance and on-resistance, and reduces process complexity and manufacturing costs, making it suitable for large-scale mass production.
Smart Images
Figure CN120475744A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of semiconductor structures, and in particular to a high short-circuit capability silicon carbide MOSFET structure and a preparation method thereof. Background Art
[0002] In the field of power semiconductor devices, silicon carbide (SiC) MOSFET has become a core device for high-voltage, high-temperature, and high-frequency applications due to its high breakdown voltage, low conduction loss, and high-frequency characteristics. As a third-generation semiconductor material, silicon carbide has advantages such as wide bandgap, high breakdown field strength, and high thermal conductivity. The new generation of spacecraft has higher requirements for energy conversion efficiency, volume, and weight. Traditional silicon (Si) devices have gradually failed to meet application requirements. Therefore, SiC power devices, especially SiC MOSFET, are expected to become the first choice for the next generation of spacecraft systems. However, the existing silicon carbide MOSFET structure faces the following technical bottlenecks in terms of short-circuit reliability and conduction performance:
[0003] Traditional structures experience high saturation currents under short-circuit conditions, making them susceptible to device failure due to overheating, limiting their application in high-reliability scenarios. To avoid channel punchthrough under high-voltage bias, a long channel length is required, resulting in higher channel resistance and overall device on-resistance, impacting energy efficiency. Existing high-reliability structures often rely on complex processes or additional masking steps, making them incompatible with mainstream fabrication processes and increasing production costs. Summary of the Invention
[0004] The purpose of the present invention is to provide a high short-circuit capability silicon carbide MOSFET structure and a preparation method thereof, so as to solve the above problems.
[0005] To achieve the above object, a high short-circuit capability silicon carbide MOSFET structure is provided, comprising a drain metal, an N substrate is provided on the drain metal, and an N - Drift region; the N - An N-type carrier storage layer is provided on the drift region, and a MOS structure, an interlayer dielectric and a source metal layer are provided on the N-type carrier storage layer; wherein, a plurality of periodically repeated back-to-back bench-type P-wells are provided in the N-type carrier storage layer, and adjacent back-to-back bench-type P-wells form a JFET structure that is narrow at the bottom and wide at the top; the JFET structure forms an enhanced pinch-off capability near the bottom of the P-well, so that the saturation current of the device under high-voltage bias state is reduced, thereby improving the short-circuit capability of the device; the pinch-off capability produces an electric field shielding effect, shortening the channel length while avoiding channel punch-through, thereby reducing the channel resistance and the device on-resistance.
[0006] Preferably, in the above-mentioned high short-circuit capability silicon carbide MOSFET structure, the back-to-back bench-type P-well region is provided with an N+ Well region and P + District, the N + A channel region is formed between the boundary of the well region and the boundary of the P-well.
[0007] Preferably, in the above-mentioned high short-circuit capability silicon carbide MOSFET structure, the MOS structure includes polycrystalline silicon, a thin layer of silicon dioxide is provided between the polycrystalline silicon and the silicon carbide semiconductor as a gate dielectric, and the polycrystalline silicon, the gate dielectric and the silicon carbide semiconductor together constitute the MOS structure; the source metal and the P + District, N + The well region is connected; the source metal and the MOS structure are separated by an interlayer dielectric; and the channel region is located below the polysilicon of the MOS structure.
[0008] A method for preparing the above-described high short-circuit capability silicon carbide MOSFET structure is compatible with existing mainstream manufacturing processes and is achieved by changing the layout pattern and adding a self-aligned ion implantation process without increasing the number of masks. The method specifically includes the following steps:
[0009] S1. Using a mask to define the bottom pattern of a back-to-back bench-type P-well on the surface of a silicon carbide MOSFET epitaxial wafer, and forming the bottom morphology of the back-to-back bench-type P-well by high-energy Al ion implantation;
[0010] S2. Based on S1, polysilicon is deposited by LPCVD, and the polysilicon is anisotropically etched to form a self-aligned mask pattern of a back-to-back bench-shaped P-well "chair back". The "chair back" morphology is formed by high-energy Al ion implantation;
[0011] S3, based on S2, continue to deposit polysilicon by LPCVD, and anisotropically etch the polysilicon to form N + The self-aligned mask pattern of the well region is formed by high-energy N ion implantation. + well region and channel region;
[0012] S4. The remaining processes adopt the existing mainstream preparation processes.
[0013] Preferably, in the above method for preparing a silicon carbide MOSFET structure with high short-circuit capability, in step S2, the thickness of the polysilicon is determined according to the width of the bench surface of the bench-type P-well.
[0014] Preferably, in the above method for preparing a silicon carbide MOSFET structure with high short-circuit capability, in step S3, the thickness of the polysilicon is determined according to the length of the channel region.
[0015] Therefore, the present invention adopts the above-mentioned high short-circuit capability silicon carbide MOSFET structure and its preparation method, breaks through the bottleneck of the existing technology through the back-to-back bench-type P-well structure design and self-aligned ion implantation process optimization, and achieves the following beneficial effects:
[0016] Adjacent back-to-back bench-type P-wells form a JFET structure that is narrow at the bottom and wide at the top, creating a stronger electric field concentration effect near the bottom of the P-well. This allows the device to quickly pinch off the conductive channel when biased at high voltage, significantly reducing the saturation current, significantly improving the device's ability to withstand short-circuit currents, and extending the short-circuit safe operating time. The enhanced pinch-off capability forms an electric field shield, effectively suppressing the diffusion of the electric field under high voltage into the channel region, avoiding the risk of channel punch-through, and providing a structural basis for shortening the channel length. The narrow-at-bottom-and-wide-at-top JFET structure maintains a high-resistance state when pinched off at high voltage, and provides a low-resistance current path through the wider upper region when normally on, achieving the dynamic resistance characteristics of "high resistance at high voltage, low resistance on-state."
[0017] Through a self-aligned ion implantation process, a back-to-back bench-shaped P-well structure is achieved without increasing the number of masks. This structure is fully compatible with existing mainstream SiC MOSFET processes (such as LPCVD deposition and anisotropic etching), reducing process complexity and manufacturing costs. Simply by adjusting parameters such as the bench width and backrest height of the bench-shaped P-well in the layout, the JFET pinch-off capability and channel length can be flexibly adjusted to accommodate device designs with different voltage levels and on-resistance requirements, improving process versatility.
[0018] The source metal is isolated from the MOS structure by the interlayer dielectric to avoid the risk of electrical short circuit; + Area and N + The ohmic contact design in the well region ensures low contact resistance, while the MOS structure of polysilicon-gate dielectric-silicon carbide semiconductors enables efficient gate control. The periodic back-to-back bench-shaped P-well array within the N-type carrier storage layer enables large-area device integration through standardized layout replication, improving cell consistency while simplifying process debugging and making it suitable for large-scale mass production.
[0019] The technical solution of the present invention is further described in detail below through the accompanying drawings and embodiments. BRIEF DESCRIPTION OF THE DRAWINGS
[0020] Figure 1 This is a schematic diagram of the overall structure of a high short-circuit capability silicon carbide MOSFET structure of the present invention. DETAILED DESCRIPTION
[0021] In order to better understand the above technical solution, the above technical solution will be described in detail below in conjunction with the accompanying drawings and specific implementation methods. Obviously, the embodiments described are only part of the embodiments of the present invention, not all of them. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.
[0022] The terms used in the embodiments of the present invention are for the purpose of describing specific embodiments only and are not intended to limit the present invention. The singular forms "a," "an," "the," and "the" used in the embodiments of the present invention and the appended claims are also intended to include plural forms, and unless the context clearly indicates otherwise, "a plurality" generally includes at least two.
[0023] It should also be noted that the terms "include," "comprises," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a product or device comprising a series of elements includes not only those elements but also other elements not explicitly listed, or elements inherent to such product or device. In the absence of further limitations, an element defined by the phrase "comprises a..." does not exclude the presence of other identical elements in the product or device comprising the element.
[0024] Example 1
[0025] See Figure 1 As shown, a high short-circuit capability silicon carbide MOSFET structure is provided, comprising a drain metal 1, an N substrate 2 is provided on the drain metal 1, and an N - Drift region 3; the N - An N-type carrier storage layer 4 is provided on the drift region 3, and a MOS structure, an interlayer dielectric 5 and a source metal layer 6 are provided on the N-type carrier storage layer 4; wherein, a plurality of periodically repeated back-to-back bench-type P-wells 41 are provided in the N-type carrier storage layer 4, and adjacent back-to-back bench-type P-wells 41 form a JFET structure that is narrow at the bottom and wide at the top; the JFET structure forms an enhanced pinch-off capability near the bottom of the P-well, so that the saturation current of the device under high-voltage bias state is reduced, thereby improving the short-circuit capability of the device; the pinch-off capability produces an electric field shielding effect, shortening the channel length while avoiding channel punch-through, thereby reducing the channel resistance and the device on-resistance.
[0026] Specifically, the back-to-back bench type P well 41 area is provided with N + Well region 42 and P + Area 43, the N +A channel region 44 is formed between the boundary of the well region 42 and the boundary of the P well. The MOS structure includes polysilicon 7, a thin layer of silicon dioxide is provided between the polysilicon 7 and the silicon carbide semiconductor as a gate dielectric, and the polysilicon 7, the gate dielectric and the silicon carbide semiconductor together constitute the MOS structure; the source metal 6 and the P well are connected. + Area 43, N + The well region 42 is connected; the source metal 6 is separated from the MOS structure by an interlayer dielectric 5; and the channel region 44 is located below the polysilicon of the MOS structure.
[0027] This embodiment clarifies the spatial position relationship of each functional layer, as well as the specific structures of the back-to-back bench-type P well 41, JFET structure, and MOS structure. It defines the periodic repetitive arrangement of the back-to-back bench-type P well, clarifies the geometric characteristics of the JFET structure of "narrow at the bottom and wide at the top", and the channel region 44, N + Well region 42, P + The position of region 43 is associated. The JFET structure, which is narrow at the bottom and wide at the top, forms a local high electric field area at the bottom of the P-well. When biased at high voltage, it can quickly pinch off the conductive channel, reduce the saturation current, extend the short-circuit safe working time, and prevent the device from failing due to overheating. The enhanced pinch-off capability forms an electric field shielding layer at the bottom of the P-well, which inhibits the diffusion of the electric field to the channel area under high voltage, prevents the channel from punching through, and provides structural protection for shortening the channel length. The wider area on the upper part of the JFET structure provides a low-resistance current path when normally turned on, avoiding the increase in on-resistance caused by the narrowing of the entire area of the traditional JFET structure, and realizing the dual-state resistance characteristics of "high resistance when pinched off at high voltage, low resistance when normally turned on". The source metal is separated from the MOS structure by the interlayer dielectric to avoid the risk of electrical short circuit; P + Area 43 and N + The ohmic contact design of the well region 42 ensures low contact resistance and improves current conduction efficiency.
[0028] Example 2
[0029] A method for fabricating a high short-circuit capability silicon carbide MOSFET structure is provided. The method is compatible with existing mainstream fabrication processes and is achieved by changing the layout pattern and adding a self-aligned ion implantation process without increasing the number of masks. The method specifically includes the following steps:
[0030] S1. Using a mask to define the bottom pattern of the back-to-back bench-shaped P-well 41 on the surface of the silicon carbide MOSFET epitaxial wafer, and forming the bottom morphology of the back-to-back bench-shaped P-well 41 by high-energy Al ion implantation;
[0031] S2. Based on S1, polysilicon is deposited by LPCVD, and the polysilicon is anisotropically etched to form a self-aligned mask pattern of a back-to-back bench-shaped P well 41 "chair back", and the "chair back" morphology is formed by high-energy Al ion implantation;
[0032] S3, based on S2, continue to deposit polysilicon by LPCVD, and anisotropically etch the polysilicon to form N + The self-aligned mask pattern of the well region 42 is formed by high energy N ion implantation. + a well region 42 and a channel region 44;
[0033] S4. The remaining processes adopt the existing mainstream preparation processes.
[0034] In step S2 , the thickness of the polysilicon is determined according to the bench surface width of the bench-type P-well.
[0035] In step S3 , the thickness of the polysilicon is determined according to the length of the channel region.
[0036] This embodiment uses a self-aligned process to achieve structural innovation only by adjusting the layout pattern. Compared with the traditional process, it saves the mask and reduces the plate making cost. Mainstream process links such as anisotropic etching are retained, and there is no need to modify the existing production line. The process adaptation cycle is shortened to 1-2 months, which is suitable for rapid mass production. The "chair back" mask formed by polysilicon etching is self-aligned with the bottom pattern of the P well to ensure the geometric accuracy of the narrow and wide JFET structure, avoiding the fluctuation of the pinch-off ability caused by the alignment error of the traditional photolithography process. The secondary deposited polysilicon 7 mask accurately defines the N + The position of the well region 42 reduces the overlap error between the channel region 44 and the polysilicon gate, improves the gate control efficiency, and reduces the gate leakage current; the self-alignment process reduces the number of photolithography times, reduces the risk of particle contamination, and maintains the device yield at the current level; the precise control of ion implantation energy and dose ensures that the P well 43 and N + The uniform doping concentration of the well region 42 avoids early failure caused by local conductive anomalies.
[0037] Therefore, the present invention adopts the above-mentioned high short-circuit capability silicon carbide MOSFET structure and its preparation method, and forms a JFET structure with a narrow bottom and a wide top through adjacent back-to-back bench-type P-wells, forming a stronger electric field concentration effect near the bottom of the P-well, so that the device can quickly pinch off the conductive channel when biased at high voltage, greatly reducing the saturation current, significantly improving the device's ability to withstand short-circuit current, and extending the short-circuit safe working time. The enhanced pinch-off capability forms an electric field shielding layer, effectively inhibiting the electric field under high voltage from diffusing to the channel area, avoiding the risk of channel punch-through, and providing a structural basis for shortening the channel length. The JFET structure with a narrow bottom and a wide top maintains a high-resistance state when pinched off at high voltage, and provides a low-resistance current path through the wider upper area when normally turned on, realizing the dynamic resistance characteristics of "high resistance at high voltage, low resistance when turned on". Through the self-aligned ion implantation process, the back-to-back bench-type P-well structure is realized without increasing the number of mask plates, which is fully compatible with the existing mainstream processes of silicon carbide MOSFET (such as LPCVD deposition and anisotropic etching), reducing process complexity and manufacturing costs. By simply adjusting the bench width, back height and other parameters of the bench-shaped P-well in the layout, the JFET pinch-off capability and channel length can be flexibly controlled to adapt to device designs with different voltage levels and on-resistance requirements, thereby improving process versatility. The source metal is isolated from the MOS structure by an interlayer dielectric to avoid the risk of electrical short circuits; P + Area and N + The ohmic contact design in the well region ensures low contact resistance, while the MOS structure of polysilicon-gate dielectric-silicon carbide semiconductors enables efficient gate control. The periodic back-to-back bench-shaped P-well array within the N-type carrier storage layer enables large-area device integration through standardized layout replication, improving cell consistency while simplifying process debugging and making it suitable for large-scale mass production.
[0038] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention rather than to limit the same. Although the present invention has been described in detail with reference to the preferred embodiments, those skilled in the art should understand that they can still modify or replace the technical solutions of the present invention with equivalents, and these modifications or equivalent replacements cannot cause the modified technical solutions to deviate from the spirit and scope of the technical solutions of the present invention.
Claims
1. A high short-circuit capability silicon carbide MOSFET structure, characterized in that: The drain metal includes an N substrate disposed on the drain metal, and an N substrate disposed on the N substrate. - Drift region; the N - An N-type carrier storage layer is provided on the drift region, and a MOS structure, an interlayer dielectric and a source metal layer are provided on the N-type carrier storage layer; wherein, a plurality of periodically repeated back-to-back bench-type P-wells are provided in the N-type carrier storage layer, and adjacent back-to-back bench-type P-wells form a JFET structure that is narrow at the bottom and wide at the top; the JFET structure forms an enhanced pinch-off capability near the bottom of the P-well, so that the saturation current of the device under high-voltage bias state is reduced, thereby improving the short-circuit capability of the device; the pinch-off capability produces an electric field shielding effect, shortening the channel length while avoiding channel punch-through, thereby reducing the channel resistance and the device on-resistance.
2. A high short-circuit capability silicon carbide MOSFET structure according to claim 1, characterized in that: The back-to-back bench-type P well region is provided with an N + Well region and P + District, the N + A channel region is formed between the boundary of the well region and the boundary of the P-well.
3. A high short-circuit capability silicon carbide MOSFET structure according to claim 2, characterized in that: The MOS structure includes polycrystalline silicon, a thin layer of silicon dioxide is provided between the polycrystalline silicon and the silicon carbide semiconductor as a gate dielectric, and the polycrystalline silicon, the gate dielectric and the silicon carbide semiconductor together constitute the MOS structure; The source metal and the P + District, N + The well region is connected; the source metal and the MOS structure are separated by an interlayer dielectric; and the channel region is located below the polysilicon of the MOS structure.
4. A method for preparing a high short-circuit capability silicon carbide MOSFET structure according to any one of claims 1 to 3, characterized in that: The preparation method is compatible with existing mainstream preparation processes and is achieved by changing the layout pattern and adding a self-aligned ion implantation process without increasing the number of masks. The method specifically includes the following steps: S1. Using a mask to define the bottom pattern of a back-to-back bench-type P-well on the surface of a silicon carbide MOSFET epitaxial wafer, and forming the bottom morphology of the back-to-back bench-type P-well by high-energy Al ion implantation; S2. Based on S1, polysilicon is deposited by LPCVD, and the polysilicon is anisotropically etched to form a self-aligned mask pattern of a back-to-back bench-shaped P-well "chair back". High-energy Al ion implantation is then used to form the "chair back" morphology. S3, based on S2, continue to deposit polysilicon by LPCVD, and anisotropically etch the polysilicon to form N + The self-aligned mask pattern of the well region is formed by high-energy N ion implantation. + well region and channel region; S4. The remaining processes adopt the existing mainstream preparation processes.
5. The method for preparing a high short-circuit capability silicon carbide MOSFET structure according to claim 4, characterized in that: In step S2 , the thickness of the polysilicon is determined according to the bench surface width of the bench-type P-well.
6. The method for preparing a high short-circuit capability silicon carbide MOSFET structure according to claim 4, characterized in that: In step S3 , the thickness of the polysilicon is determined according to the length of the channel region.