Silicon carbide device and forming method thereof

Abstract

The invention provides a silicon carbide device and a forming method thereof, and the silicon carbide device comprises a silicon carbide substrate, a silicon carbide epitaxial layer is formed on the surface of the silicon carbide substrate, a drift region is formed in the silicon carbide epitaxial layer, and a groove is formed in the drift region; the diffusion layer is located at the bottom and the side wall of the groove and on the surface of the drift region, and the doping type of the diffusion layer is opposite to that of the drift region; the doping layer is located on the surface of the diffusion layer, and the doping type of the doping layer is opposite to that of the drift region; the trench is filled with the isolation structure; and the MOS transistor structure takes the doped layers on the surfaces of the drift regions on the two sides of the isolation structure as channels. According to the silicon carbide device and the forming method thereof, the diffusion layer is formed in the groove of the drift region so as to form the super junction structure, and the performance of the device can be improved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a silicon carbide device and a method for forming the same. Background Art

[0002] Silicon carbide (SiC) MOSFETs are semiconductor devices that differ from traditional silicon substrates and horizontal channels. However, the current manufacturing process for SiC devices still has flaws. For example, the application of superjunction structures in SiC devices has not yet emerged and developed.

[0003] Therefore, it is necessary to provide a more effective and reliable technical solution to achieve the formation of super junction structure in silicon carbide devices. Summary of the Invention

[0004] The present application provides a silicon carbide device and a method for forming the same, wherein a diffusion layer is formed in a trench in a drift region to form a super junction structure, which can improve device performance.

[0005] One aspect of the present application provides a method for forming a silicon carbide device, comprising: providing a silicon carbide substrate, a silicon carbide epitaxial layer formed on the surface of the silicon carbide substrate, a drift region formed in the silicon carbide epitaxial layer, and a trench formed in the drift region; forming a doping layer at the bottom and sidewalls of the trench and on the surface of the drift region, the doping type of the doping layer being opposite to the doping type of the drift region; performing an annealing process to diffuse doped ions in the doping layer into the drift region to form a diffusion layer; forming an isolation structure filling the trench; and forming a MOS transistor structure using the doping layers on the surfaces of the drift regions on both sides of the isolation structure as channels.

[0006] In some embodiments of the present application, the material of the doping layer includes BSG or PSG, the annealing process includes microwave annealing, and the temperature of the microwave annealing is greater than 2000 degrees Celsius.

[0007] In some embodiments of the present application, the material of the doping layer includes boron-doped amorphous silicon carbide or aluminum-doped amorphous silicon carbide, and the annealing process includes high-temperature annealing, and the temperature of the high-temperature annealing is greater than 2000 degrees Celsius.

[0008] In some embodiments of the present application, the material of the doping layer includes phosphoric acid or boric acid, and the annealing process includes laser annealing.

[0009] In some embodiments of the present application, after the annealing process is performed, the doping concentration of the doping layer is 6E16 to 1E19 cm -3 .

[0010] Another aspect of the present application provides a silicon carbide device, comprising: a silicon carbide substrate, a silicon carbide epitaxial layer formed on the surface of the silicon carbide substrate, a drift region formed in the silicon carbide epitaxial layer, and a groove formed in the drift region; a diffusion layer located at the bottom and sidewalls of the groove and the surface of the drift region, the doping type of the diffusion layer being opposite to the doping type of the drift region; a doping layer located on the surface of the diffusion layer, the doping type of the doping layer being opposite to the doping type of the drift region; an isolation structure filling the groove; and a MOS transistor structure, with the doping layers on the surfaces of the drift region on both sides of the isolation structure serving as channels.

[0011] In some embodiments of the present application, the material of the doping layer includes BSG or PSG.

[0012] In some embodiments of the present application, the material of the doping layer includes boron-doped amorphous silicon carbide or aluminum-doped amorphous silicon carbide.

[0013] In some embodiments of the present application, the material of the doping layer includes phosphoric acid or boric acid.

[0014] In some embodiments of the present application, the doping concentration of the doping layer is 6E16 to 1E19 cm -3 .

[0015] The present application provides a silicon carbide device and a method for forming the same, wherein a diffusion layer is formed in a trench in a drift region to form a super junction structure, which can improve device performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The following figures describe in detail exemplary embodiments disclosed in this application. Like reference numerals denote similar structures throughout the several views of the drawings. Those skilled in the art will appreciate that these embodiments are non-limiting, exemplary embodiments, and that the drawings are provided for illustration and description purposes only and are not intended to limit the scope of this application. Other embodiments may also achieve the inventive intent of this application. It should be understood that the drawings are not drawn to scale.

[0017] in:

[0018] Figures 1 to 6 This is a schematic structural diagram of each step in the method for forming a silicon carbide device described in an embodiment of the present application. DETAILED DESCRIPTION

[0019] The following description provides specific application scenarios and requirements of the present application, with the purpose of enabling those skilled in the art to make and use the content of this application. Various local modifications to the disclosed embodiments will be apparent to those skilled in the art, and the general principles defined herein may be applied to other embodiments and applications without departing from the spirit and scope of this application. Therefore, this application is not limited to the embodiments shown, but is intended to be of the widest scope consistent with the claims.

[0020] The technical solution of the present invention is described in detail below with reference to the embodiments and drawings.

[0021] Figures 1 to 6 The following is a structural diagram of each step in the method for forming a silicon carbide device according to an embodiment of the present application. The method for forming a silicon carbide device according to an embodiment of the present application is described in detail with reference to the accompanying drawings.

[0022] refer to Figure 1 As shown, a silicon carbide substrate 100 is provided. A silicon carbide epitaxial layer 110 is formed on the surface of the silicon carbide substrate 100 . A drift region 120 is formed in the silicon carbide epitaxial layer 110 . A trench 130 is formed in the drift region 120 .

[0023] The semiconductor structure described in the embodiments of the present application is a silicon carbide device MOSFET with a super junction structure. The material of the silicon carbide substrate 100 is silicon carbide material, and the material of the silicon carbide epitaxial layer 110 is also silicon carbide material. In some embodiments of the present application, the silicon carbide substrate 100 and the silicon carbide epitaxial layer 110 may have doping ions, such as N-type doping ions. The drift region 120 (drift area) can be formed by an ion implantation process in the silicon carbide epitaxial layer 110, and the doping type of the drift region 120 is the same as that of the silicon carbide epitaxial layer 110, for example, N-type. The doping concentration of the drift region 120 is lower than the doping concentration of the silicon carbide epitaxial layer 110.

[0024] refer to Figure 2 As shown, a doping layer 140 is formed at the bottom and sidewalls of the trench 130 and on the surface of the drift region 120. The doping type of the doping layer 140 is opposite to that of the drift region 120 (e.g., P-type). The function of the doping layer 140 is to provide doping ions, which are subsequently diffused into the drift region 120 through an annealing process.

[0025] In some embodiments of the present application, the material of the doping layer 140 includes BSG (boron-doped silicate glass) or PSG (phosphorus-doped silicate glass).

[0026] In some embodiments of the present application, the material of the doping layer 140 includes boron-doped amorphous silicon carbide or aluminum-doped amorphous silicon carbide.

[0027] In some embodiments of the present application, the material of the doping layer 140 includes phosphoric acid or boric acid.

[0028] In some embodiments of the present application, the thickness of the portion of the doped layer 140 located on the surface of the drift region 120 is greater than the thickness of the portion of the doped layer 140 located at the bottom and sidewalls of the trench 120. This is because a MOS transistor structure will be formed on the portion of the doped layer 140 located on the surface of the drift region 120 later.

[0029] refer to Figure 3 As shown, an annealing process is performed to diffuse the dopant ions in the doping layer 140 into the drift region 120 to form a diffusion layer 150. The dopant ions in the diffusion layer 150 originate from the doping layer 140, and therefore the doping type of the diffusion layer 150 is opposite to that of the drift region 120 (e.g., P-type). The diffusion layer 150 forms a superjunction structure with the drift region 120. In the technical solution of this application, the type of annealing process is related to the material of the doping layer 140.

[0030] In some embodiments of the present application, when the material of the doping layer 140 includes BSG or PSG, the annealing process includes microwave annealing, and the temperature of the microwave annealing is greater than 2000 degrees Celsius.

[0031] In some embodiments of the present application, when the material of the doping layer 140 includes boron-doped amorphous silicon carbide or aluminum-doped amorphous silicon carbide, the annealing process includes thermal annealing, and the temperature of the high temperature annealing is greater than 2000 degrees Celsius.

[0032] In some embodiments of the present application, when the material of the doping layer 140 includes phosphoric acid or boric acid, the annealing process includes laser annealing (Tilted Laser anneal).

[0033] In some embodiments of the present application, after the annealing process, the doping concentration of the doping layer 140 is 6E16 to 1E19 cm -3 .

[0034] In some embodiments of the present application, the doping concentration of the diffusion layer 150 is 6E16 to 1E19 cm -3 .

[0035] refer to Figure 4As shown, an isolation structure 160 is formed to fill the trench 130. The material of the isolation structure 160 includes an electrically insulating material such as silicon oxide. The isolation structure 160 may also be a conductive electrode material. The isolation material 160 may also be a thermal insulation material. In some embodiments of the present application, the material of the isolation structure 160 includes any one or more of aluminum oxide and silicon oxide.

[0036] In some embodiments of the present application, the isolation structure 160 includes a first isolation layer and a second isolation layer sequentially located on the surface of the trench, the material of the first isolation layer includes silicon oxide, and the material of the second isolation layer includes aluminum oxide.

[0037] refer to Figure 5 As shown, a MOS transistor structure 170 is formed by using the doping layer 140 on the surface of the drift region 120 on both sides of the isolation structure 160 as a channel.

[0038] In some embodiments of the present application, the MOS transistor structure 170 includes a gate structure 172 located on the surface of the doped layer 140, source regions 171 located in the doped layer 140 on both sides of the gate structure 172, and isolation regions (not shown) that isolate adjacent source regions 171. The gate structure 172 may include a gate located on the surface of the doped layer 140 and an insulating layer covering the sidewalls and top surface of the gate. The insulating layer is used to insulate and isolate the gate from subsequent metal layers, so that the metal layers can be electrically connected to the source regions 151 but not electrically connected to the gate.

[0039] refer to Figure 6 As shown, a metal layer 180 is formed on the doped layer 140 to cover the MOS transistor structure 170 and the doped layer 140. The metal layer 180 acts as a source metal to electrically connect the source region 151 and the doped layer 140, but is not electrically connected to the gate in the gate structure 152.

[0040] In some embodiments of the present application, the material of the metal layer 180 includes any one or more of titanium nitride, tungsten, or titanium silicide. The metal layer 180 can solve the heat dissipation problem of the device and improve the device performance.

[0041] The present application provides a method for forming a silicon carbide device, which forms a diffusion layer in a trench in a drift region to form a super junction structure, thereby improving device performance.

[0042] The embodiment of the present application also provides a silicon carbide device, referring to Figure 6As shown, it includes: a silicon carbide substrate 100, a silicon carbide epitaxial layer 110 is formed on the surface of the silicon carbide substrate 100, a drift region 120 is formed in the silicon carbide epitaxial layer 110, and a trench is formed in the drift region 120; a diffusion layer 150 is located at the bottom and sidewalls of the trench and the surface of the drift region 120, and the doping type of the diffusion layer 150 is opposite to the doping type of the drift region 120; a doping layer 140 is located on the surface of the diffusion layer 150, and the doping type of the doping layer 140 is opposite to the doping type of the drift region 120; an isolation structure 160, which fills the trench; and a MOS transistor structure 170, with the doping layer 140 on the surface of the drift region 120 on both sides of the isolation structure 160 as a channel.

[0043] The semiconductor structure described in the embodiments of the present application is a silicon carbide device MOSFET with a super junction structure. The material of the silicon carbide substrate 100 is silicon carbide material, and the material of the silicon carbide epitaxial layer 110 is also silicon carbide material. In some embodiments of the present application, the silicon carbide substrate 100 and the silicon carbide epitaxial layer 110 may have doping ions, such as N-type doping ions. The drift region 120 (drift area) can be formed by an ion implantation process in the silicon carbide epitaxial layer 110, and the doping type of the drift region 120 is the same as that of the silicon carbide epitaxial layer 110, for example, N-type. The doping concentration of the drift region 120 is lower than the doping concentration of the silicon carbide epitaxial layer 110.

[0044] In some embodiments of the present application, the doping type of the doping layer 140 is opposite to the doping type of the drift region 120 (eg, P-type). The function of the doping layer 140 is to provide doping ions.

[0045] In some embodiments of the present application, the material of the doping layer 140 includes BSG or PSG.

[0046] In some embodiments of the present application, the material of the doping layer 140 includes boron-doped amorphous silicon carbide or aluminum-doped amorphous silicon carbide.

[0047] In some embodiments of the present application, the material of the doping layer 140 includes phosphoric acid or boric acid.

[0048] In some embodiments of the present application, the thickness of the portion of the doped layer 140 located on the surface of the drift region 120 is greater than the thickness of the portion of the doped layer 140 located at the bottom and sidewalls of the trench 120. This is because a MOS transistor structure will be formed on the portion of the doped layer 140 located on the surface of the drift region 120 later.

[0049] In some embodiments of the present application, the doping type of the diffusion layer 150 is opposite to the doping type of the drift region 120 (eg, P-type), and the diffusion layer 150 and the drift region 120 form a super junction structure.

[0050] In some embodiments of the present application, the doping concentration of the doping layer 140 is 6E16 to 1E19 cm -3 .

[0051] In some embodiments of the present application, the doping concentration of the diffusion layer 150 is 6E16 to 1E19 cm -3 .

[0052] In some embodiments of the present application, an isolation structure 160 is further formed in the trench to fill the trench. The isolation structure 160 is made of a material including silicon oxide.

[0053] In some embodiments of the present application, the material of the isolation structure 160 includes any one or more of aluminum oxide and silicon oxide.

[0054] In some embodiments of the present application, the isolation structure 160 includes a first isolation layer and a second isolation layer sequentially located on the surface of the trench, the material of the first isolation layer includes silicon oxide, and the material of the second isolation layer includes aluminum oxide.

[0055] In some embodiments of the present application, the MOS transistor structure 170 includes a gate structure 172 located on the surface of the doped layer 140, source regions 171 located in the doped layer 140 on both sides of the gate structure 172, and isolation regions (not shown) that isolate adjacent source regions 171. The gate structure 172 may include a gate located on the surface of the doped layer 140 and an insulating layer covering the sidewalls and top surface of the gate. The insulating layer is used to insulate and isolate the gate from subsequent metal layers, so that the metal layers can be electrically connected to the source regions 151 but not electrically connected to the gate.

[0056] refer to Figure 6 As shown, a metal layer 180 is formed on the doped layer 140 to cover the MOS transistor structure 170 and the doped layer 140. The metal layer 180 acts as a source metal to electrically connect the source region 151 and the doped layer 140, but is not electrically connected to the gate in the gate structure 152.

[0057] In some embodiments of the present application, the material of the metal layer 180 includes any one or more of titanium nitride, tungsten, or titanium silicide. The metal layer 180 can solve the heat dissipation problem of the device and improve the device performance.

[0058] The present application provides a silicon carbide device and a method for forming the same, wherein a diffusion layer is formed in a trench in a drift region to form a super junction structure, which can improve device performance.

[0059] In summary, after reading the contents of this application, those skilled in the art will understand that the foregoing contents are presented by way of example only and are not intended to be limiting. Although not expressly stated herein, those skilled in the art will understand that this application is intended to encompass various reasonable changes, improvements, and modifications to the embodiments. Such changes, improvements, and modifications are within the spirit and scope of the exemplary embodiments of this application.

[0060] It should be understood that the term "and / or" used in this embodiment includes any or all combinations of one or more of the associated listed items. It should be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element, or intervening elements may also be present.

[0061] Similarly, it should be understood that when an element such as a layer, region, or substrate is referred to as being "on" another element, it can be directly on the other element or intervening elements may be present. In contrast, the term "directly" indicates that there are no intervening elements. It should also be understood that the terms "comprising," "including," "include," or "comprising," when used in this specification, indicate the presence of recited features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0062] It should also be understood that although the terms first, second, third, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Therefore, without departing from the teachings of the present application, the first element in some embodiments may be referred to as the second element in other embodiments. The same reference numerals or the same reference designators represent the same elements throughout the specification.

[0063] In addition, this specification describes exemplary embodiments by reference to idealized exemplary cross-sectional views and / or plan views and / or stereograms. Therefore, differences from the illustrated shapes due to, for example, manufacturing techniques and / or tolerances are foreseeable. Therefore, the exemplary embodiments should not be interpreted as being limited to the shapes of the regions shown herein, but should include deviations in shapes due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have rounded or curved features. Therefore, the regions shown in the figures are schematic in nature, and their shapes are not intended to illustrate the actual shape of the region of the device nor to limit the scope of the exemplary embodiments.

Claims

1. A method for forming a silicon carbide device, characterized in that: include: Providing a silicon carbide substrate, wherein a silicon carbide epitaxial layer is formed on a surface of the silicon carbide substrate, a drift region is formed in the silicon carbide epitaxial layer, and a trench is formed in the drift region; forming a doping layer on the bottom and sidewalls of the trench and the surface of the drift region, wherein the doping type of the doping layer is opposite to the doping type of the drift region; performing an annealing process to diffuse the doping ions in the doping layer into the drift region to form a diffusion layer; forming an isolation structure filling the trench; A MOS transistor structure is formed by using the doping layers on the surfaces of the drift regions on both sides of the isolation structure as channels.

2. The method for forming a silicon carbide device according to claim 1, wherein: The material of the doping layer includes BSG or PSG, the annealing process includes microwave annealing, and the temperature of the microwave annealing is greater than 2000 degrees Celsius.

3. The method for forming a silicon carbide device according to claim 1, wherein: The material of the doping layer includes boron-doped amorphous silicon carbide or aluminum-doped amorphous silicon carbide, and the annealing process includes high-temperature annealing, and the temperature of the high-temperature annealing is greater than 2000 degrees Celsius.

4. The method for forming a silicon carbide device according to claim 1, wherein: The material of the doping layer includes phosphoric acid or boric acid, and the annealing process includes laser annealing.

5. The method for forming a silicon carbide device according to claim 1, wherein: After the annealing process, the doping concentration of the doping layer is 6E16 to 1E19 cm -3 .

6. A silicon carbide device, characterized in that: include: A silicon carbide substrate, wherein a silicon carbide epitaxial layer is formed on a surface of the silicon carbide substrate, a drift region is formed in the silicon carbide epitaxial layer, and a trench is formed in the drift region; a diffusion layer, located at the bottom and sidewalls of the trench and the surface of the drift region, wherein the doping type of the diffusion layer is opposite to the doping type of the drift region; a doping layer, located on a surface of the diffusion layer, wherein the doping type of the doping layer is opposite to the doping type of the drift region; an isolation structure filling the trench; The MOS transistor structure uses the doped layers on the surfaces of the drift regions on both sides of the isolation structure as channels.

7. The silicon carbide device according to claim 6, wherein: The material of the doping layer includes BSG or PSG.

8. The silicon carbide device according to claim 6, wherein: The material of the doping layer includes boron-doped amorphous silicon carbide or aluminum-doped amorphous silicon carbide.

9. The silicon carbide device according to claim 6, wherein: The material of the doping layer includes phosphoric acid or boric acid.

10. The silicon carbide device according to claim 6, wherein: The doping concentration of the doping layer is 6E16 to 1E19 cm -3 .

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