Semiconductor structure and forming method thereof

Abstract

The invention discloses a semiconductor structure and a forming method thereof. The method comprises the steps of providing a substrate; forming a dielectric wall structure on the substrate; and after the dielectric wall structures are formed, a fin part group is formed on the substrate, the fin part group comprises at least two fin parts, the extension direction of the fin parts is perpendicular to the extension direction of the fin parts, and the dielectric wall structures are located between the two adjacent fin parts. Before the fin part is formed, the dielectric wall structure is formed on the substrate, the shape of the dielectric wall structure is easy to control, the process for forming the dielectric wall structure is simple, and the performance stability of the semiconductor structure is improved; moreover, the dielectric wall structure is directly formed, filling is not needed, gaps cannot be formed in the dielectric wall structure, and the reliability of the dielectric wall structure is higher.

Description

Technical Field

[0001] The present invention relates to a semiconductor manufacturing process, and in particular to a semiconductor structure and a forming method thereof. Background Art

[0002] The forksheet field-effect transistor (FshFET) is a special type of fin field-effect transistor (FinFET). It's based on a gate-all-around FET (GAAFET) structure with a nanosheet as the channel. It's formed by building a dielectric wall between an N-type metal oxide semiconductor (NMOS) and a P-type metal oxide semiconductor (PMOS). The dielectric wall separates the PMOS side from the NMOS side. Compared to traditional nanosheets, forksheet transistors have advantages such as a smaller spacing between the NMOS and PMOS, a smaller transistor footprint, and lower transistor capacitance.

[0003] However, the current dielectric wall structure needs to be further improved. Summary of the Invention

[0004] The technical problem solved by the present invention is how to improve the morphology of the dielectric wall structure and enhance the performance of semiconductor devices.

[0005] To solve the above technical problems, an embodiment of the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate; forming a dielectric wall structure on the substrate; after forming the dielectric wall structure, forming a fin group on the substrate, wherein the fin group includes at least two fins, which are perpendicular to the extension direction of the fins, and the dielectric wall structure is located between two adjacent fins.

[0006] Optionally, the step of forming a dielectric wall structure on the substrate includes: forming an initial dielectric wall on the substrate; forming a first mask layer on the initial dielectric wall, wherein the first mask layer exposes a portion of the surface of the initial dielectric wall; and etching the initial dielectric wall using the first mask layer as a mask to form the dielectric wall structure.

[0007] Optionally, the step of etching the initial dielectric wall includes: using the first mask layer as a mask, performing a first etching on the initial dielectric wall to form the dielectric wall structure.

[0008] Optionally, the first etching includes: anisotropic dry etching.

[0009] Optionally, the step of etching the initial dielectric wall further includes: performing a second etching on the initial dielectric wall after the first etching to form the dielectric wall structure.

[0010] Optionally, the second etching includes isotropic etching.

[0011] Optionally, the isotropic etching includes at least one of isotropic wet etching and isotropic dry etching.

[0012] Optionally, the aspect ratio of the dielectric wall structure ranges from 5:1 to 15:1.

[0013] Optionally, the material of the dielectric wall structure includes one or more combinations of silicon oxide, silicon carbon nitride, silicon oxynitride and silicon oxycarbon nitride.

[0014] Optionally, the step of forming a fin group on the substrate includes: forming a fin layer on the substrate where the dielectric wall structure is exposed, and the top of the fin layer is flush with the top of the dielectric wall structure; forming a mask structure on the dielectric wall structure; and etching the fin layer using the mask structure as a mask to form the fin group.

[0015] Optionally, after forming the fin layer, a protection layer is formed on the fin layer and the dielectric wall structure.

[0016] Optionally, perpendicular to the extension direction of the dielectric wall structure, the mask structure extends from the fin on one side of the fin group to the fin on the other side, and the mask structure exposes a portion of the surface of the protective layer.

[0017] Optionally, the material of the protective layer includes silicon.

[0018] Optionally, after forming the fin, the method further includes: forming an isolation layer on the substrate, wherein the isolation layer covers a portion of the sidewall of the fin and exposes another portion of the surface of the fin.

[0019] Optionally, the fin includes a composite stack including a sacrificial layer and a channel layer located on a side of the sacrificial layer facing away from the substrate.

[0020] Optionally, the method further includes: removing the sacrificial layer after forming the fin; and forming a fully enclosed gate structure, wherein the fully enclosed gate structure encloses the channel layer.

[0021] Correspondingly, the technical solution of the present invention further provides a semiconductor structure, which is formed by the method for forming a semiconductor structure as described in any of the above technical solutions.

[0022] Compared with the prior art, the technical solution of the embodiment of the present invention has the following beneficial effects:

[0023] In the method for forming a semiconductor structure provided by the technical solution of the present invention, a dielectric wall structure is formed on the substrate before forming the fin. The morphology of the dielectric wall structure is relatively easy to control and the process of forming the dielectric wall structure is simple, thereby improving the performance stability of the semiconductor structure. Moreover, the dielectric wall structure is directly formed without the need for filling, and no gaps are formed in the dielectric wall structure, thereby increasing the reliability of the dielectric wall structure.

[0024] In an optional solution of the present invention, the mask structure for forming the fin group extends from the fin layer on one side of the dielectric wall structure to the fin layer on the other side, perpendicular to the extension direction of the dielectric wall structure. The mask structure spans the dielectric wall structure, and the fin layer is etched using the mask structure as a mask to form the fin group. The fin group has a larger size along the direction perpendicular to the extension direction of the dielectric wall structure, and etching the fin layer to form the fin group simultaneously forms fins located on both sides of the dielectric wall structure, reducing the difficulty of etching to form the fins and simplifying the process flow.

[0025] In an optional solution of the present invention, after the fin layer is formed, a protective layer is formed on the fin layer and the dielectric wall structure. The protective layer acts as an etching barrier layer to protect the fin and the dielectric wall structure from being damaged during the process of removing the mask structure and forming the isolation layer, thereby improving the performance stability of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figures 1 to 3 It is a cross-sectional structural diagram of the formation process of a semiconductor structure.

[0027] Figures 4 to 12 It is a schematic cross-sectional structural diagram of the formation process of the semiconductor structure according to an embodiment of the present invention. DETAILED DESCRIPTION

[0028] As mentioned in the background art, the current dielectric wall structure needs to be further improved.

[0029] Figures 1 to 3 It is a cross-sectional structural diagram of the formation process of a semiconductor structure.

[0030] Please refer to Figure 1 The semiconductor structure includes: a substrate 100; a fin assembly 101 located on the substrate 100, wherein the fin assembly 101 has two separate fins 102; an isolation layer 103 located on the substrate 100, wherein the isolation layer 103 exposes the sidewalls of each of the fins 102; and an opening 104 located between the two fins 102 of the fin assembly 101, wherein the opening 104 exposes the surface of the isolation layer 103.

[0031] Please refer to Figure 2An initial dielectric wall 105 is formed on the isolation layer 103, the sidewalls of the fin 102, and the top of the fin 102. The initial dielectric wall 105 fills the opening 104. The initial dielectric wall 105 is formed by deposition.

[0032] Please refer to Figure 3 , the initial dielectric wall 105 is etched back to remove the initial dielectric wall 105 between the adjacent fin assemblies 101 and the initial dielectric wall 105 located on the top of the fin 102, forming a dielectric wall located in the opening 104 (such as Figure 1 ) within the dielectric wall structure 106.

[0033] The distance between the two fins 102 of the fin assembly 101 is small, making it difficult to deposit an initial dielectric wall 105 with uniform thickness. In addition, during the subsequent back etching process to remove the initial dielectric wall 105, the initial dielectric wall 105 within the opening 104 will be lost, resulting in the morphology of the formed dielectric wall structure 106 not meeting process expectations.

[0034] The fin 102 has a large aspect ratio, and the opening 104 has a large depth and width ratio, making it difficult to fill. Voids are easily formed in the formed dielectric wall structure 106, and the dielectric wall structure 106 has poor reliability. In addition, the fin 102 has a large aspect ratio, and the process of etching to form the fin 102 is difficult.

[0035] To address the above-mentioned technical problems, the present invention provides a method for forming a semiconductor structure. Prior to forming the fins, a dielectric wall structure is formed on the substrate. The morphology of the dielectric wall structure is easily controllable, and the process for forming the dielectric wall structure is simple, thereby improving the performance stability of the semiconductor structure. Furthermore, the dielectric wall structure is directly formed without the need for filling, and voids are not formed within the dielectric wall structure, resulting in higher reliability. Furthermore, a mask structure for forming a fin group is formed, spanning the dielectric wall structure in a direction perpendicular to the extension of the dielectric wall structure. Using the mask structure as a mask, the fin layer is etched to form a fin group. The fin group has a larger dimension in the direction perpendicular to the extension of the dielectric wall structure, and etching the fin layer to form the fin group simultaneously forms fins located on both sides of the dielectric wall structure. This reduces the difficulty of etching the fins and simplifies the process flow.

[0036] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0037] Figures 4 to 12 It is a schematic cross-sectional structural diagram of the formation process of the semiconductor structure according to an embodiment of the present invention.

[0038] Please refer to Figure 4 , providing a substrate 200.

[0039] The material of the substrate 200 includes silicon, germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium. Specifically, in this embodiment, the material of the substrate 200 is silicon.

[0040] Please refer to Figure 5 and Figure 6 , a dielectric wall structure 203 is formed on the substrate 200.

[0041] The steps of forming the dielectric wall structure 203 on the substrate 200 include: Figure 5 As shown, an initial dielectric wall 201 is formed on the substrate 200; a first mask layer 202 is formed on the initial dielectric wall 201, wherein the first mask layer 202 exposes a portion of the surface of the initial dielectric wall 201; Figure 6 As shown, the initial dielectric wall 201 is etched using the first mask layer 202 as a mask to form the dielectric wall structure 203 .

[0042] The dielectric wall structure 203 is formed directly on the substrate 200. The morphology of the dielectric wall structure 203 is easy to control and the process of forming the dielectric wall structure 203 is simple, thereby improving the performance stability of the semiconductor structure. The initial dielectric wall 201 provides a structural foundation for forming the dielectric wall structure 203.

[0043] The material of the initial dielectric wall 201 is an insulating material, and the material of the initial dielectric wall 201 includes: a combination of one or more of silicon oxide, silicon carbon nitride, silicon oxynitride, and silicon oxycarbon nitride. Specifically, in this embodiment, the material of the initial dielectric wall 201 is silicon nitride.

[0044] The formation process of the initial dielectric wall 201 includes deposition.

[0045] The thickness of the initial dielectric wall 201 is greater than The structure of the initial dielectric wall 201 includes a single-layer structure and a multi-layer stacked structure. Specifically, in this embodiment, the structure of the initial dielectric wall 201 is a single-layer structure. In other embodiments, the structure of the initial dielectric wall 201 can be a multi-layer stacked structure.

[0046] The first mask layer 202 defines the shape and position of the dielectric wall structure 203 .

[0047] In some embodiments of the present invention, a plurality of first mask layers 202 are formed on the initial dielectric wall 201 , and the plurality of first mask layers 202 are disposed separately from each other.

[0048] The aspect ratio of the dielectric wall structure 203 ranges from 5:1 to 15:1.

[0049] The height range of the dielectric wall structure 203 is greater than

[0050] The width of the dielectric wall structure 203 is in the range of 10 nm to 20 nm. The dielectric wall structure 203 extends along a first direction X. The size of the dielectric wall structure 203 in a second direction Y is in the range of 10 nm to 20 nm. The second direction Y is perpendicular to the first direction X. The first direction X is perpendicular to the paper.

[0051] The step of etching the initial dielectric wall 201 includes: using the first mask layer 202 as a mask, performing a first etching on the initial dielectric wall 201 to form the dielectric wall structure 203 .

[0052] The first etching includes: anisotropic dry etching.

[0053] The first etching is anisotropic dry etching, which etches the initial dielectric wall 201 at different rates in different directions, which is conducive to forming a dielectric wall structure 203 with a large aspect ratio.

[0054] The process parameters of the anisotropic dry etching include: etching gas includes carbon tetrafluoride (CF4); the gas flow range is: 20sccm ~ 1000sccm; the etching time range is: 5 seconds ~ 120 seconds.

[0055] The step of etching the initial dielectric wall 201 further includes: performing a second etching on the initial dielectric wall 201 after the first etching to form the dielectric wall structure 203 .

[0056] The second etching includes isotropic etching, and the isotropic etching includes at least one of isotropic wet etching and isotropic dry etching.

[0057] The second etching is isotropic etching, which etches the initial dielectric wall 201 after the first etching at the same rate in all directions, and finely controls the morphology of the initial dielectric wall 201 after the first etching to obtain a dielectric wall structure 203 that meets the critical dimensions expected by the process.

[0058] The process parameters for the isotropic dry etching process include: etching gases including ammonia (NH3) and hydrogen fluoride (HF); a gas flow rate range of 20 sccm to 1000 sccm; an etching time range of 5 seconds to 120 seconds; and a number of cycles range of 1 to 50. The etching amount in the etching process is positively correlated with the etching time, and the etching endpoint can be controlled by controlling the etching time.

[0059] The process parameters of the isotropic wet etching include: the etching solution includes: hydrofluoric acid solution; the concentration mass fraction range of the etching solution is: 0.1wt% to 1.0wt%; the etching time range is: 10 seconds to 500 seconds.

[0060] In this embodiment, after the initial dielectric wall 201 is first etched, the first etched initial dielectric wall 201 is second etched to form a dielectric wall structure 203 .

[0061] In another embodiment, only the initial dielectric wall is first etched to form the dielectric wall structure.

[0062] The dielectric wall structure 203 is made of an insulating material, and includes one or more of silicon oxide, silicon carbon nitride, silicon oxynitride, and silicon oxycarbon nitride. Specifically, in this embodiment, the dielectric wall structure 203 is made of silicon nitride.

[0063] After forming the dielectric wall structure 203 , a fin group 207 is formed on the substrate 200 . The fin group 207 includes at least two fins 208 . The dielectric wall structure 203 is located between two adjacent fins 208 , perpendicular to the extending direction of the fins 208 .

[0064] Please refer to Figures 7 to 10 The steps of forming the fin group 207 on the substrate 200 include: Figure 7 and Figure 8 As shown, a fin layer 204 is formed on the substrate 200 where the dielectric wall structure 203 is exposed, and the top of the fin layer 204 is flush with the top of the dielectric wall structure 203; Figure 9 As shown, a mask structure 206 is formed on the dielectric wall structure 203; Figure 10 As shown, the fin layer 204 is etched using the mask structure 206 as a mask to form the fin group 207 .

[0065] The dielectric wall structure 203 is filled between two adjacent fin layers 204, and the sidewalls of the dielectric wall structure 203 are in contact with the sidewalls of the fin layer 204. In some embodiments, the substrate 200 has at least two dielectric wall structures 203, and the fin layer 204 is filled between adjacent dielectric wall structures 203.

[0066] In this embodiment, the top of the fin layer 204 is flush with the top of the dielectric wall structure 203, which improves the morphology controllability of the dielectric wall structure 203 and the fin group 207 formed by subsequently etching the fin layer 204, and prevents the top of the dielectric wall structure 203 from being recessed into the top of the fin 208 of the fin group 207, resulting in a weakening of the dielectric isolation effect of the dielectric wall structure 203 on the transistors located on both sides of the dielectric wall structure 203.

[0067] The fin layer 204 includes a composite stack including a sacrificial layer and a channel layer located on the side of the sacrificial layer facing away from the substrate 200 ; the sacrificial layer material includes silicon germanium; the channel layer material includes silicon; the composite stack has 2 to 3 layers.

[0068] The fin layer 204 is formed by epitaxial growth and is selectively grown on the silicon substrate 200 .

[0069] The protection layer 205 acts as an etching barrier layer to protect the fin 208 and the dielectric wall structure 203 from being lost during the subsequent process of removing the mask structure 206 and etching the initial isolation layer 209 to form the isolation layer 210 , thereby improving the performance stability of the semiconductor structure.

[0070] The material of the protective layer 205 is silicon, and the thickness range of the protective layer 205 is: Specifically, in this embodiment, since the silicon nitride material of the dielectric wall structure 203 is amorphous, the protective layer 205 grown on the top surface of the dielectric wall structure 203 is amorphous; the silicon germanium of the fin layer 204 is single crystal, and the protective layer 205 grown on the top surface of the fin layer 204 is crystalline.

[0071] The mask structure 206 is used as a mask for etching the fin layer 204 to form the fin group 207. Due to the large aspect ratio of the fin 208, the mask structure 206 is relatively thick and is a multi-layer stacked structure. Specifically, in this embodiment, the mask structure 206 includes a polysilicon layer.

[0072] The fin group 207 includes at least two fins 208. The dielectric wall structure 203 is located between two adjacent fins 208, perpendicular to the extending direction of the fins 208. The sidewalls of the dielectric wall structure 203 are in contact with the sidewalls of the fins 208 on both sides.

[0073] The mask structure 206 spans the dielectric wall structure 203, extending from the fin 208 on one side of the fin group 207 to the fin 208 on the other side. Using the mask structure 206 as a mask, the fin layer 204 is etched to form the fin group 207. The size of the fin group 207 along the direction perpendicular to the extension of the fin 208 is larger, and etching the fin layer 204 to form the fin group 207 simultaneously forms two fins 208 located on both sides of the dielectric wall structure 203, which reduces the difficulty of etching to form the fin 208 and simplifies the process flow.

[0074] In this embodiment, the dielectric wall structure 203 is located between two adjacent fins 208 of each fin group 207 , and the two fins 208 of the fin group 207 are located on opposite sides of the dielectric wall structure 203 along the second direction Y, and the two fins 208 of the fin group 207 are in contact with both sidewalls of the dielectric wall structure 203 . On the one hand, when etching the fin layer 204 to form the fin group 207, since the width of each fin group 207 along the second direction Y is the sum of the width of the two fins 208 along the second direction Y and the width of the dielectric wall structure 203 along the second direction Y, the width of the fin group 207 along the second direction Y is larger than the width of a single fin 208 along the second direction Y. Therefore, the process difficulty of etching the fin layer 204 to form the fin group 207 is reduced compared with the process difficulty of etching the fin layer 204 to form a single fin 208. On the other hand, etching the fin layer 204 to form the fin group 207 simultaneously forms two fins 208 located on both sides of the dielectric wall structure 203, which simplifies the process flow.

[0075] In some embodiments, the fin 208 includes a composite stack including a sacrificial layer and a channel layer located on the side of the sacrificial layer facing away from the substrate 200; the sacrificial layer material includes silicon germanium; the channel layer material includes silicon; and the number of layers of the composite stack is 2 to 3.

[0076] Please refer to Figures 11 to 12 After forming the fin, the method further includes forming an isolation layer 210 on the substrate 200, wherein the isolation layer 210 covers a portion of the sidewall of the fin 208 and exposes another portion of the surface of the fin 208. The steps of forming the isolation layer 210 include: Figure 11 As shown, an initial isolation layer 209 is formed on the substrate 200, the sidewalls of the fin 208, the sidewalls of the mask structure 206, and the mask structure 206; the initial isolation layer 209 is planarized until the mask structure 206 is exposed; Figure 12 As shown, after the initial isolation layer 209 is planarized, the mask structure 206 is removed; after the mask structure 206 is removed, the initial isolation layer 209 is etched back until a portion of the sidewall of the fin 208 is exposed to form an isolation layer 210.

[0077] The initial isolation layer 209 is made of silicon oxide and provides a structural foundation for forming an isolation layer 210 . The isolation layer 210 is used to separate two adjacent fin groups 207 to prevent electrical crosstalk between adjacent fin groups 207 due to current flow.

[0078] Planarization methods include mechanical polishing, chemical polishing, fluid polishing, and chemical-mechanical polishing. Specifically, in this embodiment, the planarization method is chemical-mechanical polishing. Unlike traditional purely mechanical or purely chemical polishing methods, chemical-mechanical polishing avoids the surface damage caused by mechanical polishing alone and the shortcomings of chemical polishing alone, such as slow polishing speed, poor surface flatness, and poor polishing consistency. Chemical-mechanical polishing is widely used for high-planarization nanoscale polishing of various materials.

[0079] The protection layer 205 acts as an etching stop layer to protect the fin 208 and the dielectric wall structure 203 from being lost during the process of removing the mask structure 206 and forming the isolation layer 210 , thereby improving the performance stability of the semiconductor structure.

[0080] The etch-back process includes a dry etching process. Dry etching methods include physical etching, chemical etching, and physical-chemical etching. Specifically, in this embodiment, the etch-back method is a Certas gas chemical etching method. The Certas gas chemical etching method has the advantage of having a high selectivity for removing the initial isolation layer 209 without damaging the fins 208.

[0081] After forming the isolation layer 210 , the sacrificial layer is removed.

[0082] After removing the sacrificial layer, a fully surrounding gate structure is formed, and the fully surrounding gate structure surrounds the channel layer.

[0083] Correspondingly, an embodiment of the present invention further provides a semiconductor structure formed by the above-mentioned method for forming a semiconductor structure, which will not be described in detail here.

[0084] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be based on the scope defined by the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that: include: providing a substrate; forming a dielectric wall structure on the substrate; After forming the dielectric wall structure, a fin group is formed on the substrate, wherein the fin group includes at least two fins, and the dielectric wall structure is located between two adjacent fins perpendicular to the extending direction of the fins.

2. The method for forming a semiconductor structure according to claim 1, wherein: The step of forming a dielectric wall structure on the substrate includes: forming an initial dielectric wall on the substrate; forming a first mask layer on the initial dielectric wall, wherein the first mask layer exposes a portion of the surface of the initial dielectric wall; The initial dielectric wall is etched using the first mask layer as a mask to form the dielectric wall structure.

3. The method for forming a semiconductor structure according to claim 2, wherein: The step of etching the initial dielectric wall includes: using the first mask layer as a mask, performing a first etching on the initial dielectric wall to form the dielectric wall structure.

4. The method for forming a semiconductor structure according to claim 3, wherein: The first etching includes: anisotropic dry etching.

5. The method for forming a semiconductor structure according to claim 3, wherein: The step of etching the initial dielectric wall further includes: performing a second etching on the initial dielectric wall after the first etching to form the dielectric wall structure.

6. The method for forming a semiconductor structure according to claim 5, wherein: The second etching includes isotropic etching.

7. The method for forming a semiconductor structure according to claim 6, wherein: The isotropic etching includes at least one of isotropic wet etching and isotropic dry etching.

8. The method for forming a semiconductor structure according to claim 1, wherein: The aspect ratio of the dielectric wall structure ranges from 5:1 to 15:

1.

9. The method for forming a semiconductor structure according to claim 1, wherein: The material of the dielectric wall structure includes one or more combinations of silicon oxide, silicon carbon nitride, silicon oxynitride and silicon oxycarbon nitride.

10. The method for forming a semiconductor structure according to claim 1, wherein: The step of forming a fin group on the substrate includes: forming a fin layer on the substrate where the dielectric wall structure is exposed, wherein the top of the fin layer is flush with the top of the dielectric wall structure; forming a mask structure on the dielectric wall structure; and etching the fin layer using the mask structure as a mask to form the fin group.

11. The method for forming a semiconductor structure according to claim 10, wherein: After forming the fin layer, a protection layer is formed on the fin layer and the dielectric wall structure.

12. The method for forming a semiconductor structure according to claim 11, wherein: The mask structure extends perpendicular to the extension direction of the dielectric wall structure from the fin on one side of the fin group to the fin on the other side, and the mask structure exposes a portion of the surface of the protection layer.

13. The method for forming a semiconductor structure according to claim 11, wherein: The material of the protection layer includes silicon.

14. The method for forming a semiconductor structure according to claim 1, wherein: After forming the fin, the method further includes: forming an isolation layer on the substrate, wherein the isolation layer covers a portion of the sidewall of the fin and exposes another portion of the surface of the fin.

15. The method for forming a semiconductor structure according to claim 1, wherein: The fin includes a composite stack including a sacrificial layer and a channel layer located on a side of the sacrificial layer facing away from the substrate.

16. The method for forming a semiconductor structure according to claim 15, wherein: Also includes: After forming the fin, removing the sacrificial layer; A fully surrounding gate structure is formed, wherein the fully surrounding gate structure surrounds the channel layer.

17. A semiconductor structure, characterized in that The semiconductor structure is formed by the method for forming a semiconductor structure according to any one of claims 1 to 16.

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