Semiconductor structure and forming method thereof

Abstract

The invention discloses a semiconductor structure and a forming method thereof, and the structure is characterized in that each gate channel structure comprises a gate, a plurality of first channel layers and a plurality of second channel layers, the first channel layers and the second channel layers are located in the gate and are separated from each other, the second channel layers are located on the first channel layers, and the first channel layers are parallel to a first direction and penetrate through the gate in the first direction; the gate exposes two opposite first side walls of each first channel layer, the plurality of second channel layers are parallel to the second direction and penetrate through the gate in the second direction, the gate exposes two opposite second side walls of each second channel layer, the first direction and the second direction are parallel to the surface of the substrate, and the first direction is different from the second direction; the first source and drain layers are located on the surfaces of the first side walls of the first channel layers; and the second source and drain layers are located on the surfaces of the second side walls of the second channel layers, the conduction types of the second source and drain layers are different from those of the first source and drain layers, and the generation probability of short circuit abnormity between the upper-layer device and the lower-layer device is reduced.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing, and in particular to a semiconductor structure and a method for forming the same. Background Art

[0002] With the further development of semiconductor technology, the size of transistors has been reduced to less than a few nanometers. After the size of the fin field-effect device (FinFET) itself has been reduced to the limit, whether it is the fin distance, short channel effect, or leakage and material limitations, transistor manufacturing has become precarious, and even the physical structure cannot be completed. The wrap-around gate (gate-all-around, GAA) device has become a new direction of research and development in the industry. The characteristic of this technology is that the gate wraps around the channel on all four sides. The source and drain are no longer in contact with the substrate. Instead, multiple source and drain electrodes are distributed horizontally and perpendicular to the gate in the form of lines (which can be understood as sticks) or flat plates or sheets to achieve the basic structure and function of MOSFET.

[0003] As chip area continues to shrink, further reductions in cell height will require even smaller spacing between nFET and pFET devices within a standard cell. However, for FinFETs and gate-all-around devices, the process limits the spacing between these n and p devices. Complementary field-effect devices (CFETs) stack nFETs and pFETs vertically, significantly reducing chip area and achieving integration. CFETs are a potential technology trend following FinFETs and gate-all-around devices.

[0004] However, the performance of existing complementary field-effect devices still needs to be further improved. Summary of the Invention

[0005] The technical problem solved by the present invention is to provide a semiconductor structure and a method for forming the same, so as to improve the performance of a complementary field effect device.

[0006] To solve the above technical problems, the technical solution of the present invention provides a semiconductor structure, comprising: a substrate; a plurality of gate channel structures located on a portion of the surface of the substrate, each of the gate channel structures comprising a gate, a plurality of first channel layers and a plurality of second channel layers separated from each other and located in the gate, a plurality of the second channel layers being located on the plurality of the first channel layers, a plurality of the first channel layers being parallel to a first direction and penetrating the gate in the first direction, the gate exposing two first side walls opposite to each of the first channel layers, a plurality of the second channel layers being parallel to a second direction and penetrating the gate in the second direction, the gate exposing two second side walls opposite to each of the second channel layers, the first direction and the second direction being parallel to the substrate surface, and the first direction being different from the second direction; a first source and drain layer located on the first side wall surface of the plurality of the first channel layers; a second source and drain layer located on the second side wall surface of the plurality of the second channel layers, the second source and drain layer having a different conductivity type from the first source and drain layer.

[0007] Optionally, it further includes: an interlayer dielectric layer located on the surface of the substrate, the surface of the first source and drain layer, the surface of the second source and drain layer, and the surfaces of several of the gate channel structures, wherein the interlayer dielectric layer exposes the top surface of each of the gates.

[0008] Optionally, the method further includes: a first etch stop layer located between the first source / drain layer and the interlayer dielectric layer; and a second etch stop layer located between the second source / drain layer and the interlayer dielectric layer.

[0009] Optionally, it further includes: a first inner sidewall located on two sidewall surfaces of each of the gates arranged in the first direction; and a second inner sidewall located on two sidewalls of each of the gates arranged in the second direction.

[0010] Optionally, the first direction and the second direction are perpendicular to each other.

[0011] Correspondingly, the technical solution of the present invention also provides a method for forming a semiconductor structure, comprising: providing a substrate; forming a plurality of dummy gate channel structures on a portion of the substrate surface, each of the dummy gate channel structures comprising a dummy gate, a plurality of first channel layers and a plurality of second channel layers separated from each other and located in the dummy gate, the plurality of second channel layers being located on the plurality of first channel layers, the plurality of first channel layers being parallel to a first direction and penetrating the dummy gate in the first direction, the dummy gate exposing two first side walls opposite to each of the first channel layers, the plurality of second channel layers being parallel to a second direction and penetrating the dummy gate in the second direction, the dummy gate exposing two second side walls opposite to each of the second channel layers, the first direction and the second direction being parallel to the substrate surface, and the first direction being different from the second direction; forming a first source and drain layer on the first side wall surfaces of the plurality of first channel layers; forming a second source and drain layer on the second side wall surfaces of the plurality of second channel layers, the second source and drain layer having a different conductivity type from the first source and drain layer.

[0012] Optionally, after forming the first source and drain layer and the second source and drain layer, the method further includes: forming an interlayer dielectric layer on the surface of the substrate, the surface of the first source and drain layer, the surface of the second source and drain layer, and the surfaces of several of the pseudo gate channel structures, wherein the interlayer dielectric layer exposes the top surface of each of the pseudo gates; after forming the interlayer dielectric layer, forming a gate to replace the pseudo gate, and forming a gate channel structure with the pseudo gate channel structure.

[0013] Optionally, after forming the first source / drain layer, the second source / drain layer is formed; the process of forming the first source / drain layer includes a first selective epitaxial growth process; the process of forming the second source / drain layer includes a second selective epitaxial growth process.

[0014] Optionally, after forming several dummy gate channel structures and before forming the first source and drain layer, it also includes: forming a sidewall structure on the surface of the substrate and the surfaces of several of the dummy gate channel structures, the sidewall structure is located on the second sidewall surface of each second channel layer, and exposes the first sidewall surface of each first channel layer; each of the dummy gates has two third sidewalls arranged in the first direction and two fourth sidewalls arranged in the second direction; the sidewall structure is also located on the fourth sidewall surface and the top surface of each of the dummy gates, and exposes the third sidewall surface of each of the dummy gates.

[0015] Optionally, the sidewall structure includes a first outer wall and a second outer wall located on the surface of the first outer wall, and the materials of the first outer wall and the second outer wall are different; the method for forming the sidewall structure includes: forming a first outer wall material layer on the surface of the substrate and the surfaces of several of the pseudo gate channel structures; forming a second outer wall material layer on the surface of the first outer wall material layer; forming a first sacrificial layer on the surface of part of the second outer wall material layer, the first sacrificial layer exposing the second outer wall material layer on the first sidewall surface of each first channel layer and the third sidewall surface of each pseudo gate; using the first sacrificial layer as a mask, etching the second outer wall material layer to form the second outer wall layer; removing the first sacrificial layer; after removing the first sacrificial layer, etching the first outer wall material layer with the second outer wall material layer to form the first outer wall layer.

[0016] Optionally, after forming the sidewall structure and before forming the first source and drain layer, a first inner sidewall is further formed on the third sidewall surface of each of the dummy gates; the first inner sidewall is also located on a portion of the substrate surface; the method for forming the first inner sidewall comprises: using the sidewall structure as a mask, etching the third sidewall of the dummy gate so that the third sidewall surface of the dummy gate is recessed relative to the first sidewall surface of the first channel layer; after etching the third sidewall of the dummy gate, forming a first inner sidewall material layer on the substrate surface, the third sidewall surface of the dummy gate, the first sidewall surface of the first channel layer and the sidewall structure surface; etching back the first inner sidewall material layer until the first sidewall surface of the first channel layer is exposed.

[0017] Optionally, after forming the first source and drain layer and before forming the second source and drain layer, it also includes: etching the sidewall structure of the second sidewall surface of each second channel layer to expose the two second sidewall surfaces of each second channel layer; etching the sidewall structure of the fourth sidewall surface of each pseudo gate to expose the fourth sidewall surface of each pseudo gate.

[0018] Optionally, after forming the first source and drain layer and before exposing the two second sidewall surfaces of each second channel layer, a first etch stop layer is formed on the surface of the first source and drain layer; the first etch stop layer is also located on a portion of the substrate surface and the sidewall structure surface.

[0019] Optionally, the method for exposing the two second side wall surfaces of each second channel layer and the fourth side wall surface of each pseudo gate includes: forming a second sacrificial layer on the substrate surface, the first source and drain layer surface and the side wall of the pseudo gate channel structure, the second sacrificial layer exposing the fourth side wall surface of each pseudo gate and the side wall structure of the second side wall surface of each second channel layer; using the second sacrificial layer as a mask, etching the first etch stop layer until the side wall structure is exposed; after exposing the side wall structure, removing the second sacrificial layer; after removing the second sacrificial layer, etching the side wall structure using the first etch stop layer as a mask.

[0020] Optionally, after exposing the two second side wall surfaces of each second channel layer and exposing the fourth side wall surface of each dummy gate, and before forming the second source and drain layer, it also includes: forming a second inner side wall on the fourth side wall surface of each dummy gate; the second inner side wall is also located on a portion of the substrate surface; the method for forming the second inner side wall includes: etching the fourth side wall of the dummy gate so that the fourth side wall surface of the dummy gate is recessed relative to the second side wall surface of the second channel layer; after etching the fourth side wall of the dummy gate, forming a second inner side wall material layer on the substrate surface, the fourth side wall surface of the dummy gate, and the second side wall surface of the second channel layer; etching back the second inner side wall material layer until the second side wall surface of the second channel layer is exposed.

[0021] Optionally, after forming the second source / drain layer and before forming the interlayer dielectric layer, the method further includes: forming a second etch stop layer on the surface of the second source / drain layer.

[0022] Optionally, the method for forming several of the pseudo gate channel structures includes: forming a first pseudo gate material layer on the surface of the substrate; forming several first initial channel layers on the surface of part of the first pseudo gate material layer, and several of the first initial channel layers are parallel to the first direction; forming a second pseudo gate material layer on the surface of the first pseudo gate material layer and several of the first initial channel layers; forming several second initial channel layers on the surface of part of the second pseudo gate material layer, and several of the second initial channel layers are parallel to the second direction; forming a third pseudo gate material layer on the surface of the second pseudo gate material layer and several of the second initial channel layers; patterning the first pseudo gate material layer, the second pseudo gate material layer, the third pseudo gate material layer, several of the first initial channel layers and several of the second initial channel layers to form several of the pseudo gate channel structures, forming the first channel layer with the first initial channel layer, forming the second channel layer with the second initial channel layer, and forming the pseudo gate with the first pseudo gate material layer, the second pseudo gate material layer and the third pseudo gate material layer.

[0023] Optionally, the method of forming the gate by replacing the dummy gate includes: removing the dummy gate, forming a gate groove in the interlayer dielectric layer, the gate groove exposing a plurality of the first channel layers and a plurality of the second channel layers; and forming the gate in the gate groove.

[0024] Optionally, the material of the first channel layer includes silicon; the material of the second channel layer includes silicon; and the material of the dummy gate includes silicon germanium.

[0025] Optionally, the method further includes: forming a first conductive layer on the surface of the first source-drain layer; and forming a second conductive layer on the surface of the second source-drain layer.

[0026] Compared with the prior art, the technical solution of the embodiment of the present invention has the following beneficial effects:

[0027] In the semiconductor structure provided by the technical solution of the present invention, a number of second channel layers are located on a number of first channel layers, a number of first channel layers are parallel to the first direction, and a number of second channel layers are parallel to the second direction, so that the arrangement directions of the channel layers between the upper and lower devices are different, thereby making the first source and drain layers and the second source and drain layers spatially staggered. When the first source and drain layers and the second source and drain layers are electrically led out respectively by a conductive layer, mutual contact between the conductive layers caused by the stacked arrangement between the first source and drain layers and the second source and drain layers is avoided, which is beneficial to reducing the probability of short circuit anomalies between the upper and lower devices, and improving the performance of complementary field effect devices.

[0028] In the method for forming a semiconductor structure provided by the technical solution of the present invention, in the gate channel structure formed, a number of the second channel layers are located on a number of the first channel layers, a number of the first channel layers are parallel to the first direction, and a number of the second channel layers are parallel to the second direction, so that the arrangement directions of the channel layers between the upper and lower devices are different, thereby making the first source and drain layers and the second source and drain layers spatially staggered. When the first source and drain layers and the second source and drain layers are electrically led out respectively by a conductive layer, mutual contact between the conductive layers caused by the stacked arrangement between the first source and drain layers is avoided, which is beneficial to reducing the probability of short circuit anomalies between the upper and lower devices and improving the performance of complementary field effect devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 It is a structural diagram of a complementary field effect device;

[0030] Figures 2 to 15 It is a structural schematic diagram corresponding to each step in the semiconductor structure forming method according to an embodiment of the present invention. DETAILED DESCRIPTION

[0031] It should be noted that the terms “surface” and “on” in this specification are used to describe relative positional relationships in space and are not limited to whether there is direct contact.

[0032] As described in the background art, the performance of complementary field effect devices formed in the prior art needs to be improved. An explanation and analysis will now be provided in conjunction with the structure of a complementary field effect device.

[0033] Figure 1 It is a structural diagram of a complementary field effect device.

[0034] Please refer to Figure 1 The complementary field effect device includes: a substrate (not shown in the figure); a PMOS device located on the substrate, and an NMOS device located on the PMOS device, the PMOS device and the NMOS device are stacked, the PMOS device and the NMOS device share a gate 100, the PMOS device includes a plurality of first fins 101 and a first source-drain layer 102, the gate 100 spans the plurality of first fins 101, and the first source-drain layer 102 is located in the first fins 101 on both sides of the gate 100, the NMOS device includes a plurality of second fins 111 and a second source-drain layer 112, the gate 100 spans the plurality of second fins 111, and the second source-drain layer 112 is located in the second fins 101 on both sides of the gate 100.

[0035] In the complementary field-effect device described above, to separately extract current from the first source-drain layer 102 and the second source-drain layer 112, a first conductive layer is subsequently formed on the surface of the first source-drain layer 102, and a second conductive layer is subsequently formed on the second source-drain layer 103. Because the first source-drain layer 102 of the PMOS device and the second source-drain layer 112 of the NMOS device are stacked, contact between the first and second conductive layers can easily occur, leading to short circuit anomalies and severely impacting the performance of the complementary field-effect device.

[0036] In order to solve the above problems, the present invention provides a semiconductor structure and a method for forming the same, in which several second channel layers are located on several first channel layers, several first channel layers are parallel to the first direction, and several second channel layers are parallel to the second direction, so that the arrangement directions of the channel layers between the upper and lower devices are different, thereby making the first source and drain layers and the second source and drain layers spatially staggered. When the first source and drain layers and the second source and drain layers are electrically led out respectively by a conductive layer, mutual contact between the conductive layers caused by the stacked arrangement between the first source and drain layers is avoided, which is beneficial to reducing the probability of short circuit anomalies between the upper and lower devices, and improving the performance of complementary field effect devices.

[0037] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0038] Figures 2 to 15 It is a structural schematic diagram corresponding to each step in the semiconductor structure forming method according to an embodiment of the present invention.

[0039] Please refer to Figure 2 , providing a substrate 200.

[0040] In this embodiment, the material of the substrate 200 includes silicon. In other embodiments, the material of the substrate includes silicon carbide, silicon germanium, a multinary semiconductor material composed of Group III-V elements, silicon-on-insulator (SOI), or germanium-on-insulator (GOI). The multinary semiconductor material composed of Group III-V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs, or InGaAsP.

[0041] Subsequently, a number of dummy gate channel structures are formed on a portion of the surface of the substrate 200, each of the dummy gate channel structures including a dummy gate, a number of first channel layers and a number of second channel layers separated from each other and located in the dummy gate, a number of the second channel layers are located on a number of the first channel layers, a number of the first channel layers are parallel to a first direction X, and penetrate the dummy gate in the first direction X, the dummy gate exposes two first side walls opposite to each of the first channel layers, a number of the second channel layers are parallel to a second direction Y, and penetrate the dummy gate in the second direction Y, the dummy gate exposes two second side walls opposite to each of the second channel layers, the first direction X and the second direction Y are parallel to the surface of the substrate 200, and the first direction X is different from the second direction Y.

[0042] In this embodiment, the formation method of some of the dummy gate channel structures can be referred to Figures 2 to 5 .

[0043] Please continue to refer to Figure 2 , a first dummy gate material layer 201 is formed on the surface of the substrate 200; a plurality of first initial channel layers 202 are formed on a portion of the surface of the first dummy gate material layer 201, and the plurality of first initial channel layers 202 are parallel to the first direction X.

[0044] The first dummy gate material layer 201 is used to form a portion of a dummy gate; the first initial channel layers 202 are used to form a plurality of first channel layers. The dummy gate is used to occupy space for forming a gate and will need to be removed later. Therefore, to prevent the etching process for removing the dummy gate from affecting the plurality of first channel layers and the plurality of second channel layers, a large etching selectivity ratio is required between the dummy gate and the plurality of first channel layers, and between the dummy gate and the plurality of second channel layers.

[0045] In this embodiment, the dummy gate material includes silicon germanium, and the first channel layer material includes silicon. Specifically, the first dummy gate material layer 201 includes silicon germanium, and the first initial channel layer 202 includes silicon. In other embodiments, the first channel layer material may also be silicon germanium, germanium, or the like; and the first dummy gate material layer material may also be amorphous silicon, polycrystalline silicon, or the like.

[0046] In this embodiment, several methods for forming the first initial channel layer 202 include: forming a first initial channel material layer (not shown in the figure) on the surface of the first dummy gate material layer 201; and patterning the first initial channel material layer.

[0047] Please refer to Figure 3A second dummy gate material layer 203 is formed on the surface of the first dummy gate material layer 201 and several first initial channel layers 202; several second initial channel layers 204 are formed on the surface of part of the second dummy gate material layer 203, and several second initial channel layers 204 are parallel to the second direction Y.

[0048] In this embodiment, the first direction X and the second direction Y are perpendicular to each other.

[0049] The second dummy gate material layer 203 is used to form another part of the dummy gate.

[0050] In this embodiment, the material of the second dummy gate material layer 203 includes silicon germanium. In other embodiments, the material of the second dummy gate material layer may also be amorphous silicon, polysilicon, etc.

[0051] In this embodiment, the material of the second channel layer includes silicon. Specifically, the plurality of second initial channel layers 204 are used to form a plurality of second channel layers, and the material of the second initial channel layer 204 includes silicon. In other embodiments, the material of the second channel layer may also be silicon germanium, germanium, etc.

[0052] In this embodiment, the method for forming the second initial channel layer 204 includes: forming a second initial channel material layer (not shown) on the surface of the second dummy gate material layer 203; and patterning the second initial channel material layer.

[0053] Please refer to Figure 4 A third dummy gate material layer 205 is formed on the surface of the second dummy gate material layer 203 and the surfaces of the plurality of second initial channel layers 204 .

[0054] The third dummy gate material layer 205 is used to form another part of the dummy gate.

[0055] In this embodiment, the material of the third dummy gate material layer 205 includes silicon germanium. In other embodiments, the material of the third dummy gate material layer 205 may also be amorphous silicon, polysilicon, etc.

[0056] Please refer to Figure 5 , patterning the first dummy gate material layer 201, the second dummy gate material layer 203, the third dummy gate material layer 205, several first initial channel layers 202 and several second initial channel layers 204 to form several dummy gate channel structures, forming the first channel layer 206 with the first initial channel layer 202, forming the second channel layer 207 with the second initial channel layer 204, and forming the dummy gate 208 with the first dummy gate material layer 201, the second dummy gate material layer 203 and the third dummy gate material layer 205.

[0057] At this point, a number of dummy gate channel structures are formed on the surface of part of the substrate 200, each of the dummy gate channel structures includes a dummy gate 208, a number of first channel layers 206 and a number of second channel layers 207 separated from each other and located in the dummy gate 208, a number of second channel layers 207 are located on a number of first channel layers 207, a number of first channel layers 206 are parallel to a first direction X, and penetrate the dummy gate 208 in the first direction X, the dummy gate 208 exposes two opposite first side walls of each first channel layer 206 (not shown in the figure), a number of second channel layers 207 are parallel to a second direction Y, and penetrate the dummy gate 208 in the second direction Y, the dummy gate 208 exposes two opposite second side walls of each second channel layer 207 (not shown in the figure), the first direction X and the second direction Y are parallel to the surface of the substrate 200, and the first direction X is different from the second direction Y.

[0058] In this embodiment, each of the dummy gates 208 has two third sidewalls (not shown in the figure) arranged in the first direction X, and two fourth sidewalls (not shown in the figure) arranged in the second direction Y.

[0059] Subsequently, a first source / drain layer is formed on the first sidewall surfaces of the first channel layers 206 ; a second source / drain layer is formed on the second sidewall surfaces of the second channel layers 207 , wherein the second source / drain layer has a different conductivity type from the first source / drain layer.

[0060] In this embodiment, the second source / drain layer is formed after the first source / drain layer is formed.

[0061] Specifically, after forming a plurality of dummy gate channel structures and before forming the first source and drain layer, please refer to Figure 6 .

[0062] Please refer to Figure 6 A spacer structure 209 is formed on the surface of the substrate 200 and on the surfaces of several of the pseudo gate channel structures. The spacer structure 209 is located on the second sidewall surface of each second channel layer 207 and exposes the first sidewall surface of each first channel layer 206.

[0063] The spacer structure 209 is used to prevent the material of the first source / drain layer from growing on the surface of the second channel layer 207 when forming the first source / drain layer.

[0064] In this embodiment, the spacer structure 209 is further located on the fourth sidewall surface and the top surface of each dummy gate 208 , and exposes the third sidewall surface of each dummy gate 208 .

[0065] In this embodiment, the sidewall structure 209 includes a first outer wall 209 a and a second outer wall 209 b located on a surface of the first outer wall 209 , and the first outer wall 209 a and the second outer wall 209 b are made of different materials.

[0066] The material of the sidewall structure 209 includes a dielectric material, and the dielectric material includes one or more of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbide nitride, silicon boronitride, and silicon oxycarbonitride. In this embodiment, the material of the first outer sidewall 209a is silicon nitride, and the material of the second outer sidewall 209b is silicon oxide.

[0067] In this embodiment, the method for forming the spacer structure 209 includes: forming a first outer wall material layer (not shown in the figure) on the surface of the substrate 200 and on the surfaces of several of the dummy gate channel structures; forming a second outer wall material layer (not shown in the figure) on the surface of the first outer wall material layer; forming a first sacrificial layer (not shown in the figure) on a portion of the surface of the second outer wall material layer, the first sacrificial layer exposing the first sidewall surface of each first channel layer 206 and the second outer wall material layer on the third sidewall surface of each dummy gate 208; etching the second outer wall material layer using the first sacrificial layer as a mask to form the second outer wall layer 209a; removing the first sacrificial layer; and after removing the first sacrificial layer, etching the first outer wall material layer using the second outer wall material layer 209a to form the first outer wall layer 209b. Here, during the process of removing the first sacrificial layer, the first spacer material layer can protect the surface of the substrate 200 and the surface of the first channel layer 206, reducing etching damage.

[0068] In this embodiment, the material of the first sacrificial layer includes spin-on carbon or bottom anti-reflective coating (BARC) material.

[0069] In this embodiment, after forming the sidewall structure 209 and before forming the first source and drain layer, please refer to Figure 7 .

[0070] Please refer to Figure 7 A first inner spacer 210 is formed on the third sidewall surface of each dummy gate 208 .

[0071] In this embodiment, the first inner sidewall 210 is also located on a portion of the surface of the substrate 200. The first inner sidewall 210 is used to prevent the material of the first source / drain layer from growing on the surface of the substrate 200 and the surface of the third sidewall when forming the first source / drain layer.

[0072] In this embodiment, the method for forming the first inner sidewall 210 includes: using the sidewall structure 209 as a mask, etching the third sidewall of the dummy gate 208 so that the third sidewall surface of the dummy gate 208 is recessed relative to the first sidewall surface of the first channel layer 206; after etching the third sidewall of the dummy gate 208, forming a first inner sidewall material layer (not shown in the figure) on the surface of the substrate 200, the third sidewall surface of the dummy gate 208, the first sidewall surface of the first channel layer and the surface of the sidewall structure 209; and etching back the first inner sidewall material layer until the first sidewall surface of the first channel layer 206 is exposed.

[0073] The material of the first inner sidewall 210 includes a dielectric material, and the dielectric material includes one or more of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbide nitride, silicon boronitride, and silicon oxycarbonitride. In this embodiment, the material of the first inner sidewall 210 is silicon nitride.

[0074] Please refer to Figure 8 , forming first source and drain layers 211 on the first sidewall surfaces of several of the first channel layers 206 .

[0075] In this embodiment, the conductivity type of the first source / drain layer 211 is P-type, and is used to form a PMOS device. In another embodiment, the conductivity type of the first source / drain layer is P-type.

[0076] In this embodiment, the formation process of the first source / drain layer 211 includes a first selective epitaxial growth process.

[0077] In this embodiment, after forming the first source / drain layer 211 and before forming the second source / drain layer, the sidewall structure 209 on the second sidewall surface of each second channel layer 207 is further etched to expose the two second sidewall surfaces of each second channel layer 207 .

[0078] In this embodiment, after forming the first source and drain layer 211 and before exposing the two second sidewall surfaces of each second channel layer 207, please refer to Figure 9 .

[0079] Please refer to Figure 9 , forming a first etch stop layer 212 on the surface of the first source and drain layer 211 .

[0080] In this embodiment, the first etch stop layer 212 is also located on the surface of the first inner sidewall 210 and the surface of the sidewall structure.

[0081] The material of the first etch stop layer 212 includes a dielectric material, and the dielectric material includes one or more of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbon nitride, and silicon carbon nitride oxynitride. In this embodiment, the material of the first etch stop layer 212 is silicon nitride.

[0082] Please refer to Figure 10 , the first etch stop layer 212 and the spacer structure 209 on the second sidewall surface of each second channel layer 207 are etched to expose two second sidewall surfaces of each second channel layer 207 .

[0083] In this embodiment, the first etch stop layer 212 and the spacer structure 209 on the fourth sidewall surface of each dummy gate 208 are further etched to expose the fourth sidewall surface of each dummy gate 208 .

[0084] In this embodiment, the method for exposing the two second side wall surfaces of each second channel layer 207 and exposing the fourth side wall surface of each pseudo gate 208 includes: forming a second sacrificial layer (not shown in the figure) on the surface of the substrate 200, the surface of the first source and drain layer 209 and the side wall of the pseudo gate channel structure, the second sacrificial layer exposing the fourth side wall surface of each pseudo gate 208 and the side wall structure 209 of the second side wall surface of each second channel layer 207; using the second sacrificial layer 213 as a mask, etching the first etch stop layer 212 until the side wall structure 209 is exposed; after exposing the side wall structure 209, removing the second sacrificial layer; after removing the second sacrificial layer, etching the side wall structure 209 using the first etch stop layer 212 as a mask.

[0085] In this embodiment, the material of the second sacrificial layer includes spin-on carbon or bottom anti-reflective coating material.

[0086] Please refer to Figure 11 After exposing the two second side wall surfaces of each second channel layer 207 and exposing the fourth side wall surface of each dummy gate 208, and before forming the second source and drain layer, a second inner sidewall 215 is also formed on the fourth side wall surface of each dummy gate 208.

[0087] In this embodiment, the second inner sidewall 215 is also located on a portion of the surface of the substrate 200. The second inner sidewall 215 is used to prevent the second source / drain layer material from growing on the surface of the substrate 200 and the surface of the fourth sidewall when forming the second source / drain layer.

[0088] In this embodiment, the method for forming the second inner sidewall 215 includes: etching the fourth sidewall of the dummy gate 208 so that the fourth sidewall surface of the dummy gate 208 is recessed relative to the second sidewall surface of the second channel layer 207; after etching the fourth sidewall of the dummy gate 208, forming a second inner sidewall material layer (not shown in the figure) on the surface of the substrate 200, the fourth sidewall surface of the dummy gate 208, and the second sidewall surface of the second channel layer 207; and etching back the second inner sidewall material layer until the second sidewall surface of the second channel layer 207 is exposed.

[0089] The material of the second inner sidewall 215 includes one or more of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbide nitride, silicon boronitride, and silicon oxycarbonitride. In this embodiment, the material of the second inner sidewall 215 is silicon nitride.

[0090] Please refer to Figure 12 A second source / drain layer 216 is formed on the second sidewall surfaces of the plurality of second channel layers 207 , and the second source / drain layer 216 has a different conductivity type from that of the first source / drain layer 211 .

[0091] In this embodiment, the conductivity type of the second source / drain layer 216 is N-type, and is used to form an NMOS device. In another embodiment, the conductivity type of the second source / drain layer is P-type.

[0092] In this embodiment, the formation process of the second source / drain layer 216 includes a second selective epitaxial growth process.

[0093] In this embodiment, after forming the first source drain layer 211 and the second source drain layer 216, please refer to Figure 13 .

[0094] Subsequently, an interlayer dielectric layer is formed on the surface of the substrate, the surface of the first source / drain layer 211 , the surface of the second source / drain layer 216 , and the surfaces of several of the dummy gate channel structures, wherein the interlayer dielectric layer exposes the top surface of each of the dummy gates 208 .

[0095] In this embodiment, after forming the second source and drain layer and before forming the interlayer dielectric layer, please refer to Figure 13 .

[0096] Please refer to Figure 13 , a second etch stop layer 217 is formed on the surface of the second source / drain layer 216 .

[0097] The material of the second etch stop layer 217 includes a dielectric material, and the dielectric material includes one or more of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbon nitride, and silicon carbon nitride oxynitride. In this embodiment, the material of the second etch stop layer 217 is silicon nitride.

[0098] In this embodiment, the second etch stop layer 217 is also located on the surface of the second inner sidewall 215 and the surface of the second sacrificial layer 213 .

[0099] Please refer to Figure 14 An interlayer dielectric layer 218 is formed on the surface of the substrate 200 , the surface of the first source / drain layer 211 , the surface of the second source / drain layer 216 , and the surfaces of several of the dummy gate channel structures, and the interlayer dielectric layer 218 exposes the top surface of each of the dummy gates 208 .

[0100] In this embodiment, after forming the second etch stop layer 217 and before forming the interlayer dielectric layer, the second sacrificial layer 213 is further removed.

[0101] Please refer to Figure 15 After forming the interlayer dielectric layer 218 , a gate 219 is formed to replace the dummy gate 208 , and a gate channel structure is formed using the dummy gate channel structure.

[0102] At this point, in the gate channel structure formed, several second channel layers 207 are located on several first channel layers 206, several first channel layers 206 are parallel to the first direction X, and several second channel layers 207 are parallel to the second direction Y, so that the arrangement directions of the channel layers between the upper and lower devices are different, thereby making the first source and drain layers 211 and the second source and drain layers 216 staggered in space. When the conductive layer is used to electrically lead out the first source and drain layers 211 and the second source and drain layers 216 respectively, the mutual contact between the conductive layers caused by the stacked arrangement between the first source and drain layers 211 and the second source and drain layers 216 is avoided, which is beneficial to reducing the probability of short circuit anomalies between the upper and lower devices, and improving the performance of the complementary field effect device.

[0103] In this embodiment, the method of replacing the dummy gate 208 to form the gate 219 includes: removing the dummy gate 208, forming a gate groove (not shown in the figure) in the interlayer dielectric layer 218, the gate groove exposing a number of the first channel layers 206 and a number of the second channel layers 207; and forming the gate 219 in the gate groove.

[0104] In this embodiment, the method for forming the gate 219 also includes: forming a gate dielectric material layer (not shown in the figure) in the groove; forming a work function material layer (not shown in the figure) on the surface of the gate dielectric material layer; forming a metal material layer (not shown in the figure) on the surface of the work function material layer; flattening the metal material layer, the work function material layer and the gate dielectric material layer until the surface of the interlayer dielectric layer 218 is exposed, and forming the gate 219 with the gate dielectric material layer, the work function material layer and the metal material layer in the groove.

[0105] Subsequently, a first conductive layer (not shown) is formed on the surface of the first source / drain layer 211, and a second conductive layer (not shown) is formed on the surface of the second source / drain layer 216. The first conductive layer and the second conductive layer are used for electrical extraction.

[0106] Accordingly, the embodiment of the present invention further provides a semiconductor structure formed by the above method, please continue to refer to Figure 15 The semiconductor structure includes: a substrate 200; a plurality of gate channel structures located on a portion of the surface of the substrate 200, each of the gate channel structures including a gate 219, a plurality of first channel layers 206 (such as Figure 5 As shown) and a plurality of second channel layers 207 (as shown Figure 5 As shown), a number of second channel layers 207 are located on a number of first channel layers 206, and a number of first channel layers 206 are parallel to a first direction X and penetrate the gate 219 in the first direction X, and the gate 219 exposes two opposite first side walls of each first channel layer 206 (not shown in the figure), a number of second channel layers 207 are parallel to a second direction Y and penetrate the gate 219 in the second direction Y, and the gate 219 exposes two opposite second side walls of each second channel layer 207 (not shown in the figure), the first direction X and the second direction Y are parallel to the surface of the substrate 200, and the first direction X is different from the second direction Y; first source and drain layers 211 are located on the first side wall surfaces of a number of first channel layers 206; second source and drain layers 216 are located on the second side wall surfaces of a number of second channel layers 207, and the second source and drain layers 216 have a different conductivity type from the first source and drain layer 211.

[0107] At this point, several second channel layers 207 are located on several first channel layers 206, several first channel layers 206 are parallel to the first direction X, and several second channel layers 207 are parallel to the second direction Y, so that the arrangement directions of the channel layers between the upper and lower devices are different, thereby making the first source and drain layers 211 and the second source and drain layers 216 staggered in space. When the conductive layer is used to electrically lead out the first source and drain layers 211 and the second source and drain layers 216 respectively, the mutual contact between the conductive layers caused by the stacked arrangement between the first source and drain layers 211 and the second source and drain layers 216 is avoided, which is beneficial to reducing the probability of short circuit anomalies between the upper and lower devices, and improving the performance of the complementary field effect device.

[0108] In this embodiment, the semiconductor structure further includes: an interlayer dielectric layer 218 located on the surface of the substrate 200, the surface of the first source and drain layer 211, the surface of the second source and drain layer 216, and the surfaces of several gate channel structures, and the interlayer dielectric layer 218 exposes the top surface of each gate 219.

[0109] In this embodiment, the semiconductor structure further includes: a first inner sidewall 210 (eg, Figure 8 The second inner sidewall 215 (as shown) located on the two sidewalls of each gate 219 in the second direction Y Figure 11 shown).

[0110] In this embodiment, the semiconductor structure further includes: a first etch stop layer 212 located between the first source / drain layer 211 and the interlayer dielectric layer 218 ; and a second etch stop layer 217 located between the second source / drain layer 216 and the interlayer dielectric layer 218 .

[0111] In this embodiment, the first direction X and the second direction Y are perpendicular to each other.

[0112] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be based on the scope defined by the claims.

Claims

1. A semiconductor structure, characterized in that include: substrate; a plurality of gate channel structures located on a portion of the substrate surface, each of the gate channel structures comprising a gate, a plurality of first channel layers and a plurality of second channel layers located within the gate and separated from each other, the plurality of second channel layers located on the plurality of first channel layers, the plurality of first channel layers being parallel to a first direction and penetrating the gate in the first direction, the gate exposing two opposite first sidewalls of each first channel layer, the plurality of second channel layers being parallel to a second direction and penetrating the gate in the second direction, the gate exposing two opposite second sidewalls of each second channel layer, the first direction and the second direction being parallel to the substrate surface, and the first direction being different from the second direction; a first source and drain layer located on the first sidewall surfaces of the plurality of first channel layers; A second source / drain layer is located on the second sidewall surfaces of the plurality of second channel layers, and the second source / drain layer has a different conductivity type from that of the first source / drain layer.

2. The semiconductor structure according to claim 1, wherein Also includes: An interlayer dielectric layer is located on the surface of the substrate, the surface of the first source / drain layer, the surface of the second source / drain layer, and the surfaces of several gate channel structures, wherein the interlayer dielectric layer exposes the top surface of each gate.

3. The semiconductor structure according to claim 2, wherein: Also includes: a first etch stop layer located between the first source / drain layer and the interlayer dielectric layer; A second etch stop layer is located between the second source / drain layer and the interlayer dielectric layer.

4. The semiconductor structure according to claim 1, wherein: Also includes: a first inner sidewall located on two sidewall surfaces of each of the gates arranged in the first direction; The first inner sidewall is also located between the substrate surface and the first source / drain layer; and the second inner sidewall is located on two sidewalls of each gate in the second direction.

5. The semiconductor structure according to claim 1, wherein The first direction and the second direction are perpendicular to each other.

6. A method for forming a semiconductor structure, characterized in that: include: providing a substrate; forming a plurality of dummy gate channel structures on a portion of the substrate surface, each of the dummy gate channel structures comprising a dummy gate, a plurality of first channel layers and a plurality of second channel layers that are separated from each other and located within the dummy gate, wherein the plurality of second channel layers are located on the plurality of first channel layers, the plurality of first channel layers are parallel to a first direction and penetrate the dummy gate in the first direction, the dummy gate exposes two opposite first sidewalls of each of the first channel layers, the plurality of second channel layers are parallel to a second direction and penetrate the dummy gate in the second direction, the dummy gate exposes two opposite second sidewalls of each of the second channel layers, the first direction and the second direction are parallel to the substrate surface, and the first direction is different from the second direction; forming a first source and drain layer on the first sidewall surfaces of a plurality of the first channel layers; A second source / drain layer is formed on the second sidewall surfaces of a plurality of the second channel layers, wherein the second source / drain layer has a different conductivity type from that of the first source / drain layer.

7. The method for forming a semiconductor structure according to claim 6, wherein: After forming the first source-drain layer and the second source-drain layer, the method further includes: forming an interlayer dielectric layer on the surface of the substrate, the surface of the first source-drain layer, the surface of the second source-drain layer, and the surfaces of several of the pseudo gate channel structures, wherein the interlayer dielectric layer exposes the top surface of each of the pseudo gates; after forming the interlayer dielectric layer, forming a gate to replace the pseudo gate, and forming a gate-channel structure with the pseudo gate channel structure.

8. The method for forming a semiconductor structure according to claim 7, wherein: After forming the first source / drain layer, the second source / drain layer is formed; the process of forming the first source / drain layer includes a first selective epitaxial growth process; the process of forming the second source / drain layer includes a second selective epitaxial growth process.

9. The method for forming a semiconductor structure according to claim 8, wherein: After forming several pseudo gate channel structures and before forming the first source and drain layer, it also includes: forming a sidewall structure on the surface of the substrate and the surfaces of several pseudo gate channel structures, the sidewall structure is located on the second sidewall surface of each second channel layer, and exposes the first sidewall surface of each first channel layer; each pseudo gate has two third sidewalls arranged in the first direction and two fourth sidewalls arranged in the second direction; the sidewall structure is also located on the fourth sidewall surface and the top surface of each pseudo gate, and exposes the third sidewall surface of each pseudo gate.

10. The method for forming a semiconductor structure according to claim 9, wherein: The sidewall structure includes a first outer wall and a second outer wall located on the surface of the first outer wall, and the materials of the first outer wall and the second outer wall are different; the method for forming the sidewall structure includes: forming a first outer wall material layer on the surface of the substrate and the surfaces of several of the pseudo gate channel structures; forming a second outer wall material layer on the surface of the first outer wall material layer; forming a first sacrificial layer on the surface of part of the second outer wall material layer, the first sacrificial layer exposing the second outer wall material layer on the first side wall surface of each of the first channel layers and the third side wall surface of each of the pseudo gates; using the first sacrificial layer as a mask, etching the second outer wall material layer to form the second outer wall layer; removing the first sacrificial layer; after removing the first sacrificial layer, etching the first outer wall material layer with the second outer wall material layer to form the first outer wall layer.

11. The method for forming a semiconductor structure according to claim 10, wherein: After forming the spacer structure and before forming the first source and drain layer, a first inner spacer is formed on the third sidewall surface of each dummy gate; the first inner spacer is also located on a portion of the substrate surface; The method for forming the first inner sidewall includes: using the sidewall structure as a mask, etching the third sidewall of the dummy gate so that the third sidewall surface of the dummy gate is recessed relative to the first sidewall surface of the first channel layer; after etching the third sidewall of the dummy gate, forming a first inner sidewall material layer on the substrate surface, the third sidewall surface of the dummy gate, the first sidewall surface of the first channel layer and the sidewall structure surface; etching back the first inner sidewall material layer until the first sidewall surface of the first channel layer is exposed.

12. The method for forming a semiconductor structure according to claim 10, wherein: After forming the first source and drain layer and before forming the second source and drain layer, it also includes: etching the side wall structure of the second side wall surface of each second channel layer to expose the two second side wall surfaces of each second channel layer; etching the side wall structure of the fourth side wall surface of each pseudo gate to expose the fourth side wall surface of each pseudo gate.

13. The method for forming a semiconductor structure according to claim 12, wherein: After forming the first source and drain layer and before exposing the two second sidewall surfaces of each second channel layer, a first etch stop layer is formed on the surface of the first source and drain layer; the first etch stop layer is also located on a portion of the substrate surface and the sidewall structure surface.

14. The method for forming a semiconductor structure according to claim 13, wherein: The method for exposing the two second side wall surfaces of each second channel layer and the fourth side wall surface of each pseudo gate includes: forming a second sacrificial layer on the substrate surface, the first source and drain layer surface and the side wall of the pseudo gate channel structure, the second sacrificial layer exposing the fourth side wall surface of each pseudo gate and the side wall structure of the second side wall surface of each second channel layer; using the second sacrificial layer as a mask, etching the first etch stop layer until the side wall structure is exposed; after exposing the side wall structure, removing the second sacrificial layer; after removing the second sacrificial layer, etching the side wall structure using the first etch stop layer as a mask.

15. The method for forming a semiconductor structure according to claim 12, wherein: After exposing the two second side wall surfaces of each second channel layer and exposing the fourth side wall surface of each dummy gate, and before forming the second source and drain layer, it also includes: forming a second inner side wall on the fourth side wall surface of each dummy gate; the second inner side wall is also located on a portion of the substrate surface; the method for forming the second inner side wall includes: etching the fourth side wall of the dummy gate so that the fourth side wall surface of the dummy gate is recessed relative to the second side wall surface of the second channel layer; after etching the fourth side wall of the dummy gate, forming a second inner side wall material layer on the substrate surface, the fourth side wall surface of the dummy gate, and the second side wall surface of the second channel layer; etching back the second inner side wall material layer until the second side wall surface of the second channel layer is exposed.

16. The method for forming a semiconductor structure according to claim 12, wherein: After forming the second source / drain layer and before forming the interlayer dielectric layer, the method further includes: forming a second etch stop layer on the surface of the second source / drain layer.

17. The method for forming a semiconductor structure according to claim 7, wherein: The method for forming several of the pseudo gate channel structures includes: forming a first pseudo gate material layer on the surface of the substrate; forming several first initial channel layers on the surface of part of the first pseudo gate material layer, and several of the first initial channel layers are parallel to the first direction; forming a second pseudo gate material layer on the surface of the first pseudo gate material layer and several of the first initial channel layers; forming several second initial channel layers on the surface of part of the second pseudo gate material layer, and several of the second initial channel layers are parallel to the second direction; forming a third pseudo gate material layer on the surface of the second pseudo gate material layer and several of the second initial channel layers; patterning the first pseudo gate material layer, the second pseudo gate material layer, the third pseudo gate material layer, several of the first initial channel layers and several of the second initial channel layers to form several of the pseudo gate channel structures, forming the first channel layer with the first initial channel layer, forming the second channel layer with the second initial channel layer, and forming the pseudo gate with the first pseudo gate material layer, the second pseudo gate material layer and the third pseudo gate material layer.

18. The method for forming a semiconductor structure according to claim 7, wherein: The method of forming the gate by replacing the dummy gate includes: removing the dummy gate, forming a gate groove in the interlayer dielectric layer, wherein the gate groove exposes a plurality of the first channel layers and a plurality of the second channel layers; The gate is formed in the gate groove.

19. The method for forming a semiconductor structure according to claim 6, wherein: The material of the first channel layer includes silicon; the material of the second channel layer includes silicon; and the material of the dummy gate includes silicon germanium.

20. The method for forming a semiconductor structure according to claim 6, wherein: Also includes: forming a first conductive layer on a surface of the first source / drain layer; A second conductive layer is formed on the surface of the second source-drain layer.

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