A micro-display structure and preparation method for improving Micro LED light efficiency

Abstract

The present application discloses a micro-display structure and preparation method for improving the luminous efficiency of Micro LED, the structure comprising: a silicon-based CMOS driving panel; an LED unit formed by an epitaxial layer, the LED unit being connected to the silicon-based CMOS driving panel via a bonding metal layer, and the anode of the LED unit being independently arranged; an electron blocking layer wrapped around the side wall of the LED unit, the surface of the electron blocking layer being etched to form an optical extraction cavity; a conductive film layer covering the top of the LED unit, the conductive film layer connecting the cathodes of each LED unit in common; the method comprising S1, preparation of a first bonding metal layer; S2, preparation of a transparent conductive film layer; S3, preparation of an epitaxial metal layer; S4, eutectic bonding and substrate processing; S5, formation of an LED unit; S6, independence of the anode; S7, growth of an electron blocking layer; S8, formation of an optical extraction cavity; S9, common connection of the cathode; the present application significantly improves the luminous efficiency, greatly improves the brightness in the vertical direction, is suitable for large-scale mass production, has low preparation cost, and greatly enhances the life of the device.

Description

Technical Field

[0001] The present invention relates to the field of Micro LED display technology, and more particularly to a micro display structure and a preparation method for improving the light efficiency of Micro LEDs. Background Art

[0002] As a new generation of display technology, micro light-emitting diode (Micro LED) display technology has significant advantages such as high brightness, low power consumption, fast response speed and long life. It shows broad application prospects in near-eye display, ultra-large display screen and other fields. As the size of Micro LED devices shrinks to the micron level, the sidewall area of ​​the device increases significantly, resulting in an enhanced non-radiative recombination effect and a significant decrease in luminous efficiency. At the same time, the proportion of lateral light in the traditional Micro LED structure is too high, and the vertical light brightness is insufficient, which makes it difficult to meet the high brightness and high contrast requirements of high-end display devices.

[0003] In the existing technology, methods for improving the luminous efficiency of Micro LEDs mainly include surface texturing and photonic crystal structure design. However, these methods generally have problems such as complex processes, high preparation costs, and difficulty in integration with existing CMOS driver circuits. Therefore, how to improve the light extraction efficiency of Micro LEDs through structural innovation and process optimization without significantly increasing process complexity, especially enhancing the brightness of light in the vertical direction, has become a technical problem that needs to be solved urgently in this field. Summary of the Invention

[0004] The purpose of the present invention is to provide a micro-display structure and preparation method for improving the luminous efficiency of Micro LEDs. By constructing an optical extraction cavity structure on the side wall of the LED unit, the light extraction capability of the side wall is enhanced, and the current conduction path is optimized through the common cathode electrode design, thereby significantly improving the optical power, luminous efficiency and vertical brightness of the device.

[0005] In order to solve the above technical problems, the technical solution adopted by the present invention is:

[0006] A micro-display structure for improving the light efficiency of Micro LEDs, comprising:

[0007] A silicon-based CMOS driving panel, wherein a bonding metal layer is provided on the surface of the silicon-based CMOS driving panel;

[0008] An LED unit formed by an epitaxial layer, wherein the LED unit is connected to the silicon-based CMOS driver panel via a bonding metal layer, and the anode of the LED unit is independently provided;

[0009] An electron blocking layer wrapped around the side wall of the LED unit, wherein the surface of the electron blocking layer is etched to form an optical extraction cavity;

[0010] A conductive film layer covers the top of the LED unit, and the conductive film layer connects the cathodes of the LED units in common.

[0011] In a preferred embodiment, the bonding metal layer on the silicon-based CMOS driving panel consists of a Cr or Ti adhesion layer, a Pt layer and an Au layer, with thicknesses of 5-50 nm for the Cr or Ti adhesion layer, 200 nm for the Pt layer and 200 nm for the Au layer.

[0012] In a preferred embodiment, the optical extraction cavity is made of a 300-500 nm silicon oxide layer, which is formed by etching an electron blocking layer through a metal particle mask formed by reflowing metal germanium, tin or indium.

[0013] In a preferred solution, the conductive film layer is a 300nm thick ITO or ZnO transparent conductive film layer.

[0014] In addition, the present application also provides a method for preparing a micro display structure for improving the light efficiency of Micro LEDs, comprising the following steps:

[0015] S1, preparation of a first bonding metal layer: forming a first bonding metal layer on the surface of a silicon-based CMOS driver panel by metal sputtering or electron beam evaporation, wherein the first bonding metal layer includes a Cr or Ti adhesion layer with a thickness of 5-50 nm, a Pt layer with a thickness of 200 nm, and an Au layer with a thickness of 200 nm, and the electron beam evaporation rate is 1-2 nm / s;

[0016] S2, preparing a transparent conductive film layer: forming a transparent conductive film layer with a thickness of 50-200 nm on the epitaxial layer by electron beam evaporation or magnetron sputtering, the evaporation rate of the transparent conductive film layer being 1-2 nm / s, and then annealing the transparent conductive film layer;

[0017] S3, preparing an epitaxial metal layer: forming a second bonding metal layer on the transparent conductive film layer by electron beam evaporation, wherein the second bonding metal layer includes a 5 nm thick Cr or Ti layer, a 20 nm thick Pt layer, and a 200 nm thick Au layer, and the electron beam evaporation rate is 0.5-2 nm / s;

[0018] S4, eutectic bonding and substrate processing: eutectic bonding the silicon-based CMOS driving panel and the epitaxial layer by a metal bonding machine, wherein the first bonding metal layer and the second bonding metal layer are eutectic bonded to form a bonding metal layer, and after bonding, the substrate of the epitaxial layer is removed;

[0019] S5, forming LED units: depositing a 300-1000 nm thick silicon oxide film layer on the surface of the epitaxial layer by chemical vapor deposition, spin-coating a positive photoresist on the silicon oxide film layer, transferring a mask pattern to the photoresist after exposure and development using a stepper lithography machine to obtain a truncated cone-shaped mask layer, transferring the pattern of the mask layer to the silicon oxide film layer and the epitaxial layer by plasma chemical etching, and obtaining periodically arranged LED units after etching;

[0020] S6, anode independence: spin-coating a positive photoresist on the surface of the LED unit, transferring the mask pattern to the photoresist after exposure and development using a stepper, to obtain a truncated cone-shaped mask layer that completely covers each of the LED units, etching the area outside the mask layer using an ion beam etching process at an etching angle of 0°-15° and an etching voltage of 300-500V to etch through the transparent conductive film layer and the bonding metal layer, thereby achieving anode independence of the LED unit;

[0021] S7, electron blocking layer growth: growing a 300-500 nm silicon oxide film layer as an electron blocking layer on the surface of the LED unit by chemical vapor deposition;

[0022] S8, forming an optical extraction cavity: spin-coating a negative photoresist on the surface of the LED unit, transferring the mask pattern to the photoresist after exposure and development using a stepper, evaporating metal germanium, tin or indium on the surface by electron beam evaporation to a thickness of 20-80 nm, removing the metal outside the side wall of the LED unit by acetone ultrasonic stripping, annealing and reflowing the metal into metal balls in a rapid annealing furnace at an annealing temperature of 350-450° C., and transferring the morphology of the metal balls to the surface of the silicon oxide film layer on the side wall by plasma chemical etching to form an optical extraction cavity;

[0023] S9, cathode common connection: spin-coat positive photoresist on the surface of the LED unit, form a hole above the LED unit through exposure and development, the size of the hole is smaller than or equal to the upper surface of the LED unit, remove the silicon oxide film layer in the hole by plasma chemical etching, and connect the cathode of each LED unit in common by electron beam evaporation of a 300nm transparent conductive film layer.

[0024] In a preferred solution, in step S2, the annealing temperature is 500-600°C, the annealing time is 3-10 minutes, the annealing atmosphere is nitrogen or oxygen, and the gas flow rate is 3-10 sccm.

[0025] In a preferred solution, in step S4, the bonding temperature is 260-350° C., the pressure is 25-80 KN, and the bonding time is 10-30 min.

[0026] In a preferred embodiment, in step S5, the reaction gas for chemical vapor deposition is and , the deposition power is 100-500W, the deposition temperature is 250-350℃; the gas for etching the epitaxial layer is and , the gas flow rate is 20-100sccm.

[0027] In a preferred embodiment, in step S8, the plasma chemical etching gas is 20 sccm. and 30 sccm , the upper plate power is 400W and the lower plate power is 50W.

[0028] In a preferred embodiment, in step S9, the gas used for the plasma chemical etching is 80 sccm. , the upper plate power is 200-500W, and the lower plate power is 50-100W.

[0029] Due to the application of the above technical solution, the beneficial effects of this application compared with the prior art are:

[0030] The present application provides a micro-display structure and preparation method for improving the luminous efficiency of Micro LEDs, which significantly improves the luminous efficiency. The sidewall optical extraction cavity structure effectively increases the amount of light output from the sidewall of the LED, significantly improves the light power compared to the traditional structure, and greatly improves the luminous efficiency; the optical extraction cavity is combined with the common cathode structure to narrow the divergence angle of the LED, and the vertical brightness is greatly improved, meeting the high brightness requirements of high-end applications such as near-eye displays; the preparation process is based on existing semiconductor manufacturing technology, is highly compatible with silicon-based CMOS drive circuits, is suitable for large-scale mass production, and has low preparation costs; the multi-layer metal bonding and dielectric protection structure ensure the electrical reliability and structural stability of the device, greatly enhancing the device life. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] In order to more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the specific embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0032] Figure 1 A schematic diagram of a micro-display structure for improving the light efficiency of Micro LEDs according to the present invention;

[0033] Figure 2 This is a flow chart of a method for preparing a micro display structure for improving Micro LED light efficiency according to the present invention;

[0034] Figure 3 Schematic diagram of step S1 in the preparation method of Example 2 of the present invention;

[0035] Figure 4 Schematic diagram of steps S2 and S3 in the preparation method of Example 2 of the present invention;

[0036] Figure 5 Schematic diagram of step S4 in the preparation method of Example 2 of the present invention;

[0037] Figure 6 Schematic diagram of step S5 in the preparation method of Example 2 of the present invention;

[0038] Figure 7 Schematic diagram of step S6 in the preparation method of Example 2 of the present invention;

[0039] Figure 8 Schematic diagram of step S7 in the preparation method of Example 2 of the present invention;

[0040] Figure 9 、 Figure 10 Schematic diagram of step S8 in the preparation method of Example 2 of the present invention;

[0041] Figure 11 Schematic diagram of step S9 in the preparation method of Example 2 of the present invention;

[0042] Among them, 1. Silicon-based CMOS driver panel; 2. Bonding metal layer; 21. First bonding metal layer; 3. Epitaxial layer; 31. Second bonding metal layer; 4. LED unit; 5. Anode; 6. Electron blocking layer; 7. Optical extraction cavity; 8. Conductive film layer; 9. Cathode. DETAILED DESCRIPTION

[0043] In order to enable those skilled in the art to better understand the present invention, the following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments in the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts should fall within the scope of protection of this application.

[0044] It should be noted that the terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequential order. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present application described here. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0045] In this application, terms such as "upper," "lower," "left," "right," "front," "back," "top," "bottom," "inner," "outer," "center," "vertical," "horizontal," "transverse," and "longitudinal" indicate positions or locations based on the positions or locations shown in the accompanying drawings. These terms are primarily intended to better describe the present invention and its embodiments and are not intended to limit the devices, elements, or components indicated to having a specific orientation, or to being constructed or operated in a specific orientation.

[0046] Furthermore, some of the above terms may be used to express other meanings besides indicating a position or location. For example, the term "on" may also be used to indicate a dependency or connection in certain circumstances. Those skilled in the art will understand the specific meanings of these terms in the present invention based on the specific circumstances.

[0047] Furthermore, the terms "installed," "disposed," "provided with," "connected," "connected," and "socketed" should be interpreted broadly. For example, they can refer to fixed connections, removable connections, or integral structures; mechanical connections or electrical connections; direct connections or indirect connections through an intermediary; or internal communication between two devices, elements, or components. Those skilled in the art will understand the specific meanings of these terms in the present invention based on specific circumstances.

[0048] It should be noted that, in the absence of conflict, the embodiments and features of the embodiments in this application can be combined with each other. The present application will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0049] Example 1

[0050] See Figure 1 A micro-display structure for improving the light efficiency of Micro LEDs, comprising:

[0051] A silicon-based CMOS driver panel 1 is provided with a bonding metal layer 2 composed of a Cr or Ti adhesion layer, a Pt layer, and an Au layer on its surface. The Cr or Ti adhesion layer has a thickness of 5-50 nm, the Pt layer has a thickness of 200 nm, and the Au layer has a thickness of 200 nm. The silicon-based CMOS driver panel 1 integrates pixel circuits, driver circuits, and interface circuits, providing independent addressing and driving capabilities for the Micro LED array.

[0052] The LED units 4 are formed by the epitaxial layer 3, and are connected to the silicon-based CMOS driver panel 1 via the bonding metal layer 2. The anodes 5 of the LED units 4 are independently provided, ensuring that the silicon-based CMOS driver panel 1 can independently control each LED unit 4.

[0053] An electron blocking layer 6 wrapped around the sidewalls of the LED unit 4 is etched to form an optical extraction cavity 7. The optical extraction cavity 7 is made of a 300-500nm thick silicon oxide layer and is formed by etching the electron blocking layer 6 through a metal particle mask formed by reflowing metal germanium, tin, or indium. This cavity effectively scatters and reflects light emitted from the sidewalls, improving light extraction efficiency.

[0054] A 300 nm thick ITO or ZnO transparent conductive film layer 8 covers the top of the LED unit 4 . The conductive film layer 8 connects the cathodes 9 of the LED units 4 to form a common cathode 9 structure, thereby achieving unified electrical connection of the LED units 4 .

[0055] Example 2

[0056] In addition, the present application also provides a method for preparing a micro display structure for improving the light efficiency of Micro LEDs, comprising the following steps:

[0057] S1, preparation of the first bonding metal layer 21: forming the first bonding metal layer 21 on the surface of the silicon-based CMOS driving panel 1 by metal sputtering or electron beam evaporation, wherein the first bonding metal layer 21 includes a Cr or Ti adhesion layer with a thickness of 5-50 nm, a Pt layer with a thickness of 200 nm, and an Au layer with a thickness of 200 nm. The electron beam evaporation rate is 1-2 nm / s to ensure uniformity and adhesion of the metal layer;

[0058] S2, preparation of transparent conductive film layer 8: forming a transparent conductive film layer 8 with a thickness of 50-200 nm on the epitaxial layer 3 by electron beam evaporation or magnetron sputtering, the evaporation rate of the transparent conductive film layer 8 being 1-2 nm / s, and then annealing the transparent conductive film layer 8 at an annealing temperature of 500-600° C. for 3-10 min in a nitrogen or oxygen atmosphere at a gas flow rate of 3-10 sccm, to optimize the crystal quality and conductive properties of the transparent conductive film layer 8;

[0059] S3, Preparation of Metal Layer of Epitaxial Layer 3: Forming a second bonding metal layer 31 on the transparent conductive film layer 8 by electron beam evaporation. The second bonding metal layer 31 includes a 5 nm thick Cr or Ti layer, a 20 nm thick Pt layer, and a 200 nm thick Au layer. The electron beam evaporation rate is 0.5-2 nm / s, providing a good metal interface for the subsequent bonding process.

[0060] S4, eutectic bonding and substrate processing: The silicon-based CMOS driving panel 1 and the epitaxial layer 3 are eutectic bonded by a metal bonding machine, wherein the first bonding metal layer 21 and the second bonding metal layer 31 are eutectic bonded to form a bonding metal layer 2, the bonding temperature is 260-350°C, the pressure is 25-80KN, and the time is 10-30 minutes; after bonding, the substrate of the epitaxial layer is removed to facilitate subsequent etching processing; different removal processes are performed for epitaxial layers 3 of different materials, as follows:

[0061] For sapphire-based GaN epitaxy, after bonding, the sapphire substrate of the epitaxial layer 3 is removed by laser stripping. The laser wavelength is 200-300nm, the frequency is 800-1200Hz, the stage temperature is 20-50°C, the period spacing is 15μm, and the stripping is performed from the outside to the inside in an annular manner. After stripping, the epitaxial layer is thinned to 1-1.5μm by chemical grinding;

[0062] For silicon-based gallium nitride epitaxy, after bonding, the silicon substrate of the epitaxial layer 3 is removed by wafer thinning, wet processing or plasma chemical etching (ICP). The grinding wheel for wafer thinning has a mesh size of 600-2000 and a grinding wheel speed of 100-2000 rpm. The silicon substrate is thinned to a thickness of 50-150 μm. The solution for wet removal of the silicon substrate is hydrofluoric acid (HF), hydrogen peroxide ( ), HF: The ratio is 1:1, 1:2, 2:1, 5:1, etc.;

[0063] For GaAs-based AlGaInP epitaxy, the GaAs substrate of the AlGaInP epitaxy is removed by wet method after bonding. The solution for wet removal of the GaAs substrate is ammonia water ( ), hydrogen peroxide ( ), : The ratio is 1:5, 1:6, 1:7, 1:8, etc.;

[0064] S5, LED unit 4 formation: a 300-1000 nm silicon oxide film is deposited on the surface of the epitaxial layer 3 by chemical vapor deposition (CVD), and the reaction gas is and , the deposition power is 100-500W, the deposition temperature is 250-350℃, 1.5μm positive photoresist is spin-coated on the silicon oxide film layer, and the mask pattern is transferred to the photoresist after exposure and development by a stepper lithography machine to obtain a truncated cone mask layer, and the pattern of the mask layer is transferred to the silicon oxide film layer and the epitaxial layer 3 by plasma chemical etching (ICP). The etching gas is and , the gas flow rate is 20-100 sccm, and after etching, a periodically arranged LED unit 4 is obtained;

[0065] S6, anode 5 independence: 2 μm positive photoresist is spin-coated on the surface of the LED unit 4. After exposure and development using a stepper, the mask pattern is transferred to the photoresist to obtain a truncated cone-shaped mask layer. The mask layer completely covers each LED unit 4. The area outside the mask layer is etched through by ion beam etching (IBE) at an etching angle of 0°-15° and an etching voltage of 300-500 V to etch through the transparent conductive film layer 8 and the bonding metal layer 2, thereby achieving independence of the anode 5 of the LED unit 4.

[0066] S7, electron blocking layer 6 growth: growing a 300-500 nm silicon oxide film layer as the electron blocking layer 6 on the surface of the LED unit 4 by chemical vapor deposition, protecting the ITO conductive film layer 8 and the bonding metal layer 2 exposed after IBE etching, and passivating the surface of the LED unit 4;

[0067] S8, optical extraction cavity 7 is formed: 2μm negative photoresist is spin-coated on the surface of the LED unit 4, and the mask pattern is transferred to the photoresist after exposure and development by a stepper lithography machine. Metal germanium, tin or indium is evaporated on the surface by electron beam evaporation with a thickness of 20-80nm. The metal outside the side wall of the LED unit 4 is removed by acetone ultrasonic stripping. The metal is annealed and reflowed into metal balls in a rapid annealing furnace at an annealing temperature of 350-450℃. The metal is etched by plasma chemical etching (ICP) with a gas of 20sccm. and 30 sccm , the upper plate power is 400W, the lower plate power is 50W, and the morphology of the metal ball is transferred to the surface of the silicon oxide film layer on the side wall to form an optical extraction cavity 7;

[0068] S9, cathode 9 is connected: 2 μm positive photoresist is spin-coated on the surface of the LED unit 4, and a hole is formed above the LED unit 4 by exposure and development. The size of the hole is smaller than or equal to the upper surface of the LED unit 4, and the hole is etched by plasma chemical (ICP) with a gas of 80 sccm. The power of the upper plate is 200-500W, and the power of the lower plate is 50-100W. The silicon oxide film layer in the hole is removed, and a 300nm transparent conductive film layer is deposited by electron beam evaporation. The cathode 9 of each LED unit 4 is connected in common to realize the electrical connection of the device.

[0069] Example 3

[0070] A method for preparing a micro-display structure for improving the light efficiency of Micro LEDs comprises the following steps:

[0071] S1, preparation of the first bonding metal layer 21: forming the first bonding metal layer 21 on the surface of the silicon-based CMOS driver panel 1 by metal sputtering or electron beam evaporation, first evaporating a 10 nm thick Cr adhesion layer (evaporation rate 1 nm / s), then evaporating a 200 nm thick Pt layer and a 200 nm thick Au layer (evaporation rate 2 nm / s);

[0072] S2, preparation of transparent conductive film layer 8: forming a 100 nm thick ITO transparent conductive film layer 8 on the epitaxial layer 3 by electron beam evaporation or magnetron sputtering at a rate of 1.5 nm / s. Then, annealing the transparent conductive film layer 8 at an annealing temperature of 550° C. for 5 minutes in a nitrogen atmosphere at a gas flow rate of 5 sccm to optimize the crystal quality and conductive properties of the transparent conductive film layer 8;

[0073] S3, Preparation of Metal Layer of Epitaxial Layer 3: Forming a second bonding metal layer 31 on the transparent conductive film layer 8 by electron beam evaporation, with a 5 nm Ti layer, a 20 nm Pt layer, and a 200 nm Au layer being deposited at a rate of 1 nm / s to provide a good metal interface for the subsequent bonding process;

[0074] S4, eutectic bonding and substrate processing: The silicon-based CMOS driver panel 1 and the epitaxial layer 3 are eutectic bonded using a metal bonding machine at a bonding temperature of 300°C, a pressure of 50 kN, and a duration of 15 minutes. For sapphire-based gallium nitride epitaxy, after bonding, the sapphire substrate of the epitaxial layer 3 is removed by laser stripping. The laser has a wavelength of 248 nm, a frequency of 1000 Hz, a stage temperature of 30°C, a periodic spacing of 15 μm, and is stripped from the outside to the inside in an annular manner. After stripping, the epitaxial layer is thinned to a thickness of 1.2 μm by chemical grinding.

[0075] S5, LED unit 4 formation: a 500nm thick silicon oxide film is deposited on the surface of the epitaxial layer 3 by chemical vapor deposition (CVD), and the reaction gas is and , the deposition power is 300W, the deposition temperature is 300℃, 1.5μm positive photoresist is spin-coated on the silicon oxide film layer, and the mask pattern is transferred to the photoresist after exposure and development by a stepper lithography machine to obtain a truncated cone mask layer, and the pattern of the mask layer is transferred to the silicon oxide film layer and the epitaxial layer 3 by plasma chemical etching (ICP). The etching gas is and , the gas flow rate is 50 sccm, and after etching, a periodically arranged LED unit 4 is obtained;

[0076] S6, anode 5 independence: 2 μm positive photoresist is spin-coated on the surface of the LED unit 4. After exposure and development using a stepper, the mask pattern is transferred to the photoresist to obtain a truncated cone-shaped mask layer. The mask layer completely covers each LED unit 4. The area outside the mask layer is etched through by ion beam etching (IBE) at an etching angle of 10° and an etching voltage of 400 V to etch through the transparent conductive film layer 8 and the second bonding metal layer 31, thereby achieving the independence of the anode 5 of the LED unit 4.

[0077] S7, electron blocking layer 6 growth: growing a 400 nm silicon oxide film layer as the electron blocking layer 6 on the surface of the LED unit 4 by chemical vapor deposition, protecting the ITO conductive film layer 8 and the bonding metal layer 2 exposed after IBE etching, and passivating the surface of the LED unit 4;

[0078] S8, optical extraction cavity 7 is formed: 2μm negative photoresist is spin-coated on the surface of the LED unit 4, and the mask pattern is transferred to the photoresist after exposure and development by a stepper lithography machine. Metal germanium, tin or indium is evaporated on the surface by electron beam evaporation with a thickness of 50nm. The metal outside the side wall of the LED unit 4 is removed by acetone ultrasonic stripping. The metal is annealed and reflowed into metal balls in a rapid annealing furnace at an annealing temperature of 400℃. The metal is etched by plasma chemical etching (ICP) with a gas of 20sccm. and 30 sccm , the upper plate power is 400W, the lower plate power is 50W, and the morphology of the metal ball is transferred to the surface of the silicon oxide film layer on the side wall to form an optical extraction cavity 7;

[0079] S9, cathode 9 is connected: 2 μm positive photoresist is spin-coated on the surface of the LED unit 4, and a hole is formed above the LED unit 4 by exposure and development. The size of the hole is smaller than or equal to the upper surface of the LED unit 4, and the hole is etched by plasma chemical (ICP) with a gas of 80 sccm. The power of the upper plate is 300W, and the power of the lower plate is 80W. The silicon oxide film layer in the hole is removed, and a 300nm ITO transparent conductive film layer is deposited by electron beam evaporation. The cathode 9 of each LED unit 4 is connected in common to realize the electrical connection of the device.

[0080] Example 4

[0081] A method for preparing a micro-display structure for improving the light efficiency of Micro LEDs comprises the following steps:

[0082] S1, preparation of the first bonding metal layer 21: forming the first bonding metal layer 21 on the surface of the silicon-based CMOS driver panel 1 by metal sputtering or electron beam evaporation, first evaporating a 10 nm thick Cr adhesion layer (evaporation rate 1 nm / s), then evaporating a 200 nm thick Pt layer and a 200 nm thick Au layer (evaporation rate 2 nm / s);

[0083] S2, preparation of transparent conductive film layer 8: forming a 100 nm thick ITO transparent conductive film layer 8 on the epitaxial layer 3 by electron beam evaporation or magnetron sputtering at a rate of 1.5 nm / s. Then, annealing the transparent conductive film layer 8 at an annealing temperature of 550° C. for 5 minutes in a nitrogen atmosphere at a gas flow rate of 5 sccm to optimize the crystal quality and conductive properties of the transparent conductive film layer 8;

[0084] S3, Preparation of Metal Layer of Epitaxial Layer 3: Forming a second bonding metal layer 31 on the transparent conductive film layer 8 by electron beam evaporation, with a 5 nm Ti layer, a 20 nm Pt layer, and a 200 nm Au layer being deposited at a rate of 1 nm / s to provide a good metal interface for the subsequent bonding process;

[0085] S4, eutectic bonding and substrate processing: the silicon-based CMOS driving panel 1 and the epitaxial layer 3 are eutectic bonded by a metal bonding machine, with a bonding temperature of 300°C, a pressure of 50KN, and a time of 15 minutes; for silicon-based gallium nitride epitaxy, after bonding, the silicon substrate of the epitaxial layer 3 is removed by wafer thinning, wet processing or plasma chemical etching (ICP), the grinding wheel for wafer thinning has a mesh size of 1000 and a grinding wheel speed of 1000rpm, the silicon substrate is thinned to a thickness of 100μm, and the solution for wet removal of the silicon substrate is hydrofluoric acid (HF), hydrogen peroxide ( ), HF: The ratio is 1:1;

[0086] S5, LED unit 4 formation: a 500nm thick silicon oxide film is deposited on the surface of the epitaxial layer 3 by chemical vapor deposition (CVD), and the reaction gas is and , the deposition power is 300W, the deposition temperature is 300℃, 1.5μm positive photoresist is spin-coated on the silicon oxide film layer, and the mask pattern is transferred to the photoresist after exposure and development by a stepper lithography machine to obtain a truncated cone mask layer, and the pattern of the mask layer is transferred to the silicon oxide film layer and the epitaxial layer 3 by plasma chemical etching (ICP). The etching gas is and , the gas flow rate is 50 sccm, and after etching, a periodically arranged LED unit 4 is obtained;

[0087] S6, anode 5 independence: 2 μm positive photoresist is spin-coated on the surface of the LED unit 4. After exposure and development using a stepper, the mask pattern is transferred to the photoresist to obtain a truncated cone-shaped mask layer. The mask layer completely covers each LED unit 4. The area outside the mask layer is etched through by ion beam etching (IBE) at an etching angle of 10° and an etching voltage of 400 V to etch through the transparent conductive film layer 8 and the second bonding metal layer 31, thereby achieving the independence of the anode 5 of the LED unit 4.

[0088] S7, electron blocking layer 6 growth: growing a 400 nm silicon oxide film layer as the electron blocking layer 6 on the surface of the LED unit 4 by chemical vapor deposition, protecting the ITO conductive film layer 8 and the bonding metal layer 2 exposed after IBE etching, and passivating the surface of the LED unit 4;

[0089] S8, optical extraction cavity 7 is formed: 2μm negative photoresist is spin-coated on the surface of the LED unit 4, and the mask pattern is transferred to the photoresist after exposure and development by a stepper lithography machine. Metal germanium, tin or indium is evaporated on the surface by electron beam evaporation with a thickness of 50nm. The metal outside the side wall of the LED unit 4 is removed by acetone ultrasonic stripping. The metal is annealed and reflowed into metal balls in a rapid annealing furnace at an annealing temperature of 400℃. The metal is etched by plasma chemical etching (ICP) with a gas of 20sccm. and 30 sccm , the upper plate power is 400W, the lower plate power is 50W, and the morphology of the metal ball is transferred to the surface of the silicon oxide film layer on the side wall to form an optical extraction cavity 7;

[0090] S9, cathode 9 is connected: 2 μm positive photoresist is spin-coated on the surface of the LED unit 4, and a hole is formed above the LED unit 4 by exposure and development. The size of the hole is smaller than or equal to the upper surface of the LED unit 4, and the hole is etched by plasma chemical (ICP) with a gas of 80 sccm. The power of the upper plate is 300W, and the power of the lower plate is 80W. The silicon oxide film layer in the hole is removed, and a 300nm ITO transparent conductive film layer is deposited by electron beam evaporation. The cathode 9 of each LED unit 4 is connected in common to realize the electrical connection of the device.

[0091] Example 5

[0092] A method for preparing a micro-display structure for improving the light efficiency of Micro LEDs comprises the following steps:

[0093] S1, preparation of the first bonding metal layer 21: forming the first bonding metal layer 21 on the surface of the silicon-based CMOS driver panel 1 by metal sputtering or electron beam evaporation, first evaporating a 10 nm thick Cr adhesion layer (evaporation rate 1 nm / s), then evaporating a 200 nm thick Pt layer and a 200 nm thick Au layer (evaporation rate 2 nm / s);

[0094] S2, preparation of transparent conductive film layer 8: forming a 100 nm thick ITO transparent conductive film layer 8 on the epitaxial layer 3 by electron beam evaporation or magnetron sputtering at a rate of 1.5 nm / s. Then, annealing the transparent conductive film layer 8 at an annealing temperature of 550° C. for 5 minutes in a nitrogen atmosphere at a gas flow rate of 5 sccm to optimize the crystal quality and conductive properties of the transparent conductive film layer 8;

[0095] S3, Preparation of Metal Layer of Epitaxial Layer 3: Forming a second bonding metal layer 31 on the transparent conductive film layer 8 by electron beam evaporation, with a 5 nm Ti layer, a 20 nm Pt layer, and a 200 nm Au layer being deposited at a rate of 1 nm / s to provide a good metal interface for the subsequent bonding process;

[0096] S4, eutectic bonding and substrate processing: the silicon-based CMOS driving panel 1 and the epitaxial layer 3 are eutectic bonded by a metal bonding machine, with a bonding temperature of 300°C, a pressure of 50KN, and a time of 15 minutes; for gallium arsenide-based aluminum gallium indium phosphide epitaxy, the gallium arsenide substrate of the aluminum gallium indium phosphide epitaxy is removed by wet method after bonding, and the solution for wet removal of the gallium arsenide substrate is ammonia water ( ), hydrogen peroxide ( ), : The ratio is 1:5;

[0097] S5, LED unit 4 formation: a 500nm thick silicon oxide film is deposited on the surface of the epitaxial layer 3 by chemical vapor deposition (CVD), and the reaction gas is and , the deposition power is 300W, the deposition temperature is 300℃, 1.5μm positive photoresist is spin-coated on the silicon oxide film layer, and the mask pattern is transferred to the photoresist after exposure and development by a stepper lithography machine to obtain a truncated cone mask layer, and the pattern of the mask layer is transferred to the silicon oxide film layer and the epitaxial layer 3 by plasma chemical etching (ICP). The etching gas is and , the gas flow rate is 50 sccm, and after etching, a periodically arranged LED unit 4 is obtained;

[0098] S6, anode 5 independence: 2 μm positive photoresist is spin-coated on the surface of the LED unit 4. After exposure and development using a stepper, the mask pattern is transferred to the photoresist to obtain a truncated cone-shaped mask layer. The mask layer completely covers each LED unit 4. The area outside the mask layer is etched through by ion beam etching (IBE) at an etching angle of 10° and an etching voltage of 400 V to etch through the transparent conductive film layer 8 and the second bonding metal layer 31, thereby achieving the independence of the anode 5 of the LED unit 4.

[0099] S7, electron blocking layer 6 growth: growing a 400 nm silicon oxide film layer as the electron blocking layer 6 on the surface of the LED unit 4 by chemical vapor deposition, protecting the ITO conductive film layer 8 and the bonding metal layer 2 exposed after IBE etching, and passivating the surface of the LED unit 4;

[0100] S8, optical extraction cavity 7 is formed: 2μm negative photoresist is spin-coated on the surface of the LED unit 4, and the mask pattern is transferred to the photoresist after exposure and development by a stepper lithography machine. Metal germanium, tin or indium is evaporated on the surface by electron beam evaporation with a thickness of 50nm. The metal outside the side wall of the LED unit 4 is removed by acetone ultrasonic stripping. The metal is annealed and reflowed into metal balls in a rapid annealing furnace at an annealing temperature of 400℃. The metal is etched by plasma chemical etching (ICP) with a gas of 20sccm. and 30 sccm , the upper plate power is 400W, the lower plate power is 50W, and the morphology of the metal ball is transferred to the surface of the silicon oxide film layer on the side wall to form an optical extraction cavity 7;

[0101] S9, cathode 9 is connected: 2 μm positive photoresist is spin-coated on the surface of the LED unit 4, and a hole is formed above the LED unit 4 by exposure and development. The size of the hole is smaller than or equal to the upper surface of the LED unit 4, and the hole is etched by plasma chemical (ICP) with a gas of 80 sccm. The power of the upper plate is 300W, and the power of the lower plate is 80W. The silicon oxide film layer in the hole is removed, and a 300nm ITO transparent conductive film layer is deposited by electron beam evaporation. The cathode 9 of each LED unit 4 is connected in common to realize the electrical connection of the device.

[0102] The present application provides a micro-display structure and preparation method for improving the luminous efficiency of Micro LEDs, which significantly improves the luminous efficiency. The sidewall optical extraction cavity 7 structure effectively increases the amount of light output from the sidewall of the LED, significantly improves the light power compared to the traditional structure, and greatly improves the luminous efficiency; the optical extraction cavity 7 cooperates with the common cathode structure to narrow the divergence angle of the LED, and greatly improves the brightness in the vertical direction, meeting the high brightness requirements of high-end applications such as near-eye displays; the preparation process is based on existing semiconductor manufacturing technology, is highly compatible with the silicon-based CMOS driver panel 1 circuit, is suitable for large-scale mass production, and has low preparation cost; the multi-layer metal bonding and dielectric protection structure ensure the electrical reliability and structural stability of the device, greatly enhancing the device life.

[0103] Finally, it should be noted that the above are only preferred embodiments of the present invention and are not intended to limit the present invention. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art can still modify the technical solutions described in the aforementioned embodiments or make equivalent replacements for some of the technical features therein. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A micro-display structure for improving the light efficiency of Micro LEDs, characterized in that: include: A silicon-based CMOS driving panel, wherein a bonding metal layer is provided on the surface of the silicon-based CMOS driving panel; An LED unit formed by an epitaxial layer, wherein the LED unit is connected to the silicon-based CMOS driver panel via a bonding metal layer, and the anode of the LED unit is independently provided; An electron blocking layer wrapped around the side wall of the LED unit, wherein the surface of the electron blocking layer is etched to form an optical extraction cavity; A conductive film layer covers the top of the LED unit, and the conductive film layer connects the cathodes of the LED units in common.

2. The micro-display structure for improving Micro LED light efficiency according to claim 1, wherein: The bonding metal layer on the silicon-based CMOS driving panel consists of a Cr or Ti adhesion layer, a Pt layer and an Au layer, with thicknesses of 5-50 nm for the Cr or Ti adhesion layer, 200 nm for the Pt layer and 200 nm for the Au layer.

3. The micro-display structure for improving Micro LED light efficiency according to claim 1, wherein: The optical extraction cavity is made of a 300-500nm thick silicon oxide layer, which is formed by etching an electron blocking layer through a metal particle mask formed by reflowing metal germanium, tin or indium.

4. The micro-display structure for improving Micro LED light efficiency according to claim 1, wherein: The conductive film layer is a 300nm ITO or ZnO transparent conductive film layer.

5. A method for preparing a micro-display structure for improving the light efficiency of Micro LEDs, characterized in that: The steps include: S1, preparation of a first bonding metal layer: forming a first bonding metal layer on the surface of a silicon-based CMOS driver panel by metal sputtering or electron beam evaporation, wherein the first bonding metal layer includes a Cr or Ti adhesion layer with a thickness of 5-50 nm, a Pt layer with a thickness of 200 nm, and an Au layer with a thickness of 200 nm, and the electron beam evaporation rate is 1-2 nm / s; S2, preparing a transparent conductive film layer: forming a transparent conductive film layer with a thickness of 50-200 nm on the epitaxial layer by electron beam evaporation or magnetron sputtering, the evaporation rate of the transparent conductive film layer being 1-2 nm / s, and then annealing the transparent conductive film layer; S3, preparing an epitaxial metal layer: forming a second bonding metal layer on the transparent conductive film layer by electron beam evaporation, wherein the second bonding metal layer includes a 5 nm thick Cr or Ti layer, a 20 nm thick Pt layer, and a 200 nm thick Au layer, and the electron beam evaporation rate is 0.5-2 nm / s; S4, eutectic bonding and substrate processing: eutectic bonding the silicon-based CMOS driving panel and the epitaxial layer by a metal bonding machine, wherein the first bonding metal layer and the second bonding metal layer are eutectic bonded to form a bonding metal layer, and after bonding, the substrate of the epitaxial layer is removed; S5, forming LED units: depositing a 300-1000 nm thick silicon oxide film layer on the surface of the epitaxial layer by chemical vapor deposition, spin-coating a positive photoresist on the silicon oxide film layer, transferring a mask pattern to the photoresist after exposure and development using a stepper lithography machine to obtain a truncated cone-shaped mask layer, transferring the pattern of the mask layer to the silicon oxide film layer and the epitaxial layer by plasma chemical etching, and obtaining periodically arranged LED units after etching; S6, anode independence: spin-coating a positive photoresist on the surface of the LED unit, transferring the mask pattern to the photoresist after exposure and development using a stepper, to obtain a truncated cone-shaped mask layer that completely covers each of the LED units, etching the area outside the mask layer using an ion beam etching process at an etching angle of 0°-15° and an etching voltage of 300-500V to etch through the transparent conductive film layer and the bonding metal layer, thereby achieving anode independence of the LED unit; S7, electron blocking layer growth: growing a 300-500 nm silicon oxide film layer as an electron blocking layer on the surface of the LED unit by chemical vapor deposition; S8, forming an optical extraction cavity: spin-coating a negative photoresist on the surface of the LED unit, transferring the mask pattern to the photoresist after exposure and development using a stepper, evaporating metal germanium, tin or indium on the surface by electron beam evaporation to a thickness of 20-80 nm, removing the metal outside the side wall of the LED unit by acetone ultrasonic stripping, annealing and reflowing the metal into metal balls in a rapid annealing furnace at an annealing temperature of 350-450° C., and transferring the morphology of the metal balls to the surface of the silicon oxide film layer on the side wall by plasma chemical etching to form an optical extraction cavity; S9, cathode common connection: spin-coat positive photoresist on the surface of the LED unit, form a hole above the LED unit through exposure and development, the size of the hole is smaller than or equal to the upper surface of the LED unit, remove the silicon oxide film layer in the hole by plasma chemical etching, and connect the cathode of each LED unit in common by electron beam evaporation of a 300nm transparent conductive film layer.

6. The method for preparing a micro-display structure for improving Micro LED light efficiency according to claim 5, wherein: In step S2, the annealing temperature is 500-600°C, the annealing time is 3-10 minutes, the annealing atmosphere is nitrogen or oxygen, and the gas flow rate is 3-10 sccm.

7. The method for preparing a micro-display structure for improving Micro LED light efficiency according to claim 5, wherein: In step S4, the bonding temperature is 260-350° C., the pressure is 25-80 KN, and the bonding time is 10-30 min.

8. The method for preparing a micro-display structure for improving Micro LED light efficiency according to claim 5, wherein: In step S5, the reaction gas for chemical vapor deposition is and , the deposition power is 100-500W, the deposition temperature is 250-350℃; the gas for etching the epitaxial layer is and , the gas flow rate is 20-100sccm.

9. The method for preparing a micro-display structure for improving Micro LED light efficiency according to claim 5, wherein: In step S8, the gas for plasma chemical etching is 20 sccm. and 30 sccm , the upper plate power is 400W and the lower plate power is 50W.

10. The method for preparing a micro display structure for improving Micro LED light efficiency according to claim 5, wherein: In step S9, the gas for plasma chemical etching is 80 sccm. , the upper plate power is 200-500W, and the lower plate power is 50-100W.

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