A resistive switching memory and its fabrication method

Abstract

This invention discloses a resistive switching memory (RSM) and its fabrication method. The RSM includes: a substrate layer; a first electrode layer located on one side of the substrate layer; a resistive switching layer located on the side of the first electrode layer away from the substrate layer; and a second electrode layer located on the side of the resistive switching layer away from the first electrode layer. The lattice mismatch f1 between the first electrode layer and the resistive switching layer satisfies 0% ≤ f1 < 7%, and the lattice mismatch f2 between the second electrode layer and the resistive switching layer satisfies 0% ≤ f2 < 7%. By employing a first electrode and a second electrode with low lattice mismatch with the resistive switching layer, this invention can alleviate lattice mismatch stress, reduce interface stress accumulation, and improve the stability and reliability of the RSM.

Description

Technical Field

[0001] This invention relates to the field of memory technology, and in particular to a resistive switching memory and its fabrication method. Background Technology

[0002] With the rapid development of information technology, traditional storage technologies are gradually facing bottlenecks such as physical size approaching the quantum limit, soaring power consumption, and the "memory wall." Against this backdrop, Resistive Random-Access Memory (RRAM), with its high-speed read / write, ultra-low power consumption, non-volatile storage, and potential for high-density three-dimensional integration, is considered a revolutionary next-generation core storage technology and exhibits unique hardware adaptability in the field of neuromorphic computing. The core structure of RRAM is a metal-insulator-metal (MIM) sandwich structure, whose characteristics are determined by material selection and microscopic physical mechanisms. This structure consists of a top electrode (TE), a middle resistive switching layer (insulator), and a bottom electrode (BE). The middle resistive switching layer is the functional core of the RRAM and is typically composed of transition metal oxides or chalcogenides. The defect characteristics of these materials, such as oxygen vacancies or interstitial metal atoms, dynamically change under electric field control, thereby controlling the formation and breakage of conductive channels.

[0003] Innovation in resistive switching layer materials has become a key breakthrough for optimizing the performance of resistive switching memory (RSM). Aluminum nitride (Anitrile Nitride), as a resistive switching layer material for memristors, possesses numerous significant advantages. Its excellent chemical and thermal stability ensures the reliability of RSM under various environments. Its superior insulation properties enable the effective formation of the resistive switching layer, facilitating the transition between high-resistivity and low-resistivity states. Furthermore, Anitrile Nitride exhibits good interfacial compatibility with various electrode materials, enabling the formation of stable ohmic or Schottky contacts, which is beneficial for device integration and performance optimization.

[0004] Compared to traditional resistive switching memories (RSMs), RSMs with ultrathin resistive switching layers can generate a stronger electric field at the same voltage, thus significantly reducing the required operating voltage. The shortened ion migration paths in the ultrathin resistive switching layer reduce the migration time of oxygen vacancies or metal ions, resulting in a substantial increase in switching speed and higher integration density and miniaturization potential.

[0005] Aluminum nitride-based resistive switching memory (RSM) faces multiple technical challenges in its ultra-thinning process, primarily stemming from the conflict between its material properties and process compatibility. The high lattice mismatch between aluminum nitride and commonly used electrode materials (such as Pt and Ag) leads to interfacial stress accumulation, affecting the structural integrity of the ultra-thin resistive switching layer and consequently impacting the stability and reliability of the RSM. Summary of the Invention

[0006] This invention provides a resistive switching memory and its fabrication method to solve the problem that the high lattice mismatch between the resistive switching layer and the electrode layer in existing resistive switching memories leads to the accumulation of interfacial stress, which in turn affects the stability and reliability of the resistive switching memory.

[0007] In a first aspect, embodiments of the present invention provide a resistive random access memory, comprising:

[0008] Substrate layer;

[0009] The first electrode layer is located on one side of the substrate layer;

[0010] A resistive switching layer is located on the side of the first electrode layer away from the substrate layer;

[0011] The second electrode layer is located on the side of the resistive switching layer away from the first electrode layer;

[0012] Wherein, the lattice mismatch f1 between the first electrode layer and the resistive switching layer satisfies 0%≤f1<7%, and the lattice mismatch f2 between the second electrode layer and the resistive switching layer satisfies 0%≤f2<7%.

[0013] Optionally, the percentage difference P1 between the thermal expansion coefficient of the first electrode layer and the thermal expansion coefficient of the resistive switching layer satisfies 0% ≤ P1 < 10%;

[0014] The percentage difference P2 between the thermal expansion coefficient of the second electrode layer and the thermal expansion coefficient of the resistive switching layer satisfies 0% ≤ P2 < 10%.

[0015] Optionally, the resistive switching layer may be made of aluminum nitride.

[0016] The material of the first electrode layer includes tungsten or a tungsten-rhenium alloy;

[0017] The material of the second electrode layer includes tungsten or a tungsten-rhenium alloy.

[0018] Optionally, the rhenium content W1 in the tungsten-rhenium alloy satisfies 3% ≤ W1 ≤ 12%.

[0019] Optionally, it may also include a reinforcement layer located between the second electrode layer and the resistive switching layer;

[0020] The reinforcing layer is made of aluminum oxynitride.

[0021] Optionally, the thickness M1 of the reinforcing layer satisfies 0nm < M1 < 5nm.

[0022] Optionally, the thickness M2 of the resistive switching layer satisfies 5nm ≤ M2 ≤ 15nm;

[0023] The thickness M3 of the first electrode layer satisfies 20nm ≤ M3 < 50nm;

[0024] The thickness M4 of the second electrode layer satisfies 20nm ≤ M4 < 50nm.

[0025] Secondly, embodiments of the present invention provide a method for fabricating a resistive switching memory (RSM), used to fabricate the RSM as described in the first aspect, the fabrication method comprising:

[0026] Preparation of substrate layer;

[0027] A first electrode layer is prepared on one side of the substrate layer;

[0028] A resistive switching layer is fabricated on the side of the first electrode layer away from the substrate layer, wherein the lattice mismatch f1 between the first electrode layer and the resistive switching layer satisfies 0% ≤ f1 < 7%;

[0029] A second electrode layer is prepared on the side of the resistive switching layer away from the first electrode layer, wherein the lattice mismatch f2 between the second electrode layer and the resistive switching layer satisfies 0% ≤ f2 < 7%.

[0030] Optionally, a resistive switching layer is fabricated on the side of the first electrode layer away from the substrate layer, including:

[0031] The substrate layer and the first electrode layer are placed in a vacuum cavity;

[0032] At a preset temperature, the reactive precursor and reactant precursor are repeatedly introduced into the vacuum cavity until a preset number of times are reached, so as to form the resistive switching layer on the side of the first electrode layer away from the substrate layer.

[0033] Optionally, after fabricating a resistive switching layer on the side of the first electrode layer away from the substrate layer, the fabrication method further includes:

[0034] A reinforcement layer is prepared on the side of the resistive switching layer away from the first electrode layer;

[0035] A second electrode layer is fabricated on the side of the resistive switching layer away from the first electrode layer, including:

[0036] A second electrode layer is prepared on the side of the reinforcement layer away from the resistive switching layer.

[0037] The technical solution of this invention sets the lattice mismatch degree f1 of the first electrode layer and the resistive switching layer to satisfy 0%≤f1<7%, and the lattice mismatch degree f2 of the second electrode layer and the resistive switching layer to satisfy 0%≤f2<7%. That is, by using the first electrode layer and the second electrode layer with low lattice mismatch degree with the resistive switching layer, the lattice mismatch stress can be alleviated, the interface stress accumulation can be reduced, and the stability and reliability of the resistive switching memory can be improved.

[0038] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0039] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0040] Figure 1 This is a schematic diagram of the structure of a resistive random access memory (RRAM) provided in an embodiment of the present invention;

[0041] Figure 2 A thermal expansion coefficient curve of aluminum nitride is provided for an embodiment of the present invention;

[0042] Figure 3 A thermal expansion coefficient curve of a tungsten-rhenium alloy provided in an embodiment of the present invention;

[0043] Figure 4 This is a schematic diagram of another resistive random access memory provided in an embodiment of the present invention;

[0044] Figure 5 A cross-sectional structural diagram of a resistive random access memory (RRAM) provided in an embodiment of the present invention;

[0045] Figure 6 A flowchart illustrating a method for fabricating a resistive switching memory (RSM) according to an embodiment of the present invention;

[0046] Figure 7 A flowchart illustrating another method for fabricating a resistive switching memory provided in an embodiment of the present invention;

[0047] Figure 8 A flowchart illustrating another method for fabricating a resistive switching memory (RSM) according to an embodiment of the present invention. Detailed Implementation

[0048] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0049] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or device that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or devices. The terms "upper," "lower," "left," "right," etc., indicate orientation or positional relationships based on the orientation or positional relationships shown in the accompanying drawings and are only used to describe the relative positional relationships between components or constituent parts, and do not specifically limit the specific installation orientation of each component or constituent part.

[0050] Figure 1 This is a schematic diagram of a resistive random access memory (RRAM) provided in an embodiment of the present invention. (Refer to...) Figure 1 The resistive switching memory 100 in this embodiment of the invention includes: a substrate layer 10, a first electrode layer 20, a resistive switching layer 30, and a second electrode layer 40. The first electrode layer 20 is located on one side of the substrate layer 10. The resistive switching layer 30 is located on the side of the first electrode layer 20 away from the substrate layer 10. The second electrode layer 40 is located on the side of the resistive switching layer 30 away from the first electrode layer 20. The lattice mismatch f1 between the first electrode layer 20 and the resistive switching layer 30 satisfies 0% ≤ f1 < 7%, and the lattice mismatch f2 between the second electrode layer 40 and the resistive switching layer 30 satisfies 0% ≤ f2 < 7%.

[0051] For example, the substrate 10 is used to carry the first electrode layer 20, the resistive switching layer 30 and the second electrode layer 40. Its material must be an insulating material, such as silicon, silicon carbide, sapphire or silicon nitride.

[0052] Both the first electrode layer 20 and the second electrode layer 40 are electrically connected to an external circuit, allowing a positive or reverse voltage to be applied to the resistive switching layer 30. Under the influence of the positive or reverse voltage, the resistive switching layer 30 achieves reversible switching between a high-resistivity state (HRS) and a low-resistivity state (LRS) through ion migration or defect modulation, thereby realizing data storage. Specifically, when the first electrode layer 20 and the second electrode layer 40 apply a positive voltage to the resistive switching layer 30, for example, when the second electrode is connected to a positive voltage and the first electrode is grounded, electrode ions or oxygen vacancies form conductive filaments in the resistive switching layer 30, and the device switches from a high-resistivity state to a low-resistivity state. When the first electrode layer 20 and the second electrode layer 40 apply a reverse voltage to the resistive switching layer 30, for example, when the second electrode is grounded and the first electrode is connected to a positive voltage, the conductive filaments melt or ions migrate back, and the device returns to the high-resistivity state. The high-resistivity state represents logic "0", and the low-resistivity state represents logic "1", achieving data storage through resistance states.

[0053] It should be noted that lattice mismatch refers to the degree of difference in lattice constants between two materials at the interface, usually expressed as a percentage. The lattice mismatch f1 between the first electrode layer 20 and the resistive switching layer 30 satisfies the following correspondence:

[0054] Where a1 represents the lattice constant of the first electrode layer 20, and a0 represents the lattice constant of the resistive switching layer 30. A high lattice mismatch between the first electrode layer 20 and the resistive switching layer 30 can lead to voids and cracks at the interface, affecting the uniformity of the conductive filament formation in the resistive switching layer 30. By setting the lattice mismatch f1 between the first electrode layer 20 and the resistive switching layer 30 to satisfy 0% ≤ f1 < 7%, i.e., using a first electrode layer 20 with a low lattice mismatch with the resistive switching layer 30, lattice mismatch stress can be alleviated, charge trapping and lattice distortion can be reduced, and mechanical stability can be improved.

[0055] The lattice mismatch f2 between the second electrode layer 40 and the resistive switching layer 30 satisfies the following correspondence:

[0056] Where a2 represents the lattice constant of the second electrode layer 40. A high lattice mismatch between the second electrode layer 40 and the resistive switching layer 30 can lead to voids and cracks at the interface between them, affecting the uniformity of the conductive filament formation in the resistive switching layer 30. By setting the lattice mismatch f2 between the second electrode layer 40 and the resistive switching layer 30 to satisfy 0% ≤ f2 < 7%, i.e., using a second electrode layer 40 with a low lattice mismatch with the resistive switching layer 30, lattice mismatch stress can be alleviated, charge traps and lattice distortion can be reduced, and mechanical stability can be improved.

[0057] The present invention sets the lattice mismatch f1 between the first electrode layer 20 and the resistive switching layer 30 to satisfy 0%≤f1<7%, and the lattice mismatch f2 between the second electrode layer 40 and the resistive switching layer 30 to satisfy 0%≤f2<7%. That is, by using the first electrode layer 20 and the second electrode layer 40 with low lattice mismatch with the resistive switching layer 30, the lattice mismatch stress can be alleviated, the interface stress accumulation can be reduced, and the stability and reliability of the resistive switching memory 100 can be improved.

[0058] By employing an electrode layer with low lattice mismatch with the resistive switching layer 30, interface scattering and charge trapping can be reduced, improving charge transport efficiency; chemical reactions can be suppressed, enhancing interface stability; lattice distortion can be reduced, optimizing defect control; and uniform growth can be promoted, improving material growth quality.

[0059] Based on the above embodiments, the percentage difference P1 between the thermal expansion coefficients of the first electrode layer 20 and the resistive switching layer 30 satisfies 0% ≤ P1 < 10%. The percentage difference P2 between the thermal expansion coefficients of the second electrode layer 40 and the resistive switching layer 30 satisfies 0% ≤ P2 < 10%.

[0060] Understandably, in the existing technology, although the high thermal conductivity of aluminum nitride resistive switching layers is beneficial for heat dissipation, the local temperature gradient during the ultrathinning process can easily lead to the accumulation of thermal stress, which in turn affects the structural stability of the resistive switching memory 100 in a high-temperature environment.

[0061] In this embodiment of the invention, by setting the percentage difference P1 between the thermal expansion coefficients of the first electrode layer 20 and the resistive switching layer 30 to be 0% ≤ P1 < 10%, that is, setting the thermal expansion coefficients of the first electrode layer 20 and the resistive switching layer 30 to be similar, the interfacial stress caused by temperature changes can be reduced, which is beneficial to improving the structural stability of the resistive switching memory 100 in high-temperature environments. Similarly, by setting the percentage difference P2 between the thermal expansion coefficients of the second electrode layer 40 and the resistive switching layer 30 to be 0% ≤ P2 < 10%, that is, setting the thermal expansion coefficients of the second electrode layer 40 and the resistive switching layer 30 to be similar, the interfacial stress caused by temperature changes can be reduced, which is beneficial to improving the structural stability of the resistive switching memory 100 in high-temperature environments.

[0062] In one possible implementation, the resistive switching layer 30 is made of aluminum nitride. The first electrode layer 20 is made of tungsten or a tungsten-rhenium alloy. The second electrode layer 40 is made of tungsten or a tungsten-rhenium alloy.

[0063] For example, tungsten and aluminum nitride have similar coefficients of thermal expansion. This close proximity reduces interfacial stress caused by temperature changes, thereby improving the structural stability of the resistive switching memory 100 in high-temperature environments. It is understood that the coefficient of thermal expansion of aluminum nitride, the material of the resistive switching layer 30, increases steadily with increasing temperature. By adding rhenium to tungsten, the coefficient of thermal expansion of tungsten can be adjusted, reducing the difference between the coefficients of thermal expansion of the tungsten-rhenium alloy and aluminum nitride, thereby further reducing interfacial stress caused by temperature changes and improving the structural stability of the resistive switching memory 100 in high-temperature environments.

[0064] For example, when the first electrode layer 20 and the second electrode layer 40 are made of pure tungsten, their lattice mismatch with the resistive switching layer 30 made of aluminum nitride is 1.7%, and the difference in their coefficients of thermal expansion is 23.3%. Specifically, the lattice constant of tungsten (W) is 0.3165 nm, and the lattice constant of aluminum nitride (AlN) is 0.3112 nm. According to the formula for calculating the lattice mismatch, the lattice mismatch between the electrode layers (first electrode layer 20 and second electrode layer 40) and the resistive switching layer 30 is approximately 1.7%. The coefficient of thermal expansion of tungsten at room temperature is... The coefficient of thermal expansion of aluminum nitride is The difference in the coefficient of thermal expansion between the electrode layer (first electrode layer 20 and second electrode layer 40) and the resistive switching layer 30 is 23.3%.

[0065] It should be noted that the material of the resistive switching layer 30 in the embodiments of the present invention can be replaced with gallium nitride or boron nitride, and the materials of the first electrode layer 20 and the second electrode layer 40 can be replaced with materials that have a low lattice mismatch with the material of the resistive switching layer 30, such as tungsten disulfide.

[0066] Specifically, in the tungsten-rhenium alloy of the present invention, the rhenium content W1 satisfies 3%≤W1≤12%.

[0067] It is understandable that the higher the rhenium content in the tungsten-rhenium alloy, the greater the coefficient of thermal expansion of the first electrode layer 20 or the second electrode layer 40 using the tungsten-rhenium alloy, and the closer it is to the coefficient of thermal expansion of the resistive switching layer 30 at high temperature. In order to ensure that the percentage difference P1 between the coefficient of thermal expansion of the first electrode layer 20 and the coefficient of thermal expansion of the resistive switching layer 30 satisfies 0%≤P1<10%, and the percentage difference P2 between the coefficient of thermal expansion of the second electrode layer 40 and the coefficient of thermal expansion of the resistive switching layer 30 satisfies 0%≤P2<10%, the rhenium content W1 in the tungsten-rhenium alloy needs to be set to satisfy W1≥3%.

[0068] It is understandable that the higher the rhenium content in the tungsten-rhenium alloy, the larger the lattice constant of the tungsten-rhenium alloy, and the higher the lattice mismatch between the first electrode layer 20 or the second electrode layer 40 and the resistive switching layer 30. In order to ensure that the lattice mismatch f1 between the first electrode layer 20 and the resistive switching layer 30 satisfies 0%≤f1<7% and the lattice mismatch f2 between the second electrode layer 40 and the resistive switching layer 30 satisfies 0%≤f2<7%, the rhenium content W1 in the tungsten-rhenium alloy needs to be set to satisfy W1≤12%.

[0069] For example, the tungsten-rhenium alloy is a solid solution, and its lattice constant increases linearly with the rhenium content, satisfying the following correspondence: aWRe≈0.3165+0.00032×x, where aWRe represents the lattice constant of the tungsten-rhenium alloy, x represents the rhenium content in the tungsten-rhenium alloy, the rhenium content x in the tungsten-rhenium alloy satisfies 3%≤x≤12%, and its lattice mismatch f with the resistive switching layer 30 (aluminum nitride AlN) satisfies: f≤2.9%. Specifically, when the rhenium content x is 3%, f=2.0%; when the rhenium content x is 12%, f=2.9%.

[0070] Figure 2 A thermal expansion coefficient curve of aluminum nitride is provided for an embodiment of the present invention, for reference. Figure 2 , Figure 3 A thermal expansion coefficient curve of a tungsten-rhenium alloy is provided as an embodiment of the present invention, for reference. Figure 2 and Figure 3 When growing aluminum nitride layers (resistive switching layer 30) using atomic layer deposition (ALD), the growth temperature is controlled between 300 and 400 degrees Celsius, corresponding to the coefficient of thermal expansion of aluminum nitride. to At this point, the corresponding coefficient of thermal expansion of the tungsten-rhenium alloy is [value missing] when the rhenium content is 3%-12%. to The optimal rhenium content can be controlled at 4-6%, at which point the coefficient of thermal expansion is... Compared to the slow change in the coefficient of thermal expansion of pure W alloy below 500 degrees Celsius, the addition of rhenium can reduce the difference in the coefficient of thermal expansion between the electrode layers (first electrode layer 20 and second electrode layer 40) and the resistive switching layer 30 (aluminum nitride AlN) electrode at high temperatures. Specifically, the original difference in the coefficient of thermal expansion of 42.8%-56.0% at high temperatures can be reduced to 30.6%, thus optimizing the lattice growth quality.

[0071] In summary, by setting the rhenium content W1 in the tungsten-rhenium alloy to satisfy 3%≤W1≤12%, not only can the thermal expansion coefficient of the first electrode layer 20 or the second electrode layer 40 using the tungsten-rhenium alloy be close to the thermal expansion coefficient of the resistive switching layer 30 at high temperatures, reducing the interfacial stress caused by temperature changes and improving the structural stability of the resistive switching memory 100 in high-temperature environments, but also the lattice mismatch between the first electrode layer 20 or the second electrode layer 40 using the tungsten-rhenium alloy and the resistive switching layer 30 can be kept within a low range, alleviating lattice mismatch stress and reducing interfacial stress accumulation, which is beneficial to improving the stability and reliability of the resistive switching memory 100.

[0072] Figure 4 This is a schematic diagram of another resistive random access memory provided in an embodiment of the present invention. Figure 5 This is a cross-sectional structural diagram of a resistive random access memory (RRAM) provided in an embodiment of the present invention. (Refer to...) Figure 4 and Figure 5 The resistive switching memory 100 in this embodiment of the invention further includes a reinforcement layer 50, which is located between the second electrode layer 40 and the resistive switching layer 30. The material of the reinforcement layer 50 includes aluminum oxynitride.

[0073] For example, an aluminum oxynitride layer can be formed by infiltrating oxygen ions into the surface of the aluminum nitride layer through plasma oxidation and high-temperature annealing, with an oxygen doping content of 5%-10%, i.e., the reinforcement layer 50. The aluminum oxynitride layer helps in the formation of conductive wires and the trapping of nitride traps in the resistive switching layer 30. Introducing an aluminum oxynitride reinforcement interface on the basis of the ultrathin aluminum nitride layer enables the resistive switching memory 100 in the embodiments of the present invention to have the advantages of low power consumption, high stability, and long lifespan.

[0074] For details, please refer to Figure 5 The thickness M1 of the reinforcing layer 50 satisfies 0nm < M1 < 5nm.

[0075] It is understandable that the greater the thickness of the aluminum oxynitride reinforcement layer 50, the higher the operating voltage (the voltage applied to the first electrode layer 20 and the second electrode layer 40) required to achieve the reversible switching between the high-resistivity state (HRS) and low-resistivity state (LRS) of the resistive switching layer 30. This is detrimental to reducing the power consumption of the resistive switching memory 100. Therefore, to ensure that the presence of the reinforcement layer 50 does not cause a significant increase in power consumption, the thickness M1 of the reinforcement layer 50 needs to be set to satisfy M1 < 5 nm. Simultaneously, to ensure the presence of the reinforcement layer 50 and improve the performance of the resistive switching memory 100, the thickness M1 of the reinforcement layer 50 needs to be set to satisfy M1 > 0 nm.

[0076] For example, the design of the ultrathin resistive switching layer 30 can stabilize the operating voltage below ±3V. The surface of the resistive switching layer 30 can be modified to aluminum oxynitride (i.e., reinforcement layer 50) by ion implantation, with an oxygen ion implantation depth of 4nm and a reinforcement layer thickness of 4nm.

[0077] Based on the above embodiments, continue to refer to Figure 5 The thickness M2 of the resistive switching layer 30 satisfies 5nm ≤ M2 ≤ 15nm. The thickness M3 of the first electrode layer 20 satisfies 20nm ≤ M3 < 50nm. The thickness M4 of the second electrode layer 40 satisfies 20nm ≤ M4 < 50nm.

[0078] It is understandable that if the thickness of the resistive switching layer 30 is too thin, it is prone to breakdown, while if it is too thick, a high voltage is required. By setting the thickness M2 of the resistive switching layer 30 to meet the condition of 5nm≤M2≤15nm, the high resistance ratio and low operating voltage can be balanced, achieving a balance between low power consumption, high durability and long holding time.

[0079] Choosing a thickness of 20nm ≤ M3 < 50nm for the first electrode layer 20 balances low resistance and interface stability. Understandably, a thinner second electrode layer 40 reduces the space occupied by the device in the thickness direction, which is beneficial for high-density integration. However, an excessively thin second electrode layer 40 may lead to increased resistance, especially causing current fluctuations during high-voltage or high-frequency operation. Choosing a thickness of 20nm ≤ M4 < 50nm balances low power consumption, high switching ratio, and high integration density.

[0080] This invention also provides a method for fabricating a resistive switching memory (RSM), used to fabricate the RSM shown in any of the above embodiments of this invention. Figure 4 A flowchart illustrating a method for fabricating a resistive random access memory (RRAM) according to an embodiment of the present invention is provided, with reference to... Figure 4 The method for fabricating resistive random access memory in this embodiment of the invention includes:

[0081] S110, Prepare the substrate layer.

[0082] For example, refer to Figure 1 The substrate layer 10 can be made of insulating materials such as silicon, silicon carbide, sapphire or silicon nitride.

[0083] S120. Prepare a first electrode layer on one side of the substrate layer.

[0084] For example, refer to Figure 1 The first electrode layer 20 can be deposited on the substrate layer 10 by magnetron sputtering. The material of the first electrode layer 20 can be tungsten or tungsten-rhenium alloy, and the thickness M3 of the first electrode layer 20 can satisfy 20nm≤M3<50nm.

[0085] S130. A resistive switching layer is prepared on the side of the first electrode layer away from the substrate layer, wherein the lattice mismatch f1 between the first electrode layer and the resistive switching layer satisfies 0%≤f1<7%.

[0086] For example, refer to Figure 1The resistive switching layer 30 can be prepared on the side of the first electrode layer 20 away from the substrate layer 10 by atomic vapor deposition (ALD). The material of the resistive switching layer 30 can be aluminum nitride, and the thickness M2 of the resistive switching layer 30 satisfies 5nm ≤ M2 ≤ 15nm. The lattice mismatch f1 between the first electrode layer 20, which is made of tungsten or a tungsten-rhenium alloy, and the resistive switching layer 30, which is made of aluminum nitride, satisfies 0% ≤ f1 < 7%.

[0087] S140. A second electrode layer is prepared on the side of the resistive switching layer away from the first electrode layer, wherein the lattice mismatch f2 between the second electrode layer and the resistive switching layer satisfies 0%≤f2<7%.

[0088] For example, refer to Figure 1 A second electrode layer 40 can be fabricated on the side of the resistive switching layer 30 away from the first electrode layer 20 using a magnetron sputtering process. The material of the second electrode layer 40 can be tungsten or a tungsten-rhenium alloy, and the thickness M4 of the second electrode layer 40 can satisfy 20nm ≤ M4 < 50nm. The lattice mismatch f2 between the second electrode layer 40, made of tungsten or a tungsten-rhenium alloy, and the resistive switching layer 30, made of aluminum nitride, satisfies 0% ≤ f2 < 7%.

[0089] The present invention sets the lattice mismatch f1 of the first electrode layer 20 and the resistive switching layer 30 in the resistive switching memory 100 prepared by the above steps to satisfy 0%≤f1<7%, and the lattice mismatch f2 of the second electrode layer 40 and the resistive switching layer 30 to satisfy 0%≤f2<7%. That is, by using the first electrode layer 20 and the second electrode layer 40 with low lattice mismatch with the resistive switching layer 30, the lattice mismatch stress can be alleviated, the interface stress accumulation can be reduced, and the stability and reliability of the resistive switching memory 100 can be improved.

[0090] Figure 7 This is a flowchart illustrating another method for fabricating a resistive random access memory (RAD) according to an embodiment of the present invention. Figure 7 The illustrated embodiment provides a detailed description of how to fabricate a resistive switching layer on the side of the first electrode layer away from the substrate layer. (Refer to...) Figure 7 The method for fabricating resistive random access memory in this embodiment of the invention includes:

[0091] S210, Prepare the substrate layer.

[0092] S220. Prepare a first electrode layer on one side of the substrate layer.

[0093] S230. Place the substrate layer and the first electrode layer in a vacuum chamber.

[0094] For example, refer to Figure 1 The prepared substrate layer 10 and the first electrode layer 20 are placed in a vacuum chamber.

[0095] S240. At a preset temperature, the reactive precursor and the reactant precursor are repeatedly introduced into the vacuum chamber until a preset number of times are reached, so as to form a resistive switching layer on the side of the first electrode layer away from the substrate layer, wherein the lattice mismatch f1 of the first electrode layer and the resistive switching layer satisfies 0%≤f1<7%.

[0096] For example, refer to Figure 1 The reactive precursor (e.g., trimethylaluminum) is deposited using atomic vapor deposition (ALD). The substrate 10 and the first electrode layer 20 are introduced into a vacuum chamber containing the substrate 10 and the first electrode layer 20, and the process is repeated 60-180 times at a temperature of 450°C.

[0097] S250. A second electrode layer is prepared on the side of the resistive switching layer away from the first electrode layer, wherein the lattice mismatch f2 between the second electrode layer and the resistive switching layer satisfies 0%≤f2<7%.

[0098] Figure 8 A flowchart illustrating another method for fabricating a resistive random access memory (RAD) according to an embodiment of the present invention. Figure 8 The illustrated embodiments enrich the fabrication process of resistive switching memory and further illustrate how to fabricate the second electrode layer on the side of the resistive switching layer away from the first electrode layer. (Refer to...) Figure 8 The method for fabricating resistive random access memory in this embodiment of the invention includes:

[0099] S310, Prepare the substrate layer.

[0100] S320. Prepare a first electrode layer on one side of the substrate layer.

[0101] S330. A resistive switching layer is prepared on the side of the first electrode layer away from the substrate layer, wherein the lattice mismatch f1 between the first electrode layer and the resistive switching layer satisfies 0%≤f1<7%.

[0102] S340. An enhancement layer is prepared on the side of the resistive switching layer away from the first electrode layer.

[0103] For example, refer to Figure 4 and Figure 5Oxygen ions can be diffused into the surface of the resistive switching layer 30, which is composed of aluminum nitride, to form an aluminum oxynitride layer, i.e., the reinforcement layer 50. The thickness M1 of the reinforcement layer 50 satisfies 0 nm < M1 < 5 nm. During the plasma oxidation process, the sample consisting of the substrate layer 10, the first electrode layer 20, and the resistive switching layer 30 is placed in an ICP chamber (Multiplex ICP, STSInc). The oxygen (O2) flow rate is 30 sccm, the platen power is 20 W, the coil power is 50 W, and the oxidation time is 5 min. During the high-temperature annealing, the sample is placed in a furnace and annealed in nitrogen (N2) at 800°C for 30 minutes.

[0104] The surface of the aluminum nitride layer is reconstructed by plasma oxidation and high-temperature annealing, and lattice stress is controlled by using the oxygen-doped heterojunction between aluminum nitride and aluminum oxynitride.

[0105] S350. A second electrode layer is prepared on the side of the reinforcement layer away from the resistive switching layer, wherein the lattice mismatch f2 between the second electrode layer and the resistive switching layer satisfies 0%≤f2<7%.

[0106] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A resistive random access memory, characterized in that, include: Substrate layer; The first electrode layer is located on one side of the substrate layer; A resistive switching layer is located on the side of the first electrode layer away from the substrate layer; The second electrode layer is located on the side of the resistive switching layer away from the first electrode layer; Wherein, the lattice mismatch f1 between the first electrode layer and the resistive switching layer satisfies 0% ≤ f1 < 7%, and the lattice mismatch f2 between the second electrode layer and the resistive switching layer satisfies 0% ≤ f2 < 7%; The resistive switching layer is made of aluminum nitride; The material of the first electrode layer includes a tungsten-rhenium alloy; The material of the second electrode layer includes a tungsten-rhenium alloy; The rhenium content W1 in the tungsten-rhenium alloy satisfies 3% ≤ W1 ≤ 12%.

2. The resistive random access memory according to claim 1, characterized in that, The percentage difference P1 between the thermal expansion coefficient of the first electrode layer and the thermal expansion coefficient of the resistive switching layer satisfies 0% ≤ P1 < 10%; The percentage difference P2 between the thermal expansion coefficient of the second electrode layer and the thermal expansion coefficient of the resistive switching layer satisfies 0% ≤ P2 < 10%.

3. The resistive random access memory according to claim 1, characterized in that, It also includes a reinforcement layer located between the second electrode layer and the resistive switching layer; The reinforcing layer is made of aluminum oxynitride.

4. The resistive random access memory according to claim 3, characterized in that, The thickness M1 of the reinforcement layer satisfies 0nm < M1 < 5nm.

5. The resistive random access memory according to claim 1, characterized in that, The thickness M2 of the resistive switching layer satisfies 5nm≤M2≤15nm; The thickness M3 of the first electrode layer satisfies 20nm ≤ M3 < 50nm; The thickness M4 of the second electrode layer satisfies 20nm ≤ M4 < 50nm.

6. A method for fabricating a resistive switching memory (RSM), used to fabricate the RSM as described in any one of claims 1-5, characterized in that, The preparation method includes: Preparation of substrate layer; A first electrode layer is prepared on one side of the substrate layer; the material of the first electrode layer includes a tungsten-rhenium alloy. A resistive switching layer is prepared on the side of the first electrode layer away from the substrate layer, wherein the lattice mismatch f1 between the first electrode layer and the resistive switching layer satisfies 0%≤f1<7%; the material of the resistive switching layer includes aluminum nitride. A second electrode layer is prepared on the side of the resistive switching layer away from the first electrode layer, wherein the lattice mismatch f2 between the second electrode layer and the resistive switching layer satisfies 0%≤f2<7%; the material of the second electrode layer includes a tungsten-rhenium alloy; the rhenium content W1 in the tungsten-rhenium alloy satisfies 3%≤W1≤12%.

7. The preparation method according to claim 6, characterized in that, A resistive switching layer is fabricated on the side of the first electrode layer away from the substrate layer, including: The substrate layer and the first electrode layer are placed in a vacuum cavity; At a preset temperature, the reactive precursor and reactant precursor are repeatedly introduced into the vacuum cavity until a preset number of times are reached, so as to form the resistive switching layer on the side of the first electrode layer away from the substrate layer.

8. The preparation method according to claim 6, characterized in that, After fabricating a resistive switching layer on the side of the first electrode layer away from the substrate layer, the fabrication method further includes: A reinforcement layer is prepared on the side of the resistive switching layer away from the first electrode layer; A second electrode layer is fabricated on the side of the resistive switching layer away from the first electrode layer, including: A second electrode layer is prepared on the side of the reinforcement layer away from the resistive switching layer.

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