Method of manufacturing light emitting device, light emitting device and display apparatus including the same

Abstract

The method of manufacturing a light emitting element includes: patterning a first semiconductor layer on a substrate; patterning a first insulating layer on a side surface of the first semiconductor layer; and forming an active layer and a second semiconductor layer on the first semiconductor layer.

Description

Technical Field

[0001] Various embodiments relate to a light emitting element, a method of manufacturing a light emitting element, and a display device including the light emitting element. Background Art

[0002] With the development of information technology, the importance of display devices as a connection medium between users and information has increased. Display devices may include light-emitting elements that emit light. The light-emitting elements may be diodes including a P-type semiconductor, an N-type semiconductor, and a quantum well structure disposed therebetween.

[0003] In order to manufacture a high-performance display device with high resolution, it is necessary to reduce the size of a light emitting element and further improve the emission efficiency of the light emitting element.

[0004] It is necessary to eliminate process risks occurring during the process of manufacturing a light emitting element. Summary of the Invention

[0005] Technical issues

[0006] Various embodiments provide a light emitting element, a method of manufacturing a light emitting element, and an apparatus including a light emitting element, which can reduce or minimize the risk of defects in a process of manufacturing the light emitting element and can improve emission efficiency.

[0007] However, the embodiments of the present disclosure are not limited to those described herein. The above and other embodiments will become more apparent to those skilled in the art to which the present disclosure pertains by referencing the detailed description of the present disclosure given below.

[0008] Technical Solution

[0009] In an embodiment, a method of manufacturing a light emitting element may include patterning a first semiconductor layer on a substrate; patterning a first insulating layer on a side surface of the first semiconductor layer; and forming an active layer and a second semiconductor layer on the first semiconductor layer.

[0010] In an embodiment, patterning the first semiconductor layer may include: forming a base semiconductor layer on a substrate; and etching at least a portion of the base semiconductor layer by using a mask exposing an upper surface of the base semiconductor layer.

[0011] In an embodiment, patterning the first semiconductor layer and forming the second semiconductor layer may be performed in separate processes.

[0012] In an embodiment, forming the active layer and the second semiconductor layer may include depositing the active layer and the second semiconductor layer.Depositing the active layer and the second semiconductor layer may include separately patterning the active layer and the second semiconductor layer.

[0013] In an embodiment, patterning the first insulating layer may include exposing an upper surface of the first semiconductor layer from the first insulating layer.

[0014] In an embodiment, forming the active layer and the second semiconductor layer may include growing the active layer and the second semiconductor layer on an exposed upper surface of the first semiconductor layer.

[0015] In an embodiment, the first insulating layer may cover side surfaces of the first semiconductor layer so that the active layer and the second semiconductor layer may not be grown on the side surfaces of the first semiconductor layer.

[0016] In an embodiment, the method may further include patterning the second insulating layer. Patterning the second insulating layer may include: disposing a first portion of the second insulating layer on the first insulating layer; and disposing a second portion of the second insulating layer on side surfaces of the active layer and side surfaces of the second semiconductor layer.

[0017] In an embodiment, the method may further include patterning an electrode layer on the second semiconductor layer after patterning the second insulating layer.

[0018] In an embodiment, the first semiconductor layer, the active layer, and the second semiconductor layer may form a semiconductor stack member. The first semiconductor layer may include adjacent first semiconductor layers. The method may further include: forming a lower active layer and a lower second semiconductor layer between the adjacent first semiconductor layers while forming the active layer and the second semiconductor layer; and separating the semiconductor stack member from the substrate. Separating the semiconductor stack member includes individually separating the semiconductor stack member along a separation line that is a portion of the first semiconductor layer. The separation line may be defined at a position substantially equal to or higher than the uppermost surface of the lower second semiconductor layer.

[0019] In an embodiment, the method may further include forming an additional first semiconductor layer on the first semiconductor layer.

[0020] In an embodiment, the method may further include forming an active layer and a second semiconductor layer on the additional first semiconductor layer. The surface area (or surface size) of the upper surface of the first semiconductor layer on which the additional first semiconductor layer is grown may be smaller than the surface area (or surface size) of an adjacent surface between the additional first semiconductor layer and the active layer.

[0021] In an embodiment, a light emitting element may include a semiconductor stack member and an insulating layer disposed on a side surface of the semiconductor stack member, the semiconductor stack member including a first semiconductor layer, a second semiconductor layer, and an active layer disposed between the first and second semiconductor layers. The insulating layer may include a first insulating layer disposed on a side surface of the first semiconductor layer and exposing a side surface of the active layer or a side surface of the second semiconductor layer, and a second insulating layer disposed on a side surface of the semiconductor stack member. The second insulating layer may include a first portion that does not contact the first semiconductor layer due to the first insulating layer being interposed between the first portion and the first semiconductor layer, and a second portion that contacts the active layer and the second semiconductor layer.

[0022] In an embodiment, the active layer may include: a quantum well layer including a first side surface; and a quantum barrier layer including a second side surface, and the first side surface and the second side surface may form a flat plane.

[0023] In an embodiment, the first side surface and the second side surface may form side surfaces without any recessed portion.

[0024] In an implementation, the second insulating layer may form a stepped portion in a region between the first portion and the second portion of the second insulating layer.

[0025] In an embodiment, the insulating layer may have a first thickness in a region overlapping the first semiconductor layer, and a second thickness smaller than the first thickness in a region overlapping the active layer.

[0026] In an embodiment, the first insulating layer may not cover side surfaces of the active layer and the second semiconductor layer.

[0027] In an embodiment, the active layer and the first semiconductor layer may have the same cross-sectional size.

[0028] In an embodiment, the active layer may include an active surface facing the first semiconductor layer. The active surface may completely cover the first semiconductor layer and include a portion of the active surface that does not contact the first semiconductor layer.

[0029] In an embodiment, the active layer may have a truncated shape.

[0030] In an embodiment, the first semiconductor layer may include a body overlapping the first insulating layer and the second insulating layer; and a protrusion protruding from the body.

[0031] In an embodiment, the light emitting element may further include: a first end portion adjacent to the first semiconductor layer; a second end portion adjacent to the second semiconductor layer; and an auxiliary semiconductor layer disposed on the first insulating layer in a region adjacent to the first end portion and including the same material as that of the second semiconductor layer.

[0032] In an embodiment, the light emitting element may further include a first end portion adjacent to the first semiconductor layer; a second end portion adjacent to the second semiconductor layer; an electrode layer disposed on the second semiconductor layer; and an auxiliary electrode layer disposed on the first insulating layer in a region adjacent to the first end portion and including a material substantially the same as that of the electrode layer.

[0033] Embodiments may provide a display device, which may include: a base layer; and a light-emitting element layer disposed on the base layer and including a light-emitting element. The light-emitting element layer may include: a first electrode and a second electrode spaced apart from each other; an anode connection electrode electrically connected to a first end portion of the light-emitting element; and a cathode connection electrode electrically connected to a second end portion of the light-emitting element. The light-emitting element may be aligned between the first electrode and the second electrode.

[0034] Beneficial effects

[0035] Various embodiments can provide a light emitting element, a method of manufacturing a light emitting element, and a device including a light emitting element, which can reduce or minimize the risk of defects in a process of manufacturing the light emitting element and can improve emission efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Figures 1 to 3 is a schematic diagram illustrating a light emitting element according to a first embodiment.

[0037] Figure 4 and Figure 5 is a schematic diagram illustrating a light emitting element according to a second embodiment.

[0038] Figure 6 is a schematic cross-sectional view showing a light emitting element according to a third embodiment.

[0039] Figure 7 is a schematic cross-sectional view showing a light emitting element according to a fourth embodiment.

[0040] Figure 8 is a schematic cross-sectional view showing a light emitting element according to a fifth embodiment.

[0041] Figure 9 is a schematic cross-sectional view showing a light emitting element according to a sixth embodiment.

[0042] Figure 10 is a schematic plan view showing a display device according to an embodiment.

[0043] Figure 11 is a schematic cross-sectional view illustrating a display device according to an embodiment.

[0044] Figure 12is a schematic cross-sectional view showing a connection electrode and a light emitting element according to an embodiment.

[0045] Figure 13 is a schematic flowchart illustrating a method of manufacturing a light emitting element according to one or more embodiments.

[0046] Figure 14 、 Figure 15 as well as Figures 19 to 28 is a schematic cross-sectional view illustrating a method of manufacturing a light emitting element according to one or more embodiments.

[0047] Figures 16 to 18 are schematic plan views each illustrating a method of manufacturing a light emitting element according to an embodiment.

[0048] Figure 29 is a schematic flowchart illustrating a method of manufacturing a light emitting element according to a fifth embodiment.

[0049] Figures 30 to 32 is a schematic cross-sectional view illustrating a method of manufacturing a light emitting element according to a fifth embodiment.

[0050] Figure 33 is a schematic flowchart illustrating a method of manufacturing a light emitting element according to a sixth embodiment.

[0051] Figures 34 to 38 is a schematic cross-sectional view illustrating a method of manufacturing a light emitting element according to a sixth embodiment. DETAILED DESCRIPTION

[0052] In the following description, for the purpose of explanation, many specific details are set forth to provide a thorough understanding of various embodiments or implementations of the present invention. As used herein, "embodiment" and "implementation" are interchangeable words that are non-limiting examples of the apparatus or method disclosed herein. However, it is apparent that various embodiments can be practiced without these specific details or with one or more equivalent arrangements. Here, various embodiments do not necessarily have to be exclusive or limit the present disclosure. For example, the specific shape, configuration, and characteristics of an embodiment can be used or implemented in another embodiment.

[0053] Unless otherwise indicated, the illustrated embodiments should be understood to provide features of the present invention. Therefore, unless otherwise indicated, the features, components, modules, layers, films, panels, regions and / or aspects, etc. (hereinafter, individually or collectively referred to as "elements") of the various embodiments may be combined, separated, interchanged and / or rearranged in other ways without departing from the present invention.

[0054] The use of cross hatching and / or shading in the drawings is generally provided to clarify the boundaries between adjacent elements. As such, unless specified, the presence or absence of cross hatching or shading does not convey or indicate any preference or requirement for a particular material, material properties, size, ratio, commonality between the elements shown, and / or any other characteristics, attributes, properties, etc. of the elements. In addition, in the drawings, the size and relative size of the elements may be exaggerated for clarity and / or descriptive purposes. When the embodiments can be implemented differently, a specific process sequence may be performed differently from the described sequence. For example, two processes described in succession may be performed substantially simultaneously or in an order opposite to the described sequence. In addition, the same reference numerals represent the same elements.

[0055] When an element, such as a layer, is referred to as being "on," "connected to," or "coupled to" another element or layer, it may be directly on, directly connected to, or directly coupled to the other element or layer, or there may be intervening elements or layers. However, when an element or layer is referred to as being "directly on," "directly connected to," or "directly coupled to" another element or layer, there may be no intervening elements or layers. For this purpose, the term "connected" may refer to a physical connection, an electrical connection, and / or a fluid connection with or without intervening elements. Furthermore, the DR1, DR2, and DR3 axes are not limited to the three axes of a rectangular coordinate system (such as the X, Y, and Z axes) and may be interpreted in a broader sense. For example, the DR1, DR2, and DR3 axes may be perpendicular to each other, or may represent different directions that are not perpendicular to each other. Furthermore, the X, Y, and Z axes are not limited to the three axes of a rectangular coordinate system (such as the X, Y, and Z axes) and may be interpreted in a broader sense. For example, the X-axis, Y-axis, and Z-axis may be perpendicular to each other, or may represent different directions that are not perpendicular to each other. For the purposes of this disclosure, "at least one of A and B" may be interpreted to mean only A, only B, or any combination of A and B. In addition, "at least one of X, Y, and Z" and "at least one selected from the group consisting of X, Y, and Z" may be interpreted to mean only X, only Y, only Z, or any combination of two or more of X, Y, and Z. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0056] Although the terms "first," "second," etc. may be used herein to describe various types of elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another. Thus, the first element discussed below may be referred to as the second element without departing from the teachings of the present disclosure.

[0057] For descriptive purposes, spatially relative terms such as "below," "beneath," "under," "above," "upper," "above," "higher," "side" (e.g., as in "sidewall"), etc. may be used herein and thereby describe the relationship of one element to another element(s) as shown in the drawings. Spatially relative terms are intended to encompass different orientations of the device in use, operation, and / or manufacture in addition to the orientation depicted in the drawings. For example, if the device in the drawings is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the term "below" can encompass both above and below orientations. Additionally, the device may be otherwise oriented (e.g., rotated 90 degrees or at other orientations), and therefore, the spatially relative descriptors used herein should be interpreted accordingly.

[0058] The terms used herein are for the purpose of describing particular embodiments and are not intended to be limiting. As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. In addition, when used in this specification, the terms "comprises," "comprising," "includes," and / or "including" specify the presence of the recited features, wholes, steps, operations, elements, components, and / or groups thereof, but do not preclude the presence or addition of one or more other features, wholes, steps, operations, elements, components, and / or groups thereof. It is also noted that, as used herein, the terms "substantially," "about," and other similar terms are used as terms of approximation and not as terms of degree, and are therefore used to allow for inherent deviations in measurements, calculations, and / or provided values that would be recognized by one of ordinary skill in the art.

[0059] Various embodiments are described herein with reference to cross-sectional views and / or exploded views that are schematic diagrams of embodiments and / or intermediate structures. Therefore, variations in the illustrated shapes due to, for example, manufacturing techniques and / or tolerances should be expected. Therefore, the embodiments disclosed herein should not necessarily be interpreted as being limited to the specific illustrated shapes of the regions, but should include deviations in shapes due to, for example, manufacturing. In this way, the regions shown in the drawings may be schematic in nature, and the shapes of these regions may not reflect the actual shapes of the regions of the device, and are not necessarily intended to be limiting.

[0060] Various embodiments relate to a method of manufacturing a light emitting element, a light emitting element, and a display device including the light emitting element. Hereinafter, a light emitting element, a method of manufacturing a light emitting element, and a display device including the light emitting element according to the embodiments will be described with reference to the accompanying drawings.

[0061] The light emitting element LD according to the embodiment can be manufactured without performing an etching process on the active layer AL. Therefore, the risk of defects in manufacturing the light emitting element LD can be reduced, thereby improving emission efficiency.

[0062] Will refer to Figures 1 to 9 The light emitting element LD according to one or more embodiments is described.

[0063] Will refer to Figures 1 to 3 A light emitting element LD according to a first embodiment is described.

[0064] Figures 1 to 3 1 and 2 are schematic diagrams each showing a light emitting element LD according to the first embodiment. Figure 1 is a schematic cross-sectional view showing the light emitting element LD according to the first embodiment. Figure 2 is a schematic perspective view showing the light emitting element LD according to the first embodiment. Figure 3 is a schematic cross-sectional view showing the active layer AL of the light emitting element LD according to the first embodiment.

[0065] The light emitting element LD may emit light. The light emitting element LD may include a semiconductor stack member ESS and an insulating layer INF. The semiconductor stack member ESS may include a first semiconductor layer SCL1, a second semiconductor layer SCL2, and an active layer AL disposed between the first and second semiconductor layers SCL1 and SCL2. In an embodiment, the light emitting element LD may further include an electrode layer ELL.

[0066] In an embodiment, the first semiconductor layer SCL1 , the active layer AL, and the second semiconductor layer SCL2 may be continuously stacked in a longitudinal direction of the light emitting element LD, which extends in a direction of a length L of the light emitting element LD.

[0067] The light-emitting element LD can have various shapes. For example, the light-emitting element LD can have a columnar shape extending in a direction (e.g., a longitudinal direction). In embodiments, the cross-sectional shape of the light-emitting element LD is not limited. For example, the cross-sectional shape of the light-emitting element LD can have a circular shape or an elliptical shape. In another example, the cross-sectional shape of the light-emitting element LD can have an n-gonal shape, where n is an integer of 3 or greater.

[0068] The light emitting element LD may include a first end portion EP1 and a second end portion EP2. In an embodiment, the first semiconductor layer SCL1 may be adjacent to the first end portion EP1 of the light emitting element LD. The second semiconductor layer SCL2 may be adjacent to the second end portion EP2. In an embodiment, the electrode layer ELL may be adjacent to the second end portion EP2.

[0069] The light emitting element LD may have various sizes. In an embodiment, the diameter D (or width) of the light emitting element LD and the length L of the light emitting element LD may each be within a range from nanometers to micrometers. However, the embodiment is not limited thereto.

[0070] The first semiconductor layer SCL1 may include a first conductive semiconductor. The first semiconductor layer SCL1 may be disposed on the active layer AL and include a semiconductor layer having a different type from that of the second semiconductor layer SCL2. For example, the first semiconductor layer SCL1 may include an N-type semiconductor layer. For example, the first semiconductor layer SCL1 may include one or more selected from the group consisting of InAlGaN, GaN, AlGaN, InGaN, AlN, AlGaINP, GaAs, and InN, and may include an N-type semiconductor layer doped with a first conductive dopant such as Si, Ge, and Sn. However, embodiments are not limited thereto. The first semiconductor layer SCL1 may include various materials.

[0071] The active layer AL may be disposed between the first semiconductor layer SCL1 and the second semiconductor layer SCL2. The position of the active layer AL may be changed in various ways according to the type of the light emitting element LD.

[0072] The active layer AL may include a single quantum well structure or a multiple quantum well structure.

[0073] The active layer AL may include a quantum well layer WL and a quantum barrier layer BL. The quantum barrier layer BL may form a quantum barrier for forming a quantum well structure. The quantum well layer WL may form a quantum well for forming a quantum well structure. For example, the quantum barrier layer BL may include GaN, and the quantum well layer WL may include InGaN. However, embodiments are not limited thereto.

[0074] The second semiconductor layer SCL2 may include a second conductive semiconductor. The second semiconductor layer SCL2 may be disposed on the active layer AL and include a semiconductor layer of a different type from that of the first semiconductor layer SCL1. For example, the second semiconductor layer SCL2 may include a P-type semiconductor layer. For example, the second semiconductor layer SCL2 may include one or more semiconductor materials selected from the group consisting of InAlGaN, GaN, AlGaN, InGaN, AlN, AlGaINP, GaAs, and InN, and may include a P-type semiconductor layer doped with a second conductive dopant such as Ga, B, and Mg. However, embodiments are not limited thereto. The second semiconductor layer SCL2 may include various materials.

[0075] In an embodiment, the active layer AL and the first semiconductor layer SCL1 may be adjacent to each other (e.g., may be in contact with each other). In an embodiment, the surface area (or surface size) of the first surface of the active layer AL facing the first semiconductor layer SCL1 and the surface area (or surface size) of the surface of the first semiconductor layer SCL1 facing the active layer AL may be the same. For example, when the active layer AL is grown on the upper surface of the first semiconductor layer SCL1 after forming the first semiconductor layer SCL1, the surface area (or surface size) of the surface of the active layer AL and the surface area (or surface size) of the surface of the first semiconductor layer SCL1 may be the same.

[0076] In an embodiment, the active layer AL and the second semiconductor layer SCL2 may be adjacent to each other (e.g., may be in contact with each other). In an embodiment, the surface area (or surface size) of the second surface of the active layer AL facing the second semiconductor layer SCL2 and the surface area (or surface size) of the surface of the second semiconductor layer SCL2 facing the active layer AL may be the same as each other.

[0077] In an embodiment, the active layer AL and the second semiconductor layer SCL2 may have a uniform cross-sectional area (or uniform cross-sectional size) (e.g., in a lateral direction (or width direction)). For example, the active layer AL and the second semiconductor layer SCL2 may be grown on the first semiconductor layer SCL1 and formed to have a substantially uniform cross-sectional area (or uniform cross-sectional size) (e.g., in a lateral direction (or width direction)).

[0078] The active layer AL may include a side surface having a minimally curved portion and thus having a substantially flat surface. For example, the quantum well layer WL may have a first side surface S1, and the quantum barrier layer BL may have a second side surface S2. For example, the first side surface S1 and the second side surface S2 may have a flat plane (e.g., a flat surface).

[0079] For example, each of the first side surface S1 and the second side surface S2 may not have a groove. In an embodiment, the first side surface S1 and the second side surface S2 may form side surfaces without a recess (eg, flat side surfaces).

[0080] In this specification, the term "side surface" may refer to a portion of an object (e.g., a semiconductor stack member ESS, an active layer AL, a first semiconductor layer SCL1, a second semiconductor layer SCL2, etc.) including a portion of the remaining area excluding the upper and lower surfaces of the object. For example, the upper and lower surfaces of the object may refer to surfaces corresponding to the first end portion EP1 or the second end portion EP2 of the light-emitting element LD (or the semiconductor stack member ESS). In embodiments, the side surface may refer to a portion of the outer surface of the object defined between the first and second end portions EP1, EP2 of the light-emitting element LD (or the semiconductor stack member ESS).

[0081] For example, the active layer AL may be fabricated without performing a separate etching process. Therefore, in an embodiment, defects may not be formed in the active layer AL, and thus the emission efficiency of the light emitting element LD may be improved.

[0082] When a threshold voltage or higher is applied between the first end portion EP1 and the second end portion EP2 of the light-emitting element LD, electron-hole pairs in the active layer AL can recombine, and the light-emitting element LD can emit light. Since the light emission of the light-emitting element LD is controlled based on the aforementioned principle, the light-emitting element LD can be used as a light source in various devices.

[0083] An insulating layer INF may be disposed on a side surface of the semiconductor stack member ESS. The insulating layer INF may surround (or surround) at least a portion of the side surface of the active layer AL and may also surround (or surround) a portion of each of the first and second semiconductor layers SCL1 and SCL2.

[0084] The insulating layer INF may include a first insulating layer INF1 and a second insulating layer INF2. In an embodiment, the insulating layer INF may include an inorganic material.

[0085] In an embodiment, the first insulating layer INF1 and the second insulating layer INF2 may include the same inorganic material. In an embodiment, the first insulating layer INF1 and the second insulating layer INF2 may include different inorganic materials, respectively.

[0086] In an embodiment, the inorganic material may include a material selected from silicon oxide (SiO x ), silicon nitride (SiN x ), silicon oxynitride (SiO x N y ), aluminum oxide (Al x O y )、ZrO2(Zr x O y ), Hafnium Oxide (Hf x Oy ) and titanium oxide (TiO x ) is one or more of the groups consisting of .

[0087] The insulating layer INF may expose the first and second end portions EP1 and EP2 of the light emitting element LD having different polarities. For example, the insulating layer INF may expose respective end portions of the electrode layer ELL and the first semiconductor layer SCL1 adjacent to the first and second end portions EP1 and EP2 of the light emitting element LD.

[0088] The insulating layer INF can ensure the electrical stability of the light-emitting element LD. Furthermore, the insulating layer INF can minimize surface defects in the light-emitting element LD, thereby improving the lifespan and efficiency of the light-emitting element LD. When multiple light-emitting elements LD are arranged adjacent to each other, the insulating layer INF can prevent short circuit defects from occurring between the light-emitting elements LD.

[0089] The first insulating layer INF1 and the second insulating layer INF2 can be formed by different processes. For example, the first insulating layer INF1 can be formed before the second insulating layer INF2 is formed. In an embodiment, the first insulating layer INF1 can be patterned before the active layer AL and the second semiconductor layer SCL2 are formed. The second insulating layer INF2 can be patterned after the active layer AL and the second semiconductor layer SCL2 are formed.

[0090] In an embodiment, the first insulating layer INF1 forming the inner structure of the insulating layer INF may be selectively disposed at a position in the semiconductor stack member ESS.

[0091] For example, a stepped portion defined by the second insulating layer INF2 may be formed between a first side surface region of the semiconductor stack member ESS on which the first insulating layer INF1 is disposed and a second side surface region of the semiconductor stack member ESS on which the first insulating layer INF1 is not disposed.

[0092] For example, when the second insulating layer INF2 is provided on the entire surface of the side surface of the semiconductor stack structure ESS, the second insulating layer INF2 may form a step portion between a first side surface region of the semiconductor stack structure ESS on which the first insulating layer INF1 is provided and a second side surface region of the semiconductor stack structure ESS on which the first insulating layer INF1 is not provided.

[0093] In an embodiment, the thickness of the insulating layer INF in a region corresponding to the position of the first semiconductor layer SCL1 may be greater than the thickness of the insulating layer INF in a region corresponding to the position of the second semiconductor layer SCL2 and / or the active layer AL. For example, the insulating layer INF may have a first thickness TH1 in a region overlapping with the first semiconductor layer SCL1, and may have a second thickness TH2 that is less than the first thickness TH1 in a region overlapping with the active layer AL or the second semiconductor layer SCL2.

[0094] The first insulating layer INF1 may be disposed on side surfaces of the first semiconductor layer SCL1. For example, the first insulating layer INF1 may cover side surfaces of the first semiconductor layer SCL1 and may not cover corresponding side surfaces of the active layer AL and the second semiconductor layer SCL2.

[0095] The first insulating layer INF1 may be manufactured after forming the first semiconductor layer SCL1 and before forming the active layer AL and the second semiconductor layer SCL2. Therefore, the first insulating layer INF1 may determine a position where the active layer AL and the second semiconductor layer SCL2 will be formed.

[0096] The second insulating layer INF2 may be disposed on respective side surfaces of the first semiconductor layer SCL1, the active layer AL, and the second semiconductor layer SCL2. The second insulating layer INF2 may be disposed on the first insulating layer INF1. For example, the second insulating layer INF2 may cover respective side surfaces of the first semiconductor layer SCL1, the active layer AL, and the second semiconductor layer SCL2.

[0097] The second insulating layer INF2 may include a first portion P1 and a second portion P2, the first portion P1 overlaps with the first semiconductor layer SCL1 in the cross-sectional direction of the light emitting element LD (or in the lateral direction extending in the direction of the diameter D (or width) of the light emitting element LD), and the second portion P2 overlaps with the active layer AL or the second semiconductor layer SCL2 in the cross-sectional direction of the light emitting element LD (or in the lateral direction extending in the direction of the diameter D (or width) of the light emitting element LD).

[0098] The first portion P1 of the second insulating layer INF2 may not contact the first semiconductor layer SCL1 by the first insulating layer INF1 interposed therebetween. The second portion P2 of the second insulating layer INF2 may contact the active layer AL and the second semiconductor layer SCL2.

[0099] The first portion P1 of the second insulating layer INF2 may overlap with the first insulating layer INF1. The first portion P1 of the second insulating layer INF2 may be disposed on the first insulating layer INF1. In an embodiment, the first portion P1 of the second insulating layer INF2 may overlap with the first semiconductor layer SCL1 and the first insulating layer INF1, and may not overlap with the active layer AL and the second semiconductor layer SCL2.

[0100] The second portion P2 of the second insulating layer INF2 may not overlap with the first insulating layer INF1. The second portion P2 of the second insulating layer INF2 may be disposed on the active layer AL and the second semiconductor layer SCL2. In an embodiment, the second portion P2 of the second insulating layer INF2 may overlap with the active layer AL and the second semiconductor layer SCL2, and may not overlap with the first semiconductor layer SCL1.

[0101] A portion of the second insulating layer INF2 may not contact the semiconductor stack member ESS, while another portion of the second insulating layer INF2 may contact the semiconductor stack member ESS. For example, the first portion P1 of the second insulating layer INF2 may be separated from the semiconductor stack member ESS by the first insulating layer INF1. The second portion P2 of the second insulating layer INF2 may contact the semiconductor stack member ESS. For example, the second portion P2 of the second insulating layer INF2 may contact the active layer AL and the second semiconductor layer SCL2.

[0102] The second portion P2 of the second insulating layer INF2 may form a contact surface with the active layer AL or the second semiconductor layer SCL2. In an embodiment, a surface of the active layer AL facing the second insulating layer INF2 may include a substantially flat surface. Figure 3 , the active layer AL may include a first side surface S1 and a second side surface S2. The first side surface S1 and the second side surface S2 may face the second portion P2 of the second insulating layer INF2. In an embodiment, the first side surface S1 and the second side surface S2 of the active layer AL may contact the second insulating layer INF2.

[0103] The electrode layer ELL may be disposed on the second semiconductor layer SCL2 and adjacent to the second end portion EP2.

[0104] The electrode layer ELL may be connected (e.g., electrically connected) to the second semiconductor layer SCL2. A portion of the electrode layer ELL may be exposed. For example, the insulating layer INF may expose a surface of the electrode layer ELL. The electrode layer ELL may be exposed in a region corresponding to the second end portion EP2. In an embodiment, a side surface of the electrode layer ELL may be exposed.

[0105] In an embodiment, the electrode layer ELL may be an ohmic contact electrode. However, the embodiment is not limited thereto. For example, the electrode layer ELL may be a Schottky contact electrode.

[0106] In embodiments, the electrode layer ELL may be substantially transparent. For example, the electrode layer ELL may include indium tin oxide (ITO). Thus, the electrode layer ELL may transmit emitted light therethrough. However, embodiments are not limited thereto. In embodiments, the electrode layer ELL may include one or more selected from the group consisting of chromium (Cr), titanium (Ti), aluminum (Al), gold (Au), nickel (Ni), and oxides or alloys thereof.

[0107] The structure of the light emitting element LD according to the embodiment is not limited thereto. For example, the light emitting element LD may include a superlattice layer disposed between the first semiconductor layer SCL1 and the active layer AL and / or a strain relief layer disposed between the active layer AL and the second semiconductor layer SCL2.

[0108] In embodiments, a superlattice layer may have a structure formed by alternating stacks of two or more layers having different compositions. For example, a superlattice layer may have a structure in which GaN layers and InGaN layers are alternately stacked. In embodiments, the superlattice layer may alleviate (or reduce) stress between the first semiconductor layer SCL1 and the active layer AL. The electron blocking layer may block at least some of the electrons between the active layer AL and the second semiconductor layer SCL2, thereby improving the efficiency of electron-hole pair recombination for light emission.

[0109] In an embodiment, the electron blocking layer may include a material having a band gap energy greater than that of the second semiconductor layer SCL2 to prevent overflow of electrons. For example, the electron blocking layer may include AlGaN doped with Mg.

[0110] Will refer to Figure 4 and Figure 5 The light emitting element LD according to the second embodiment will be described. The features of the light emitting element LD according to the second embodiment will be described focusing on the differences from the light emitting element LD of the first embodiment described above. For the sake of convenience, redundant descriptions similar to or identical to those of the above embodiments will be simplified or omitted.

[0111] Figure 4 and Figure 5 2 is a schematic diagram illustrating a light emitting element LD according to a second embodiment. Figure 4 is a schematic cross-sectional view showing a light emitting element LD according to a second embodiment. Figure 5 is a schematic perspective view showing a light emitting element LD according to a second embodiment.

[0112] The light emitting element LD according to the second embodiment is different from the light emitting element LD according to the first embodiment in that the active layer AL and the second semiconductor layer SCL2 each have a larger cross-sectional area than that of the first semiconductor layer SCL1 .

[0113] The active layer AL may include an active surface facing the first semiconductor layer SCL1. The first semiconductor layer SCL1 may include a semiconductor surface facing the active layer AL. For example, the active surface of the active layer AL may have a surface area (or surface size) larger than the surface area (or surface size) of the semiconductor surface of the first semiconductor layer SCL1.

[0114] For example, the active surface of the active layer AL may cover the entire surface of the semiconductor surface of the first semiconductor layer SCL1. The active surface of the active layer AL may include the semiconductor surface of the first semiconductor layer SCL1 and may include some areas that do not contact the semiconductor surface of the first semiconductor layer SCL1.

[0115] The second semiconductor layer SCL2 may include a semiconductor surface facing the first semiconductor layer SCL1. For example, the semiconductor surface of the second semiconductor layer SCL2 may have a surface area (or surface size) larger than the surface area (or surface size) of the semiconductor surface of the first semiconductor layer SCL1. In embodiments, the semiconductor surface of the second semiconductor layer SCL2 may have a surface area (or surface size) corresponding to the surface area (or surface size) of the active surface of the active layer AL. In embodiments, the surface area of the electrode layer ELL may have a surface area (or surface size) corresponding to the surface area (or surface size) of the active surface of the active layer AL.

[0116] In an embodiment, the active surface of the active layer AL may overlap with at least a portion of the first insulating layer INF1. For example, a portion of the active surface of the active layer AL may not contact the first semiconductor layer SCL1, may contact the first insulating layer INF1 (for example, the upper surface of the first insulating layer INF1 in the longitudinal direction), and may overlap with a side surface of the second insulating layer INF2 in the thickness direction of the second insulating layer INF2.

[0117] For example, when the active surface of the active layer AL covers the entire surface of the semiconductor surface of the first semiconductor layer SCL1 , an electrical contact region between the first semiconductor layer SCL1 and the active layer AL may be reliably formed.

[0118] Will refer to Figure 6A light emitting element LD according to a third embodiment will be described. The features of the light emitting element LD according to the third embodiment will be described focusing on differences from the light emitting element LD of the first embodiment described above. For convenience of description, redundant descriptions similar to or identical to those of the above embodiments will be simplified or omitted.

[0119] Figure 6 is a schematic cross-sectional view showing a light emitting element LD according to a third embodiment.

[0120] The light emitting element LD according to the third embodiment is different from the light emitting element LD according to the first embodiment in that a cross-sectional area of each of the active layer AL and the second semiconductor layer SCL2 increases in a direction adjacent to the second end portion EP2 of the light emitting element LD.

[0121] In an embodiment, the active layer AL and the second semiconductor layer SCL2 may each have an approximately truncated shape, such as a truncated cone shape and a truncated n-gon shape, where n is a natural number of 3 or greater.

[0122] For example, the active layer AL may have a cross-sectional area that increases in a direction from a region adjacent to the first end portion EP1 toward a region adjacent to the second end portion EP2. The second semiconductor layer SCL2 may have a cross-sectional area that increases in a direction from a region adjacent to the first end portion EP1 toward a region adjacent to the second end portion EP2.

[0123] In an embodiment, the second portion P2 of the second insulating layer INF2 may have a thickness complementary to the cross-sectional area of the active layer AL and the second semiconductor layer SCL2. For example, the second portion P2 of the second insulating layer INF2 may have a thickness that increases toward the second end portion EP2 as it approaches the first end portion EP1. Thus, the light emitting element LD may have a substantially uniform cross-sectional area (e.g., in a lateral direction (or width direction)) in the region corresponding to the active layer AL and the second semiconductor layer SCL2.

[0124] Will refer to Figure 7 A light emitting element LD according to a fourth embodiment will be described. Features of the light emitting element LD according to the fourth embodiment will be described focusing on differences from the light emitting element LD of the above embodiments. For convenience of description, redundant descriptions similar to or identical to those of the above embodiments will be simplified or omitted.

[0125] Figure 7 is a schematic cross-sectional view showing a light emitting element LD according to a fourth embodiment.

[0126] The light emitting element LD according to the fourth embodiment is different from the light emitting element LD according to the above embodiments in that the light emitting element LD according to the fourth embodiment further includes an auxiliary semiconductor layer RSCL.

[0127] The auxiliary semiconductor layer RSCL may be disposed on the first insulating layer INF1 in the same manner as the first portion P1 of the second insulating layer INF2. For example, the auxiliary semiconductor layer RSCL may be disposed on the outer periphery of the first insulating layer INF1. The auxiliary semiconductor layer RSCL may overlap the semiconductor stack member ESS in the radial direction of the light emitting element LD.

[0128] The auxiliary semiconductor layer RSCL may be disposed on the first insulating layer INF1. For example, the auxiliary semiconductor layer RSCL and the second insulating layer INF2 may be adjacent to each other, may contact each other, and may be disposed on the same layer (eg, the first insulating layer INF1).

[0129] The auxiliary semiconductor layer RSCL may be disposed on the first insulating layer INF1 in a region adjacent to the first end portion EP1 of the light-emitting element LD. For example, the auxiliary semiconductor layer RSCL may be disposed on the first insulating portion of the first insulating layer INF1, and the first portion P1 of the second insulating layer INF2 may be disposed on the second insulating portion of the first insulating layer INF1. For example, the first insulating portion of the first insulating layer INF1 may be closer to the first end portion EP1 of the light-emitting element LD than the second insulating portion of the first insulating layer INF1, and may not overlap with the second insulating portion of the first insulating layer INF1 in a cross-sectional direction of the light-emitting element LD (or in a lateral direction extending in the direction of the diameter D (or width) of the light-emitting element LD).

[0130] The auxiliary semiconductor layer RSCL and the second semiconductor layer SCL2 may include the same material. For example, the auxiliary semiconductor layer RSCL may include a P-type semiconductor material and may include one or more of the materials described above with respect to the second semiconductor layer SCL2. The auxiliary semiconductor layer RSCL and the second semiconductor layer SCL2 may be grown (or formed) using the same process. Therefore, in embodiments, the light-emitting element LD including the auxiliary semiconductor layer RSCL may be manufactured without an additional process for manufacturing the auxiliary semiconductor layer RSCL.

[0131] Will refer to Figure 8 A light emitting element LD according to a fifth embodiment will be described. The features of the light emitting element LD according to the fifth embodiment will be described focusing on differences from the light emitting element LD of the above embodiments. For convenience of description, redundant descriptions similar to or identical to those of the above embodiments will be simplified or omitted.

[0132] Figure 8 is a schematic cross-sectional view showing a light emitting element LD according to a fifth embodiment.

[0133] The light emitting element LD according to the fifth embodiment differs from the light emitting element LD according to the above embodiments in that the light emitting element LD according to the fifth embodiment further includes an auxiliary electrode layer RELL. The auxiliary electrode layer RELL may be provided at a position corresponding to the auxiliary semiconductor layer RSCL.

[0134] The auxiliary electrode layer RELL may be provided on the first insulating layer INF1 in the same manner as the first portion P1 of the second insulating layer INF2. For example, the auxiliary electrode layer RELL may be provided on the outer periphery of the first insulating layer INF1. The auxiliary electrode layer RELL may overlap the semiconductor stack member ESS in the radial direction of the light emitting element LD.

[0135] The auxiliary electrode layer RELL may be disposed on the first insulating layer INF1. For example, the auxiliary electrode layer RELL and the second insulating layer INF2 may be adjacent to each other, may contact each other, and may be disposed on the same layer (eg, the first insulating layer INF1).

[0136] The auxiliary electrode layer RELL may be provided on the first insulating layer INF1 in a region adjacent to the first end portion EP1 of the light-emitting element LD. For example, the auxiliary electrode layer RELL may be provided on the first insulating portion of the first insulating layer INF1, and the first portion P1 of the second insulating layer INF2 may be provided on the second insulating portion of the first insulating layer INF1. For example, the first insulating portion of the first insulating layer INF1 may be closer to the first end portion EP1 of the light-emitting element LD than the second insulating portion of the first insulating layer INF1, and may not overlap with the second insulating portion of the first insulating layer INF1 in a cross-sectional direction of the light-emitting element LD (or in a lateral direction extending in the direction of the diameter D (or width) of the light-emitting element LD).

[0137] The auxiliary electrode layer RELL and the electrode layer ELL may include the same material. For example, the auxiliary electrode layer RELL may include a conductive material and may include one or more of the materials described above with respect to the electrode layer ELL. The auxiliary electrode layer RELL and the electrode layer ELL may be deposited (or formed) using the same process. Therefore, in embodiments, the light-emitting element LD including the auxiliary electrode layer RELL can be manufactured without an additional process for manufacturing the auxiliary electrode layer RELL. In embodiments, the auxiliary electrode layer RELL may help the light-emitting element LD more reliably connect (e.g., electrically connect) to other lines. For example, the first end portion EP1 of the light-emitting element LD may be connected (e.g., electrically connected) to the cathode connection electrode CNEC. For example, the auxiliary electrode layer RELL may facilitate electrical connection between the first end portion EP1 of the light-emitting element LD and the cathode connection electrode CNEC.

[0138] Will refer to Figure 9 A light emitting element LD according to a sixth embodiment will be described. The features of the light emitting element LD according to the sixth embodiment will be described focusing on differences from the light emitting element LD of the first embodiment described above. For convenience of description, redundant descriptions similar to or identical to those of the above embodiments will be simplified or omitted.

[0139] Figure 9 is a schematic cross-sectional view showing a light emitting element LD according to a sixth embodiment.

[0140] The light emitting element LD according to the sixth embodiment is different from the light emitting element LD according to the first embodiment in that the first semiconductor layer SCL1 has a partial protruding portion.

[0141] For example, the first semiconductor layer SCL1 may include a body SCL1_B and a protrusion SCL1_A.

[0142] The body SCL1_B may be a portion of the first semiconductor layer SCL1 and overlap the first insulating layer INF1 and the second insulating layer INF2. The body SCL1_B may correspond to the entire structure of the first semiconductor layer SCL1 described above.

[0143] The protrusion SCL1_A may be a semiconductor layer formed (e.g., grown) on the body SCL1_B. The protrusion SCL1_A may have a shape in which at least a portion thereof protrudes. For example, the protrusion SCL1_A may have a tapered shape in which one region of the tapered shape protrudes significantly, but the embodiment is not limited thereto.

[0144] In an embodiment, the active layer AL, the second semiconductor layer SCL2 , and the electrode layer ELL may each have a shape corresponding to an outer shape of the protrusion SCL1_A.

[0145] The protrusion SCL1_A may be adjacent to the active layer AL. For example, the protrusion SCL1_A may be directly adjacent to the active layer AL. The active layer AL may have an active surface directly adjacent to the protrusion SCL1_A. For example, the adjacent surface area between the active layer AL and the first semiconductor layer SCL1 may be increased, thereby improving the emission efficiency of the light emitting element LD.

[0146] Will refer to Figures 10 to 12 A display device DD including a light emitting element LD according to an embodiment is described. For convenience of description, redundant descriptions similar to or the same as those of the above-described embodiment will be simplified or may be omitted.

[0147] Figure 10 is a schematic plan view showing a display device according to an embodiment.

[0148] The display device DD can emit light. The display device DD may include a light-emitting element LD. In embodiments, the display device DD may be configured in various shapes. For example, the display device DD may be applied to a smartphone, a notebook computer, a desktop personal computer (PC), a wearable device (e.g., a head-mounted device, a smartwatch, smart glasses), a television, or an in-vehicle infotainment system, and may also be applied to various other embodiments.

[0149] refer to Figure 10 The display device DD may include a base layer BSL and pixels PXL disposed on the base layer BSL. The display device DD may further include driving circuit components (eg, a scan driver and a data driver), lines, and pads configured to drive the pixels PXL.

[0150] The display device DD may include a display area DA and a non-display area NDA. The non-display area NDA may refer to an area other than the display area DA. The non-display area NDA may surround (or enclose) at least a portion of the display area DA.

[0151] The base layer BSL may form the substrate of the display device DD. The base layer BSL may be a rigid substrate or film or a flexible substrate or film. For example, the base layer BSL may be a rigid substrate made of glass or reinforced glass, a flexible substrate (or film) formed of plastic or metal, or at least one insulating layer. The material and / or properties of the base layer BSL are not limited. In an embodiment, the base layer BSL may be substantially transparent. For example, the term "substantially transparent" may mean that light can pass through the base layer BSL with a transmittance of a specific value or higher. In an embodiment, the base layer BSL may be translucent or opaque. In addition, the base layer BSL may include a reflective material.

[0152] The display area DA may refer to an area in which the pixels PXL are disposed. The non-display area NDA may refer to an area in which the pixels PXL are not disposed. Driving circuit components, lines, and pads connected to the pixels PXL in the display area DA may be disposed in the non-display area NDA.

[0153] In an embodiment, the pixels PXL (or sub-pixels SPX) may be arranged according to a stripe or PENTILE™ arrangement structure. However, the embodiment is not limited thereto.

[0154] In an embodiment, each pixel PXL may include a light-emitting element LD. A pixel PXL (or subpixel SPX) may include a first subpixel SPX1, a second subpixel SPX2, and a third subpixel SPX3. The at least one first subpixel SPX1, the at least one second subpixel SPX2, and the at least one third subpixel SPX3 may form a pixel unit PXU that may emit light of various colors.

[0155] For example, each of the first subpixel SPX1, the second subpixel SPX2, and the third subpixel SPX3 may emit light of a single color. For example, the first subpixel SPX1 may be a red pixel that emits red light (e.g., the first color), the second subpixel SPX2 may be a green pixel that emits green light (e.g., the second color), and the third subpixel SPX3 may be a blue pixel that emits blue light (e.g., the third color). The colors, types, and / or numbers of the first subpixels SPX1, the second subpixels SPX2, and the third subpixels SPX3 that form each pixel unit PXU are not limited to specific examples.

[0156] Figure 11 is a schematic cross-sectional view illustrating a display device according to an embodiment. Figure 11 A light emitting element layer EML in which the light emitting element LD is provided and a pixel circuit layer PCL including a pixel circuit are shown.

[0157] refer to Figure 11 , the display device DD may include a pixel circuit layer PCL and a light emitting element layer EML.

[0158] The pixel circuit layer PCL may be a layer including pixel circuits that drive the light-emitting elements LD. The pixel circuit layer PCL may include a base layer BSL, metal layers configured to form the pixel circuits, and insulating layers disposed between the metal layers. In an embodiment, the base layer BSL may form a base surface for supporting the display device DD.

[0159] In an embodiment, each of the pixel circuits may include a thin film transistor. Each pixel circuit may further include a storage capacitor. The pixel circuit may be connected (eg, electrically connected) to the light emitting element LD and may provide an electrical signal that controls the light emitting element LD to emit light.

[0160] The light emitting element layer EML may be disposed on the pixel circuit layer PCL and may include first and second insulating pattern layers INP1 and INP2, an alignment electrode layer ELT, a first insulating layer INS1, a bank BNK, a light emitting element LD, a second insulating layer INS2, and a connection electrode layer CNE.

[0161] The first insulating pattern layer INP1 and the second insulating pattern layer INP2 may be disposed on the passivation layer PSV. Each of the first insulating pattern layer INP1 and the second insulating pattern layer INP2 may have various shapes. In an embodiment, the first insulating pattern layer INP1 and the second insulating pattern layer INP2 may protrude in a thickness direction of the base layer BSL (e.g., in the third direction DR3).

[0162] The first insulating pattern layer INP1 and the second insulating pattern layer INP2 may form a stepped portion so that the light-emitting element LD can be easily aligned in the emission region. In an embodiment, each of the first insulating pattern layer INP1 and the second insulating pattern layer INP2 may be a partition wall (or wall). In an embodiment, each of the first insulating pattern layer INP1 and the second insulating pattern layer INP2 may include at least one organic material and / or inorganic material. However, embodiments are not limited to examples.

[0163] The alignment electrode layer ELT may include an electrode for aligning the light emitting element LD. In an embodiment, the alignment electrode layer ELT may include a first electrode ELTA and a second electrode ELTG. In an embodiment, the first electrode ELTA may be a first alignment electrode, and the second electrode ELTG may be a second alignment electrode.

[0164] The alignment electrode layer ELT may be disposed on the pixel circuit layer PCL. A portion of the alignment electrode layer ELT may be disposed on the first insulation pattern layer INP1 and the second insulation pattern layer INP2. The first electrode ELTA may be provided with a first alignment signal and / or a first power. The second electrode ELTG may be provided with a second alignment signal and / or a second power.

[0165] The first electrode ELTA may be an electrode to which an AC signal is supplied to align the light-emitting element LD. The first electrode ELTA may be an electrode to which an anode signal is supplied so that the light-emitting element LD can emit light. The second electrode ELTG may be an electrode to which a ground signal is supplied to align the light-emitting element LD. The second electrode ELTG may be an electrode to which a cathode signal is supplied so that the light-emitting element LD can emit light.

[0166] During the process of aligning the light-emitting element LD, a first alignment signal and a second alignment signal may be supplied (or provided) to the first electrode ELTA (or first alignment electrode) and the second electrode ELTG (or second alignment electrode), respectively. For example, ink containing the light-emitting element LD may be supplied (or provided), the first alignment signal may be supplied to the first electrode ELTA, and the second alignment signal may be supplied to the second electrode ELTG. For example, the first alignment signal and the second alignment signal may have different waveforms, different potentials, and / or different phases. For example, the first alignment signal may be an AC signal, and the second alignment signal may be a ground signal. However, embodiments are not limited thereto. An electric field may be formed between (or above) the first electrode ELTA and the second electrode ELTG, such that the light-emitting element LD can be aligned between the first electrode ELTA and the second electrode ELTG based on the electric field. For example, the light-emitting element LD may be moved (or rotated) by a force (e.g., dielectrophoresis (DEP) force) generated by the electric field, thereby aligning (or positioning) the light-emitting element LD on the first and second alignment electrodes.

[0167] The first insulating layer INS1 may be disposed on the alignment electrode layer ELT. For example, the first insulating layer INS1 may cover the first electrode ELTA and the second electrode ELTG.

[0168] The bank BNK may be provided on the first insulating layer INS1. The bank BNK may form a space in which the ink including the light emitting element LD is received. For example, the ink including the light emitting element LD may be supplied into the space defined by the bank BNK.

[0169] In an embodiment, the bank BNK may include an organic material such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, polyester resin, polyphenylene sulfide resin, or benzocyclobutene (BCB), but the embodiment is not limited thereto.

[0170] The light emitting elements LD may be disposed on the first insulating layer INS1 in a region surrounded by the bank BNK. In an embodiment, each of the light emitting elements LD may emit light based on electrical signals (eg, anode and cathode signals) provided from the anode and cathode connection electrodes CNEA and CNEC.

[0171] A second insulating layer INS2 may be disposed on the light-emitting elements LD. The second insulating layer INS2 may cover the active layer AL of each light-emitting element LD. The second insulating layer INS2 may expose at least a portion of the light-emitting element LD. For example, the second insulating layer INS2 may not cover the first and second end portions EP1, EP2 of the light-emitting element LD. Thus, the first and second end portions EP1, EP2 of the light-emitting element LD may be exposed and connected (e.g., electrically connected) to the anode connection electrode CNEA and the cathode connection electrode CNEC, respectively. In an embodiment, another portion of the second insulating layer INS2 may be disposed on the bank BNK and the first insulating layer INS1.

[0172] In the case where the second insulating layer INS2 is formed on the light emitting element LD after the alignment of the light emitting element LD has been completed, the light emitting element LD can be prevented from being moved from the aligned position.

[0173] The second insulating layer INS2 may have a single-layer structure or a multi-layer structure. The second insulating layer INS2 may include a material selected from silicon oxide (SiO x ), silicon nitride (SiN x ), silicon oxynitride (SiO x N y ), aluminum nitride (AlN x ), aluminum oxide (AlO x )、ZrO x ), hafnium oxide (HfO x ) and titanium oxide (TiO x However, the embodiment is not limited thereto.

[0174] An anode connection electrode CNEA and a cathode connection electrode CNEC may be disposed on the first and second insulating layers INS1 and INS2. The anode connection electrode CNEA may be connected (e.g., electrically connected) to the first end portion EP1 of the light emitting element LD. The cathode connection electrode CNEC may be connected (e.g., electrically connected) to the second end portion EP2 of the light emitting element LD.

[0175] The anode connection electrode CNEA may be connected (e.g., electrically connected) to the first electrode ELTA via a first contact CNT1 passing through the first insulating layer INS1. The cathode connection electrode CNEC may be connected (e.g., electrically connected) to the second electrode ELTG via a second contact CNT2 passing through the first insulating layer INS1. In embodiments, the anode connection electrode CNEA may be connected (e.g., directly or electrically connected) to a line of the pixel circuit layer PCL via the first contact CNT1. The cathode connection electrode CNEC may be connected (e.g., directly or electrically connected) to a line of the pixel circuit layer PCL via the second contact CNT2.

[0176] In an embodiment, the anode connection electrode CNEA and the cathode connection electrode CNEC may be patterned at the same time by the same process. However, the embodiment is not limited thereto. After patterning either the anode connection electrode CNEA or the cathode connection electrode CNEC, the other electrode may be patterned.

[0177] refer to Figure 12 , a structure in which the connection electrodes CNEA and CNEC are connected (eg, electrically connected) to the light emitting element LD will be described. Figure 12 is a schematic cross-sectional view showing the connection electrodes CNEA and CNEC and the light emitting element LD according to an embodiment.

[0178] In embodiments, the insulating layer INF of the light-emitting element LD may have a stepped portion. For example, the connection electrodes CNEA and CNEC provided on the light-emitting element LD may have a shape corresponding to the stepped portion. For example, the first stepped portion may be defined in the region between the active layer AL and the first semiconductor layer SCL1. Thus, a portion of the anode connection electrode CNEA may be bent in the region where the stepped portion is formed. In embodiments, the stepped portion may not be defined in the region where the first insulating layer INF1 and the second insulating layer INF2 overlap. Thus, a portion of the cathode connection electrode CNEC may not be bent on the light-emitting element LD.

[0179] The application field of the light emitting element LD according to the embodiment is not limited. For example, the light emitting element LD may be a micro light emitting diode (micro LED) transferred onto the base layer BSL using various transfer methods.

[0180] In the following, reference will be made to Figures 13 to 38 A method of manufacturing the light emitting element LD according to the embodiment is described. For convenience of description, redundant descriptions similar to or the same as those of the above-mentioned embodiment will be simplified or may be omitted.

[0181] Will refer to Figures 13 to 28 A method of manufacturing the light emitting element LD according to the first to fourth embodiments is described. Figures 13 to 28 Schematic diagram illustrating a method of manufacturing the light emitting element according to the first to fourth embodiments. Figures 14 to 19 First to fourth embodiments are shown. Figure 20 and Figure 23 A first embodiment is shown. Figure 21 and Figure 24 A second embodiment is shown. Figure 22 and Figure 25 A third embodiment is shown. Figure 26The steps of forming the electrode layer ELL according to the first to fourth embodiments are described focusing on the first embodiment. Figure 27 The steps of separating the light emitting elements LD according to the first to third embodiments are described focusing on the first embodiment. Figure 28 A step of separating the light emitting element LD according to the fourth embodiment is shown.

[0182] Figure 13 is a schematic flowchart illustrating a method of manufacturing a light emitting element LD according to one or more embodiments. Figure 14 、 Figure 15 as well as Figures 19 to 28 Schematic cross-sectional views illustrating a method of manufacturing the light emitting element LD according to one or more embodiments. Figures 16 to 18 are schematic plan views each illustrating a method of manufacturing the light emitting element LD according to the embodiment.

[0183] refer to Figure 13 The method of manufacturing a light emitting element LD according to one or more embodiments may include a step S100 of patterning a first semiconductor layer on a growth substrate, a step S200 of patterning a first insulating layer, a step S300 of forming an active layer and a second semiconductor layer, a step S400 of patterning a second insulating layer, a step S500 of patterning an electrode layer, and a step S600 of separating a semiconductor stack member.

[0184] refer to Figures 13 to 15 In the step S100 of patterning the first semiconductor layer on the growth substrate, an undoped semiconductor layer USCL and a base semiconductor layer BSCL may be formed (or disposed) on the growth substrate GS, and the first semiconductor layer SCL1 may be patterned by etching the base semiconductor layer BSCL.

[0185] The growth substrate GS may be a base plate configured to grow the target material. For example, the growth substrate GS may be a wafer used for epitaxial growth of the target material. The growth substrate GS may be a GaAs, GaP, or InP substrate, and the material used to form the growth substrate GS is not limited to the examples.

[0186] The undoped semiconductor layer USCL may be disposed on the buffer layer to minimize defects in the semiconductor formed on the growth substrate GS. In an embodiment, the undoped semiconductor layer USCL may include GaN without a separate dopant, but the material for forming the undoped semiconductor layer USCL is not limited to the example.

[0187] A base semiconductor layer BSCL may be epitaxially grown on the undoped semiconductor layer USCL. The base semiconductor layer BSCL may be a layer used to form the first semiconductor layer SCL1 and may include one or more of the aforementioned N-type semiconductor materials. In embodiments, the base semiconductor layer BSCL may be formed using a metal organic chemical vapor deposition (MOCVD) process, but embodiments are not limited thereto.

[0188] In step S100, an etching mask MAS may be formed on the base semiconductor layer BSCL, and the base semiconductor layer BSCL may be etched using the etching mask MAS, thereby patterning the first semiconductor layer SCL1. For example, the etching mask MAS may be formed by forming a plurality of layers (e.g., silicon oxide (SiO x ) layer and an aluminum layer) and then patterning the multiple layers to manufacture. In an embodiment, a nanoimprint process or a photolithography process may be performed, and the embodiment is not limited to one example.

[0189] In step S100 , an etched base semiconductor layer BSCL′ and first semiconductor layers SCL1 independently spaced apart from each other may be manufactured by etching the base semiconductor layer BSCL.

[0190] In step S100 , a dry etching process may be performed to pattern the first semiconductor layer SCL1 . Embodiments are not limited thereto. According to embodiments, a wet etching process may be performed.

[0191] After patterning the first semiconductor layer SCL1, the mask MAS may be removed by various processes. The process of removing the mask MAS is not limited to a specific process. For example, the mask MAS may be etched and removed using a solution including a buffered oxide etchant (BOE).

[0192] The cross section of each patterned first semiconductor layer SCL1 may have various shapes. The cross section of the patterned first semiconductor layer SCL1 may correspond to the cross section of the bottom surface of the light emitting element LD to be manufactured. For example, the cross section of the first semiconductor layer SCL1 may have a circular shape (refer to FIG. Figure 16 In another example, the cross section of the first semiconductor layer SCL1 may have a rectangular shape (refer to Figure 17 In another example, the cross section of the first semiconductor layer SCL1 may have a hexagonal shape (refer to Figure 18 ). However, the embodiment is not limited thereto.

[0193] In an embodiment, an etching process for forming the first semiconductor layer SCL1 may be performed while the upper surface (e.g., at least a portion of the upper surface) of the base semiconductor layer BSCL is exposed. For example, the etching process for the first semiconductor layer SCL1 may be performed before etching the active layer AL and the second semiconductor layer SCL2. For example, when etching the first semiconductor layer SCL1, a structure for individually defining the light emitting element LD may be formed.

[0194] refer to Figure 13 and Figure 19 In the step S200 of patterning the first insulating layer, the first insulating layer INF1 may be patterned on the side surface of the first semiconductor layer SCL1.

[0195] In step S200, to form the first insulating layer INF1, an insulating layer may be deposited, and then the deposited insulating layer may be etched to expose the upper surface of the first semiconductor layer SCL1. In an embodiment, the insulating layer used to form the first insulating layer INF1 may be formed by a chemical vapor deposition (CVD) method or an atomic layer deposition (ALD) method. However, the embodiment is not limited thereto.

[0196] In operation S200 , a dry etching process may be performed to pattern the first insulating layer INF1 . Thus, the side surface of the first semiconductor layer SCL1 may be covered with the first insulating layer INF1 , and the upper surface of the first semiconductor layer SCL1 may be exposed.

[0197] refer to Figure 13 as well as Figures 20 to 22 In step S300 of forming the active layer and the second semiconductor layer, the active layer AL and the second semiconductor layer SCL2 may be formed (or disposed) on the upper surface of the first semiconductor layer SCL1. Thus, a semiconductor stack member ESS including the first semiconductor layer SCL1, the active layer AL, and the second semiconductor layer SCL2 may be manufactured.

[0198] In step S300, an active layer AL and a second semiconductor layer SCL2 may be grown on the upper surface of the first semiconductor layer SCL1 exposed from the first insulating layer INF1. The active layer AL and the second semiconductor layer SCL2 may be formed by a metal organic chemical vapor deposition (MOCVD) process, but the embodiment is not limited thereto.

[0199] In step S300, according to an embodiment, when the active layer AL and the second semiconductor layer SCL2 are formed, corresponding layers may be formed on the exposed etched base semiconductor layer BSCL'. The lower active layer AL' and the lower second semiconductor layer SCL2' may be grown in the region between the first semiconductor layers SCL1 spaced apart from each other.

[0200] For example, the lower active layer AL' and the lower second semiconductor layer SCL2' may be interposed between the first insulating layers INF1 adjacent to each other. The lower active layer AL' and the lower second semiconductor layer SCL2' may be grown on the exposed etched base semiconductor layer BSCL'.

[0201] In an embodiment, quantum barrier layers BL and quantum well layers WL may be alternately grown to form an active layer AL. In an embodiment, since the quantum barrier layers BL and quantum well layers WL are grown on the upper surface of the first semiconductor layer SCL1, the etching process for separately manufacturing the active layer AL may be omitted for convenience of description.

[0202] For example, the active layer AL and the second semiconductor layer SCL2 according to embodiments can be manufactured without performing an etching process. For example, during the process of forming (e.g., growing) the active layer AL and the second semiconductor layer SCL2, the active layer AL and the second semiconductor layer SCL2 can be patterned separately. As described above, during the etching process for the active layer AL, there may be structural risks, such as defects in the active layer AL. For example, emission efficiency may be reduced. However, in embodiments, since the active layer AL is manufactured without performing an etching process, the light-emitting element LD according to embodiments can have excellent emission efficiency.

[0203] In step S300, in order to manufacture the first embodiment (eg, Figures 1 to 3 In the light emitting element LD of the embodiment of the present invention, the active layer AL and the second semiconductor layer SCL2 may be grown so that (for example, in the lateral direction (or width direction)) the cross-sectional area (or cross-sectional size) thereof may be substantially the same as the cross-sectional area (or cross-sectional size) of the first semiconductor layer SCL1 (refer to Figure 20 In an embodiment, the active layer AL and the second semiconductor layer SCL2 may be grown to correspond to the surface area of the exposed upper surface of the first semiconductor layer SCL1.

[0204] In step S300, in order to manufacture the device according to the second embodiment (eg, Figure 4 and Figure 5 In the light emitting element LD of the embodiment of the present invention, the active layer AL and the second semiconductor layer SCL2 may be grown so that (for example, in the lateral direction (or width direction)) their cross-sectional area may be larger than that of the first semiconductor layer SCL1 (refer to Figure 21 In step S300 , since the active layer AL has a larger cross-sectional area than the first semiconductor layer SCL1 , the active layer AL may cover the entire upper surface of the first semiconductor layer SCL1 . In an embodiment, the grown active layer AL may cover a portion of the first semiconductor layer SCL1 .

[0205] In step S300, in order to manufacture the device according to the third embodiment (for example, Figure 6 In the light emitting element LD of the embodiment of the present invention, the active layer AL and the second semiconductor layer SCL2 may be grown so that the cross-sectional area thereof increases from the bottom to the top (refer to Figure 22 ).

[0206] refer to Figure 13 as well as Figures 23 to 25 In the step S400 of patterning the second insulating layer, the second insulating layer INF2 may be patterned on the side surface of the semiconductor stack member ESS.

[0207] In step S400, in order to form the second insulating layer INF2, an insulating layer may be deposited, and then the deposited insulating layer may be etched to expose the upper surface of the second semiconductor layer SCL2. In an embodiment, the insulating layer for forming the second insulating layer INF2 may be formed by a CVD method or an ALD method. However, the embodiment is not limited thereto.

[0208] In step S400 , a portion of the second insulating layer INF2 may contact the first insulating layer INF1 , and another portion of the second insulating layer INF2 may contact the active layer AL and the second semiconductor layer SCL2 .

[0209] In step S400, a dry etching process may be performed to pattern the second insulating layer INF2. Thus, the side surfaces of the first semiconductor layer SCL1 and the first insulating layer INF1 may be covered by the second insulating layer INF2. The side surfaces of the active layer AL and the second semiconductor layer SCL2 may be covered by the second insulating layer INF2. The upper surface of the second semiconductor layer SCL2 may be exposed.

[0210] Figure 23 The structure in which the second insulating layer INF2 is formed to manufacture the light emitting element LD according to the first embodiment is shown. For example, the second insulating layer INF2 can be manufactured to cover the respective side surfaces of the active layer AL and the second semiconductor layer SCL2, and the active layer AL and the second semiconductor layer SCL2 have substantially uniform cross-sectional areas.

[0211] Figure 24 The structure in which the second insulating layer INF2 is formed to manufacture the light emitting element LD according to the second embodiment is shown. For example, the second insulating layer INF2 can be manufactured to cover the respective side surfaces of the active layer AL and the second semiconductor layer SCL2, and the cross-sectional area of the active layer AL and the second semiconductor layer SCL2 is larger than the cross-sectional area of the first semiconductor layer SCL1.

[0212] Figure 25The structure in which the second insulating layer INF2 is formed to manufacture the light emitting element LD according to the third embodiment is shown. For example, the second insulating layer INF2 can be manufactured to cover the respective side surfaces of the active layer AL and the second semiconductor layer SCL2, each of which has a truncated shape.

[0213] refer to Figure 13 and Figure 26 In the step S500 of patterning the electrode layer, the electrode layer ELL may be patterned on the exposed upper surface of the second semiconductor layer SCL2.

[0214] In step S500, in order to form the electrode layer ELL, a base electrode layer may be deposited, and thereafter the electrode layer ELL may be patterned by etching the deposited base electrode layer. In an embodiment, the base electrode layer may be formed by a sputtering method. However, the embodiment is not limited thereto.

[0215] In operation S500 , the electrode layer ELL may be connected (eg, electrically connected) to the second semiconductor layer SCL2 , and the insulating layer INF may be exposed.

[0216] refer to Figure 13 、 Figure 27 and Figure 28 In the step S600 of separating the semiconductor stack members, the light emitting elements LD provided individually can be manufactured by separating the semiconductor stack members ESS spaced apart from each other. For example, each of the light emitting elements LD can be manufactured to include a semiconductor stack member ESS, an insulating layer INF, and an electrode layer ELL. In an embodiment, the light emitting element LD can be manufactured to further include an auxiliary semiconductor layer RSCL.

[0217] In step S600 , the light emitting elements LD may be individually separated by cutting corresponding portions of the first semiconductor layer SCL1 . For example, lines along which the semiconductor stack members ESS are individually separated may be defined in the first semiconductor layer SCL1 .

[0218] In step S600, depending on the embodiment, the light-emitting elements LD may be individually separated by applying an external physical force thereto. For example, ultrasonic waves may be applied to the light-emitting elements LD to separate the respective lower portions of the light-emitting elements LD, thereby providing the light-emitting elements LD individually. As another example, a laser lift-off process, a thermal process, or the like may be performed to separate the light-emitting elements LD. However, the embodiment is not limited thereto, and various processes may be applied.

[0219] In embodiments, the line along which the light-emitting elements LD are separated may be defined at a position corresponding to the height of the lower second semiconductor layer SCL2'. For example, the separation line defined in the first semiconductor layer SCL1 may be determined (or defined) at a position equal to or higher than the uppermost surface of the lower second semiconductor layer SCL2'. Thus, the outer surface of the second insulating layer INF2 may be exposed, and a structure of the insulating layer INF capable of electrically separating the light-emitting elements LD from each other may be formed, thereby providing the light-emitting elements LD according to embodiments.

[0220] refer to Figure 28 In an embodiment, the line along which the light emitting element LD is separated may overlap a portion of the lower second semiconductor layer SCL2 ′. For example, the light emitting element LD according to the fourth embodiment may be manufactured.

[0221] In an embodiment, the position of the light emitting element LD along the line of separation thereof may be defined to overlap a portion of the lower second semiconductor layer SCL2 ′. A layer including the same material as the second semiconductor layer SCL2 may be provided on a portion of the insulating layer INF (e.g., the second insulating layer INF2) of the manufactured light emitting element LD.

[0222] For example, at least a portion of the lower second semiconductor layer SCL2' may remain on at least a portion of the lower portion of the first insulating layer INF1 of the light emitting element LD, thereby forming an auxiliary semiconductor layer RSCL covering the first insulating layer INF1 in the same manner as the second insulating layer INF2 and including a P-type semiconductor material.

[0223] Will refer to Figures 28 to 32 A method of manufacturing the light emitting element LD according to the fifth embodiment is described. For convenience of description, redundant descriptions similar to or the same as those of the above-described embodiments will be simplified or may be omitted.

[0224] Figures 29 to 32 : is a schematic diagram illustrating a method of manufacturing the light emitting element LD according to the fifth embodiment.

[0225] Figure 29 is a schematic flowchart illustrating a method of manufacturing the light emitting element LD according to the fifth embodiment. Figures 30 to 32 is a schematic cross-sectional view illustrating a method of manufacturing the light emitting element LD according to the fifth embodiment.

[0226] In the embodiment, the method of manufacturing the light emitting element LD according to the fifth embodiment is different from the method of manufacturing the light emitting element LD according to one or more of the above embodiments in that the electrode layer ELL is manufactured before the second insulating layer INF2 is formed.

[0227] For example, reference Figure 29The method for manufacturing the light emitting element LD according to the embodiment may include a step S100 of patterning a first semiconductor layer on a growth substrate, a step S200 of patterning a first insulating layer, a step S300 of forming an active layer and a second semiconductor layer, a step S420 of patterning an electrode layer, a step S520 of patterning a second insulating layer, and a step S600 of separating a semiconductor stack member.

[0228] refer to Figure 30 In the step S300 of forming the active layer and the second semiconductor layer and in the step S420 of patterning the electrode layer, the active layer AL, the lower active layer AL', the second semiconductor layer SCL2 and the lower second semiconductor layer SCL2' can be grown on the patterned first semiconductor layer SCL1, and thereafter, the electrode layer ELL and the lower electrode layer ELL' can be patterned.

[0229] The electrode layer ELL and the lower electrode layer ELL' can be formed by the same process. For example, after depositing a base electrode for forming the electrode layer ELL and the lower electrode layer ELL', the electrode layer ELL and the lower electrode layer ELL' can be manufactured by etching the deposited base electrode.

[0230] In an embodiment, the lower electrode layer ELL′ may be disposed on the lower second semiconductor layer SCL2 ′, and the electrode layer ELL may be disposed on the second semiconductor layer SCL2 .

[0231] refer to Figure 31 In the step S520 of patterning the second insulating layer, the second insulating layer INF2 may be patterned on the side surface of the semiconductor stack member ESS.

[0232] In step S520, the second insulating layer INF2 may expose the electrode layer ELL. In an embodiment, a portion of the second insulating layer INF2 may cover a side surface of the electrode layer ELL. In an embodiment, a portion of the second insulating layer INF2 may contact a portion of the lower electrode layer ELL'.

[0233] refer to Figure 32 In the step S600 of separating the semiconductor stack members, individually provided light emitting elements LD may be manufactured by separating the semiconductor stack members ESS spaced apart from each other.

[0234] In step S600, the line along which the light emitting element LD is separated may overlap with a portion of the lower electrode layer ELL′ For example, the light emitting element LD according to the fifth embodiment may be manufactured.

[0235] In an embodiment, the position of the light emitting element LD along the line of separation thereof may be defined to overlap a portion of the lower second semiconductor layer SCL2'. The same material as the electrode layer ELL may be provided on a portion of the insulating layer INF (eg, the second insulating layer INF2) of the manufactured light emitting element LD.

[0236] For example, at least a portion of the lower electrode layer ELL' may remain on at least a portion of the lower portion of the first insulating layer INF1 of the light emitting element LD, thereby forming an auxiliary electrode layer RELL covering the first insulating layer INF1 in the same manner as the second insulating layer INF2 and including a conductive material.

[0237] Will refer to Figures 33 to 38 A method of manufacturing the light emitting element LD according to the sixth embodiment is described. For convenience of description, redundant descriptions similar to or the same as those of the above-described embodiments will be simplified or may be omitted.

[0238] Figures 33 to 38 : is a schematic diagram illustrating a method of manufacturing the light emitting element LD according to the sixth embodiment.

[0239] Figure 33 is a schematic flowchart illustrating a method of manufacturing the light emitting element LD according to the sixth embodiment. Figures 34 to 38 is a schematic cross-sectional view illustrating a method of manufacturing the light emitting element LD according to the sixth embodiment.

[0240] In an embodiment, the method of manufacturing the light emitting element LD according to the sixth embodiment is different from the method of manufacturing the light emitting element LD according to one or more of the above embodiments in that step S250 of forming an additional first semiconductor layer is further performed.

[0241] For example, reference Figure 33 The method for manufacturing the light emitting element LD according to the embodiment may include a step S100 of patterning a first semiconductor layer on a growth substrate, a step S200 of patterning a first insulating layer, a step S250 of forming an additional first semiconductor layer, a step S300 of forming an active layer and a second semiconductor layer, a step S400 of patterning a second insulating layer, a step S500 of patterning an electrode layer, and a step S600 of separating a semiconductor stack member.

[0242] For example, in the method of manufacturing the light emitting element LD according to the embodiment, the step S250 of forming the additional first semiconductor layer may be performed after the step S100 of patterning the first semiconductor layer and the step S200 of patterning the first insulating layer are performed.

[0243] The additional first semiconductor layer SCL1_A may correspond to the above-described protrusion SCL1_A.

[0244] refer to Figure 33 and Figure 34 , an additional first semiconductor layer SCL1_A may be grown on the upper surface of the first semiconductor layer SCL1 exposed from the first insulating layer INF1.

[0245] In step S250 , since the additional first semiconductor layer SCL1_A has a shape in which at least a portion thereof protrudes, an exposed surface of the additional first semiconductor layer SCL1_A may have a surface area (or surface size) larger than that of the upper surface of the previously patterned first semiconductor layer SCL1 .

[0246] In step S250 , a first additional semiconductor layer ASCL′ may be grown on the etched base semiconductor layer BSCL′.

[0247] refer to Figure 33 and Figure 35 , after growing the additional first semiconductor layer SCL1_A, the active layer AL and the second semiconductor layer SCL2 may be grown.

[0248] In step S300, an active layer AL and a second semiconductor layer SCL2 may be grown on the exposed additional first semiconductor layer SCL1_A. Therefore, a surface area between the active layer AL and the additional first semiconductor layer SCL1_A and a surface area between the active layer AL and the second semiconductor layer SCL2 may each be larger than a surface area of the upper surface of the first semiconductor layer SCL1.

[0249] In step S300 , a lower active layer AL′ and a lower second semiconductor layer SCL2 ′ may be grown on the lower additional first semiconductor layer ASCL′.

[0250] refer to Figure 33 and Figure 36 In the step S400 of patterning the second insulating layer, the second insulating layer INF2 may be patterned to cover the side surfaces of the first insulating layer INF1. In step S400, the second insulating layer INF2 may cover the side surfaces of the semiconductor stack member ESS and may expose the outer surface of the second semiconductor layer SCL2. For example, a portion of the second insulating layer INF2 may cover the surface of the second semiconductor layer SCL2.

[0251] refer to Figure 33 and Figure 37 In the step S500 of patterning the electrode layer, the electrode layer ELL may be patterned on the exposed second semiconductor layer SCL2. In the step S500, the electrode layer ELL may have a shape corresponding to the shape of the additional first semiconductor layer SCL1_A.

[0252] refer to Figure 33 and Figure 38 In the step S600 of separating the semiconductor stacked member, a portion of each of the first semiconductor layer SCL1 and the insulating layer INF may be cut, thereby providing individually separated light-emitting elements LD. For example, the light-emitting elements LD may be separated along separation lines. Thus, the light-emitting elements LD according to the sixth embodiment may be manufactured.

[0253] At the end of the detailed description, it will be appreciated by those skilled in the art that many changes and modifications may be made to the embodiments without departing substantially from the principles, spirit and scope of the present disclosure. Therefore, the disclosed embodiments are used in a generic and descriptive sense only and not for purposes of limitation.

Claims

1. A method for manufacturing a light-emitting element, the method comprising: patterning a first semiconductor layer on a substrate; patterning a first insulating layer on a side surface of the first semiconductor layer; as well as An active layer and a second semiconductor layer are formed on the first semiconductor layer.

2. The method according to claim 1, wherein Patterning the first semiconductor layer includes: forming a base semiconductor layer on the substrate; and At least a portion of the base semiconductor layer is etched by using a mask exposing an upper surface of the base semiconductor layer.

3. The method according to claim 2, wherein: Patterning the first semiconductor layer and forming the second semiconductor layer are performed in separate processes.

4. The method according to claim 2, wherein: forming the active layer and the second semiconductor layer comprises depositing the active layer and the second semiconductor layer, and Depositing the active layer and the second semiconductor layer includes separately patterning the active layer and the second semiconductor layer.

5. The method according to claim 1, wherein Patterning the first insulating layer includes exposing an upper surface of the first semiconductor layer from the first insulating layer.

6. The method according to claim 5, wherein: Forming the active layer and the second semiconductor layer includes growing the active layer and the second semiconductor layer on the exposed upper surface of the first semiconductor layer.

7. The method according to claim 6, wherein: The first insulating layer covers the side surface of the first semiconductor layer so that the active layer and the second semiconductor layer are not grown on the side surface of the first semiconductor layer.

8. The method according to claim 1, further comprising: patterning the second insulating layer, Wherein, patterning the second insulating layer includes: disposing a first portion of the second insulating layer on the first insulating layer; and A second portion of the second insulating layer is disposed on a side surface of the active layer and a side surface of the second semiconductor layer.

9. The method according to claim 8, further comprising: After patterning the second insulating layer, an electrode layer is patterned on the second semiconductor layer.

10. The method according to claim 1, wherein The first semiconductor layer, the active layer, and the second semiconductor layer form a semiconductor stack member. The first semiconductor layer includes first semiconductor layers adjacent to each other, The method further comprises: forming a lower active layer and a lower second semiconductor layer between the first semiconductor layers adjacent to each other while forming the active layer and the second semiconductor layer; and separating the semiconductor stack structure from the substrate, separating the semiconductor stack member includes individually separating the semiconductor stack member along a separation line that is a portion of the first semiconductor layer, and The separation line is defined at a position substantially equal to or higher than an uppermost surface of the lower second semiconductor layer.

11. The method according to claim 1 , further comprising: An additional first semiconductor layer is formed on the first semiconductor layer.

12. The method according to claim 11, further comprising: forming the active layer and the second semiconductor layer on the additional first semiconductor layer, and The surface area of the upper surface of the first semiconductor layer on which the additional first semiconductor layer is grown is smaller than the surface area of the adjacent surface between the additional first semiconductor layer and the active layer.

13. Light-emitting element, comprising: A semiconductor stack structure comprising: a first semiconductor layer, a second semiconductor layer, and an active layer disposed between the first semiconductor layer and the second semiconductor layer; and an insulating layer disposed on a side surface of the semiconductor stack member, wherein The insulating layer comprises: a first insulating layer disposed on a side surface of the first semiconductor layer and exposing a side surface of the active layer or a side surface of the second semiconductor layer, and a second insulating layer disposed on the side surface of the semiconductor stack member, and The second insulating layer includes: a first portion that does not contact the first semiconductor layer with the first insulating layer interposed between the first portion and the first semiconductor layer, and The second portion contacts the active layer and the second semiconductor layer.

14. The light-emitting element according to claim 13, wherein The active layer comprises: a quantum well layer including a first side surface, and a quantum barrier layer including a second side surface, and The first side surface and the second side surface form a flat plane.

15. The light-emitting element according to claim 14, wherein The first side surface and the second side surface form a side surface without any recessed portion.

16. The light-emitting element according to claim 13, wherein The second insulating layer forms a stepped portion in a region between the first portion and the second portion of the second insulating layer.

17. The light-emitting element according to claim 16, wherein The insulating layer has a first thickness in a region overlapping with the first semiconductor layer, and has a second thickness smaller than the first thickness in a region overlapping with the active layer.

18. The light-emitting element according to claim 16, wherein The first insulating layer does not cover the side surfaces of the active layer and the second semiconductor layer.

19. The light-emitting element according to claim 13, wherein The active layer and the first semiconductor layer have the same cross-sectional size.

20. The light-emitting element according to claim 13, wherein The active layer includes an active surface facing the first semiconductor layer, and The active surface completely covers the first semiconductor layer and includes a portion of the active surface that does not contact the first semiconductor layer.

21. The light-emitting element according to claim 13, wherein The active layer has a truncated shape.

22. The light-emitting element according to claim 13, wherein The first semiconductor layer includes: a main body overlapping the first insulating layer and the second insulating layer, and A protrusion protrudes from the main body.

23. The light-emitting element according to claim 13, further comprising: a first end portion, adjacent to the first semiconductor layer, a second end portion adjacent to the second semiconductor layer, and An auxiliary semiconductor layer is provided on the first insulating layer in a region adjacent to the first end portion and includes a material substantially the same as that of the second semiconductor layer.

24. The light-emitting element according to claim 13, further comprising: a first end portion, adjacent to the first semiconductor layer, a second end portion, adjacent to the second semiconductor layer, an electrode layer disposed on the second semiconductor layer, and An auxiliary electrode layer is provided on the first insulating layer in a region adjacent to the first end portion and includes a material substantially the same as that of the electrode layer.

25. Display devices, including: base layer; as well as a light emitting element layer provided on the base layer and comprising the light emitting element according to claim 13, wherein: The light emitting element layer includes: a first electrode and a second electrode spaced apart from each other; and an anode connection electrode electrically connected to the first end portion of the light emitting element, and a cathode connection electrode electrically connected to the second end portion of the light emitting element, and The light emitting element is aligned between the first electrode and the second electrode.

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