A Single-Core Cable Logging Encoding Method Based on FPGA

Abstract

This invention provides an FPGA-based encoding method for single-core cable logging, comprising: detecting whether the edge of the original transmitted signal changes; if the edge of the original transmitted signal changes, encoding the original transmitted signal using two pulse signals to obtain a final output signal in which positive and negative levels cancel each other out. This invention uses an FPGA module and an external driving circuit in synergy to encode the original transmitted signal, resulting in a final output signal in which positive and negative levels cancel each other out. This invention effectively avoids baseline drift-induced glitches that interfere with the signal and affect data accuracy, thus solving the problem of level fluctuations affecting the signal in single-core cable transmission for oil logging.

Description

Technical Field

[0001] This invention belongs to the field of oil well logging signal processing technology, specifically relating to a single-core cable logging encoding method based on FPGA. Background Technology

[0002] Oil well logging uses single-core cables to transmit data. The single-core cable handles both power supply and signal transmission. The reason for using single-core cables for well logging data is:

[0003] ① Reduce signal transmission errors. Well logging depths can reach 4000-7000m. Using multi-core cables can cause differences in reactance between different cores, electromagnetic coupling interference between adjacent cores, and transmission delays, leading to inconsistencies and measurement errors. Single-core cables transmit data through a single path, effectively avoiding these issues.

[0004] ② Structural dimensions and installation requirements. Due to the often strict limitations on the dimensions of oil well tubing, wellhead, and instruments (e.g., outer diameter not exceeding 42mm), the slender design of single-core cables makes them more suitable for in-well use, satisfying space constraints while reducing access difficulty and installation risks. Single-core cables generally have a simple structure, reducing inconsistencies caused by vibration and minor bending between different cores in multi-core cables, thereby improving the long-term reliability and stability of the overall system.

[0005] ③ Environmental adaptability and system redundancy. In harsh environments such as deep wells, the effects of high temperature, high pressure, and chemical media (corrosive liquids in oil wells) must also be considered. Single-core cables can typically adapt to these environments and ensure long-term stable transmission by optimizing the design of the outer sheath and insulation materials. Multi-core cables may increase the risk of additional failures in connectors and wiring, while the single-core design simplifies the overall wiring structure, reduces the number of connection points, and reduces inconsistencies in logging data caused by poor contact or connector failure.

[0006] Because single-core cable transmission requires consideration of interference suppression measures, any glitches in the power signal can significantly affect the signal. To eliminate this effect, refer to... Figure 1 As shown, existing technologies use FPGA chips or microcontrollers in conjunction with peripheral modules to encode the high-level portion of the original transmitted signal into high and low levels using AMI code encoding. However, there may be instances where the overall power signal cannot be completely canceled out, leading to baseline drift. Summary of the Invention

[0007] To address the aforementioned problems in the existing technology, this invention provides a single-core cable logging coding method based on FPGA. The technical problem to be solved by this invention is achieved through the following technical solution:

[0008] An FPGA-based single-core cable logging coding method includes:

[0009] Detect whether the edges of the original transmitted signal change;

[0010] If the edge of the original transmitted signal changes, the original transmitted signal is encoded by two pulse signals to obtain a final output signal in which the positive and negative levels cancel each other out.

[0011] Beneficial effects:

[0012] This invention provides an FPGA-based encoding method for single-core cable logging, comprising: detecting whether the edge of the original transmitted signal changes; if the edge of the original transmitted signal changes, encoding the original transmitted signal using two pulse signals to obtain a final output signal in which positive and negative levels cancel each other out. This invention uses an FPGA module in conjunction with an external driving circuit to encode the original transmitted signal, thus obtaining a final output signal in which positive and negative levels cancel each other out. This invention effectively avoids interference caused by baseline drift glitches, which affect the accuracy of the data, and solves the problem of signal interference caused by level fluctuations in single-core cable transmission during oil logging.

[0013] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description

[0014] Figure 1 This is a schematic diagram of the original waveform of the original transmitted signal in the prior art and the AMI code waveform obtained after AMI encoding;

[0015] Figure 2 This is a flowchart illustrating a single-core cable logging coding method based on FPGA provided by the present invention.

[0016] Figure 3 This is a comparison diagram of the original transmitted signal waveform and the final transmitted signal waveform provided by the present invention;

[0017] Figure 4 This is a schematic diagram of the FPGA-based single-core cable logging encoding circuit provided by the present invention;

[0018] Figure 5 This is a schematic diagram of the detection process of the FPGA module provided by the present invention. Detailed Implementation

[0019] The present invention will be further described in detail below with reference to specific embodiments, but the implementation of the present invention is not limited thereto.

[0020] like Figure 2 As shown, this invention provides a single-core cable logging coding method based on FPGA, including:

[0021] S100, detects whether the edge of the original transmitted signal changes;

[0022] S200, if the edge of the original transmitted signal changes, the original transmitted signal is encoded by two pulse signals to obtain a final output signal in which the positive and negative levels cancel each other out.

[0023] The FPGA-based single-core cable logging encoding method of this invention utilizes an FPGA-based single-core cable logging encoding circuit to encode the original transmitted signal to obtain the final output signal. For example... Figure 2 As shown, the FPGA-based single-core cable logging encoding circuit includes an FPGA module and a driving circuit; wherein, the FPGA module takes into account the original transmission signal, the system clock signal and the asynchronous reset signal, and outputs two pulse signals; the driving circuit, under the control of the two pulse signals, outputs a final output signal in which the positive and negative levels cancel each other out.

[0024] refer to Figure 3 As shown, Figure 3 The original waveform above is the waveform of the original transmitted signal. The processed waveform below is the waveform of the final output signal obtained by processing the original transmitted signal using the method of this application. As can be seen from the figure, the positive and negative levels cancel each other out in the waveform processed by the scheme of this application.

[0025] The FPGA module is used to detect whether the edge of the original transmitted signal changes. If so, it generates two pulse signals, pos and neg, and outputs V. POS and V NEG , where V POS =3V, V NEG =0V, conversely, V POS =0V,V NEG =3V, the pulse signal neg is the pulse signal generated within the same clock cycle when the edge change of the original transmitted signal in is detected, and the pulse signal pos is the pulse signal generated in the next clock cycle in response to the delayed edge change.

[0026] The FPGA outputs two signals, neg and pos, corresponding to the output V. POS and V NEG This can be determined using Verilog coding. The specific coding logic is as follows:

[0027] (1) The main function of the FPGA module is to convert the edge changes of the input signal in (original transmission signal) into a pair of continuous pulse signals for output, so as to facilitate subsequent circuit triggering.

[0028] (2) Input system clock signal clk, asynchronous reset signal rst (active low), and input signal in.

[0029] The FPGA outputs two signals, `neg` and `pos`. `neg` is the pulse signal generated within the same clock cycle when the `in` edge change is detected, and `pos` is the pulse signal generated in the next clock cycle in response to the delayed edge change. That is, when `neg` is 1, the output is V. NEG =3V; when neg is 0, the output is V NEG =0V. When pos is 1, the output is V. POS =3V; when pos is 0, the output is V. POS =0V.

[0030] like Figure 2 As shown, the driving circuit includes resistors R1-R4, a differential amplifier U1, and transistors N1-N2; wherein, the first terminal of resistor R1 receives V. NEG The second terminal is connected to the negative input terminal of the differential amplifier and the first terminal of resistor R4; the first terminal of resistor R2 receives V. POS The second terminal is connected to the positive input terminal of the differential amplifier and the first terminal of resistor R3. The second terminal of resistor R3 is connected to the power supply V. SS The second end of resistor R4 is connected to the emitter of transistors N1 and N2. The output of the differential amplifier is connected to the base of transistors N1 and N2. The collector of transistor N1 is connected to a +15V voltage, and the collector of transistor N2 is connected to a -15V voltage. The source output levels of transistors N1 and N2 cancel each other out, resulting in the final output signal.

[0031] The subsequent transistor drive circuit of this invention ensures that the amplifier output signal can reach the required voltage level and has sufficient load capacity.

[0032] The FPGA module of the present invention includes two registers, namely in_prev and delay_flag;

[0033] The register in_prev stores the state of the original transmitted signal in sampled in the previous clock cycle, so as to compare it with the original transmitted signal in the current clock cycle to determine whether an edge change has occurred; the register delay_flag stores the delay control flag. When an input edge change is detected, the delay control flag is set so that a pulse signal pos is generated in the next clock cycle, and the delay control flag is cleared after generation.

[0034] When the asynchronous reset signal is applied, the FPGA module clears both the in_prev and delay_flag registers and the two pulse signals to zero, thus completing the reset. After the reset, it enters the initial state, waits for the original transmission signal to arrive, and detects whether the edge has changed.

[0035] It is worth noting that after the FPGA module of the present invention is reset, that is, when the asynchronous reset signal rst is high, whenever the rising edge of the system clock signal clk arrives, the FPGA module sequentially updates the sampling state, clears the pulse output, detects the delay control flag, and detects edge changes to obtain the detection result of whether the edge of the original transmitted signal has changed.

[0036] The update sampling state includes: storing the original transmitted signal of the current clock cycle into the register in_prev for comparison and detection in the next clock cycle;

[0037] Clearing the pulse output involves resetting the pulse signals neg and pos to 0, ensuring that pulses are not generated incorrectly when no trigger condition is met.

[0038] The detection of delay control flags includes checking the state of the delay_flag register: if the delay_flag register is 1, it indicates that the detection result is that an edge change of the original transmitted signal was detected in the previous clock cycle and a delay pulse was predetermined. In this case, the pulse signal pos is set to 1, and a delay pulse is generated in the current cycle, corresponding to the output V. POS And immediately clear the delay_flag;

[0039] Edge detection includes: when the delay_flag register is not activated, detecting whether the edge of the original transmitted signal has changed (i.e., comparing the current in with the previously stored in_prev); if a change is found (whether it is a rising edge or a falling edge), a pulse signal neg is output; setting the pulse signal neg to 1 corresponds to outputting V. NEG Simultaneously set the delay control flag by setting the delay_flag register to 1, thereby triggering the generation of the pos pulse signal in the next clock cycle.

[0040] See Figure 5 The FPGA module detects whether the edge of the input signal in changes. If it does, the two pulse signals output by the FPGA module cause V to change. POS =0V and V NEG =3V, When R1=R2 and R3=R4, V O =R4 / R1×(V POS -V NEG Therefore, the final output voltage VO =50 / 10×(0-3)=-15V;V POS =3V and V NEG =0V, the final output signal voltage V O =50 / 10×(3-0)=+15V; if it does not change, then V POS =0V and V NEG =0V, the final output signal voltage V O =0V.

[0041] Although this application has been described herein in conjunction with various embodiments, those skilled in the art will understand and implement other variations of the disclosed embodiments by reviewing the accompanying drawings, the disclosure, and the appended claims in carrying out the claimed application. In the claims, the word "comprising" does not exclude other components or steps, and "a" or "an" does not exclude a plurality.

[0042] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.

Claims

1. A single-core cable logging coding method based on FPGA, characterized in that, include: Detect whether the edges of the original transmitted signal change; If the edge of the original transmitted signal changes, the original transmitted signal is encoded by two pulse signals to obtain a final output signal in which the positive and negative levels cancel each other out. The FPGA-based single-core cable logging encoding method uses an FPGA-based single-core cable logging encoding circuit to encode the original transmitted signal to obtain the final output signal. The FPGA-based single-core cable logging encoding circuit includes an FPGA module and a driving circuit. The FPGA module takes into account the original transmission signal, the system clock signal, and the asynchronous reset signal, and outputs two pulse signals. Under the control of the two pulse signals, the driving circuit outputs a final output signal in which positive and negative levels cancel each other out. The FPGA module is used to detect whether the edge of the original transmitted signal changes. If so, it generates two pulse signals, pos and neg, and outputs V accordingly. POS and V NEG , where V POS =3V, then V NEG =0, otherwise, V POS =0V, then V NEG =3V, the pulse signal neg is the pulse signal generated within the same clock cycle when the edge change of the original transmitted signal in is detected, and the pulse signal pos is the pulse signal generated in the next clock cycle in response to the edge change delay. The driving circuit includes resistors R1-R4, a differential amplifier U1, and transistors N1-N2; wherein, the first terminal of resistor R1 receives V. NEG The second terminal is connected to the negative input terminal of the differential amplifier and the first terminal of resistor R4; the first terminal of resistor R2 receives V. POS The second terminal is connected to the positive input terminal of the differential amplifier and the first terminal of resistor R3. The second terminal of resistor R3 is connected to the power supply V. SS The second end of resistor R4 is connected to the emitter of transistors N1 and N2. The output of the differential amplifier is connected to the base of transistors N1 and N2. The collector of transistor N1 is connected to a +15V voltage, and the collector of transistor N2 is connected to a -15V voltage. The final output signal is the result of the positive and negative output levels of the sources of transistors N1 and N2 canceling each other out.

2. The FPGA-based single-core cable logging coding method according to claim 1, characterized in that, The FPGA module includes two registers, namely in_prev and delay_flag; The register in_prev stores the state of the original transmitted signal in sampled in the previous clock cycle, so as to compare it with the original transmitted signal in the current clock cycle to determine whether an edge change has occurred; the register delay_flag stores the delay control flag. When an input edge change is detected, the delay control flag is set so that a pulse signal pos is generated in the next clock cycle, and the delay control flag is cleared after generation.

3. The FPGA-based single-core cable logging coding method according to claim 2, characterized in that, When the asynchronous reset signal is activated, the FPGA module clears both the in_prev and delay_flag registers and the two pulse signals to zero, thus completing the reset. After the reset, it enters the initial state and waits for the original transmission signal to arrive.

4. The FPGA-based single-core cable logging coding method according to claim 2, characterized in that, When the system clock signal is applied, the FPGA module sequentially performs the following actions: updating the sampling state, clearing the pulse output, detecting the delay control flag, and detecting edge changes, to obtain the detection result of whether the edge of the original transmitted signal has changed.

5. The FPGA-based single-core cable logging coding method according to claim 4, characterized in that, Updating the sampling state involves storing the original transmitted signal of the current clock cycle into the in_prev register for comparison detection in the next clock cycle; Clearing the pulse output involves resetting the pulse signals `neg` and `pos` to 0 to ensure that pulses are not erroneously generated when no trigger condition is met. Detecting the delay control flag involves checking the state of the `delay_flag` register: if `delay_flag` is 1, indicating that an edge change of the original transmitted signal was detected in the previous clock cycle and a delayed pulse was scheduled, then the pulse signal `pos` is set to 1, a delayed pulse is generated in the current clock cycle, and the corresponding output `V` is displayed. POS ; And immediately clear the delay_flag; Edge change detection includes: when the delay_flag register is not activated, detecting whether the edge of the original transmitted signal changes; if it does, outputting a pulse signal neg; setting the pulse signal neg to 1 and outputting V accordingly. NEG Synchronously set the delay control flag by setting the delay_flag register to 1, thereby triggering the generation of the pos pulse signal in the next clock cycle.

6. The FPGA-based single-core cable logging coding method according to claim 1, characterized in that, When the two pulse signals output by the FPGA module cause V POS =0V and V NEG When =3V, the final output signal voltage V O =50 / 10×(0-3)=-15V;V POS =3V and V NEG When =0V, the voltage V of the final output signal O =50 / 10×(3-0)=+15V;V POS =0V and V NEG When =0V, the voltage V of the final output signal O =0V.

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