Double-code-channel signal rectifier for single-code-channel absolute position positioning

Abstract

The invention discloses a single-code-channel absolute position positioning-oriented double-code-channel signal rectifier, which is characterized in that a master state machine receives a switching strategy selection signal to enter different working modes, and a slave state machine is switched among a data waiting state, an L-channel data acquisition state and an M-channel data acquisition state according to the working mode of the master state machine, the timer provides an accurate timing signal for the slave state machine according to link delay, and the edge extraction circuit performs edge extraction on an effective synchronization pulse in an input signal; and the counter counts the effective synchronization pulses and enables the slave state machine to jump to a data waiting state when a count value reaches a preset number, in the state, the input signal is shielded, only the slave state machine and the timer work, and low power consumption is realized. Through high-precision clock control and a state machine circuit, invalid data in the establishment process can be shielded when analog front end switching has relatively long establishment time, and the validity of input data of a post-stage digital signal processing link is ensured.

Description

Technical Field

[0001] The present invention belongs to the field of digital integrated circuits and relates to a signal rectification circuit, in particular to a dual-channel signal rectification circuit applied to the absolute position positioning function of a single-channel encoder. Background Art

[0002] The dual-channel signal rectifier is specifically designed for channel switching in absolute position positioning with single-channel encoders. It is widely used in fields such as motor motion monitoring and automation systems. While ensuring a reasonable estimate of the single-channel setup time, it shields erroneous data generated during the channel switching process, ensuring that the signal processing chain receives the correct electrical signal.

[0003] Existing technical solutions mostly utilize discrete components and embedded solutions, which have limited response speed and high hardware overhead. First, embedded programs execute in a single thread, which can affect the execution of the main task and, consequently, the accuracy of the final encoder angle. Second, not only does it require timer calls, but even when supporting multiple strategies, the program is overly complex, making it impossible to achieve high-speed signal switching and rectification. Furthermore, interference from physical wiring or power supply can cause signal rectification interruptions or errors, posing application risks.

[0004] Furthermore, data rectifiers are relatively complex to design and debug, especially in complex data flow control applications. Their high cost may also limit their application in certain situations. Therefore, when selecting and designing a data rectifier, its performance, limitations, and impact on the overall system must be fully considered. Summary of the Invention

[0005] The purpose of the present invention is to provide a dual-channel signal rectifier, which can not only shield invalid data during the analog front-end switching establishment process, but also reduce power consumption.

[0006] To achieve the above-mentioned object, the present invention provides a dual-channel signal rectifier for switching and outputting dual-channel signals, wherein each group of channel signals includes a group of signals with a small number of pole pairs or a group of signals with a large number of pole pairs, and the dual-channel signal rectifier includes at least a master state machine, a slave state machine, a timer, an edge extraction circuit, and a counter;

[0007] The main state machine is used to receive a switching strategy selection signal to enter different working modes, each working mode defines obtaining a first number of small-pole pair signals and a second number of large-pole pair signals from a certain code channel signal, wherein the first number and the second number are arbitrary integers from 0 to infinity, the small-pole pair signals correspond to the L channel, and the large-pole pair signals correspond to the M channel;

[0008] The slave state machine is used to switch between the data waiting state, the L channel data acquisition state, and the M channel data acquisition state according to the working mode of the master state machine;

[0009] The timer is used to provide timing signals to the slave state machine based on the link delay, where:

[0010] Each time the slave state machine jumps to the data waiting state, it generates an analog front-end selector control signal corresponding to the next data acquisition state of the slave state machine, so that the input signal meets the channel requirements; when the slave state machine is in the data waiting state, the input signal is shielded, and only the slave state machine and the timer work; the slave state machine jumps from the data waiting state to the next data acquisition state according to the timing signal;

[0011] When the slave state machine is in the L-channel or M-channel data acquisition state, the edge extraction circuit is used to extract the edge of the valid synchronization pulse in the input signal, and the L-channel or M-channel signal in the input signal is output after processing. The counter is used to count the valid synchronization pulses, and when the count value reaches a first number or a second number, the slave state machine jumps to the data waiting state.

[0012] Optionally, the dual-channel signal rectifier further includes a clock selection circuit for selecting a low-frequency clock signal or a high-frequency clock signal to be input into the main state machine and the timer.

[0013] Optionally, the link delay is an accurate delay test result of an analog front-end link obtained by tape-out, so that the timing signal accurately quantifies the channel switching delay.

[0014] Optionally, the dual-code channel signal rectifier also includes an analog front-end controller connected to the slave state machine, which is used to generate and output the analog front-end selector control signal to the analog front-end selector so that the input signal conforms to the selected code channel and the selected channel.

[0015] Optionally, the dual-channel signal rectifier also includes a signal exchange circuit and an interpolator. When the slave state machine is in the L-channel or M-channel data acquisition state, the L-channel or M-channel signal in the input signal is output after passing through the signal exchange circuit and the interpolator. The signal exchange circuit is used to ensure the accuracy of the signal phase, and the interpolation circuit includes an interpolator for interpolating the L-channel or M-channel signal to improve the data throughput.

[0016] Optionally, the interpolation circuit further includes an integrator and a comb filter for smoothing the signal to remove high-frequency components introduced during the interpolation process.

[0017] Optionally, the dual-channel signal rectifier further includes an effective synchronization pulse generating circuit connected to the slave state machine and the edge extraction circuit, for outputting an effective synchronization output pulse while outputting the processed L channel or M channel signal.

[0018] Optionally, the dual-channel signal rectifier further includes a channel number generating circuit connected to the slave state machine, configured to generate and output a channel number indicating the channel where the output signal is located.

[0019] Optionally, the slave state machine is further configured to receive software positioning pulse signals, so as to facilitate absolute position positioning through code channel sharing at any time.

[0020] The digital integrated circuit of the present invention adopts an advanced design concept and realizes a data rectifier function of dual code channel sharing with strong anti-interference performance, low power consumption and low cost.

[0021] Its core advantage lies in its implementation of a dual-channel sharing strategy based on a single-channel signal chain, employing high-precision clock control and a flexible state machine circuit. This high-precision clock control and state machine circuitry can shield invalid data during the long setup time of analog front-end switching, ensuring the validity of input data in the subsequent digital signal processing chain. Furthermore, the use of low-power technology enables the circuit to significantly reduce energy consumption during long-term operation and in large-scale systems. This is particularly important for portable devices and embedded systems, extending battery life while reducing heat dissipation requirements and improving overall system reliability and cost-effectiveness.

[0022] In addition to implementing data rectification for code channel switching, it also features data upsampling, which can interpolate orthogonal electrical signals shared by code channels to increase data throughput and compensate for the low data rate caused by code channel switching. This basic function increases the signal sampling rate by inserting zero points between the original signal samples, and smoothes the signal through an integrator and comb filter to remove high-frequency components introduced during interpolation, thereby restoring the original spectral characteristics of the signal and providing the system with more detailed and accurate time or position feedback. This design not only improves data throughput but also provides rich information support for subsequent data processing and control decisions, enabling the system to more flexibly respond to and handle various emergencies in complex application scenarios.

[0023] Furthermore, cost control was fully considered during the circuit design process. By optimizing the circuit structure and employing proven processes, production and maintenance costs are effectively reduced, making it highly cost-effective for mass production and commercial applications. Overall, this digital integrated circuit not only implements a reliable dual-channel shared data rectifier, but also minimizes data throughput loss during dual-channel switching. With its multiple advantages of anti-interference, low power consumption, and low cost, it provides a stable and efficient timing control and data acquisition solution for various digital systems. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 Schematic diagram of the application scenario of the dual-channel shared absolute position encoder of the present invention.

[0025] Figure 2 FIG. 1 is a schematic diagram of a dual-channel signal rectifier according to an embodiment of the present invention.

[0026] Figure 3 FIG. 4 shows a schematic diagram of a state transition process of a main state machine according to an embodiment of the present invention.

[0027] Figure 4 A schematic diagram of a state transition process of a slave state machine according to an embodiment of the present invention is shown. DETAILED DESCRIPTION

[0028] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.

[0029] Figure 1 This is a schematic diagram of an application scenario of the present invention. The dual-channel signal rectifier of the present invention can be applied to signal processing of inductive coil sensors. As a commonly used angle position sensor, inductive coil sensors are widely used in fields such as motor motion monitoring and automation systems. Figure 1 For example, each of inductive coil sensor 1 and inductive coil sensor 2 includes a set of coaxial coils arranged 90° apart. One coil generates a sine signal, and the other generates a cosine signal. Each coil further comprises a small number of pole pairs and a multi-pole pair. Generally speaking, a small number of pole pairs in a single inductive coil sensor constitutes an absolute position receiving coil pair, while a multi-pole pair constitutes a high-resolution position receiving coil pair.

[0030] like Figure 1 As shown, the present invention is applied to an absolute position encoder chip shared by two inductive coil sensors (i.e., dual code channels). This chip is connected to two independent inductive coil sensors and is used to switch between the dual code channels. The received signal is processed sequentially by a single-channel signal conditioning integrated circuit, the signal rectifier of the present invention, and a digital signal processing link, ultimately outputting the signal through, for example, an RS485 interface. The primary function of the signal rectifier of the present invention is to shield erroneous data generated during the code channel switching process, ensuring that the digital signal processing link obtains and outputs correct electrical signals.

[0031] Figure 2 The dual-channel signal rectifier provided by the present invention is shown, which includes a clock selection circuit 1, a master state machine 2, a slave state machine 3, a timer circuit 4, an edge extraction circuit 5, a valid data counter circuit 6, a signal exchange circuit 7, and a valid synchronization pulse generation circuit 8.

[0032] Among them, the clock selection circuit 1 is used to select a low-frequency clock signal or a high-frequency clock signal according to the clock selection signal. The low-frequency clock signal is used for low-speed and power-sensitive scenarios, and the high-frequency clock signal is used for high-speed and performance scenarios.

[0033] The most important components of the dual-channel signal rectifier are the master state machine 2 and the slave state machine 3. The dual-channel signal rectifier's main inputs include two orthogonal electrical signals (i.e., sine and cosine signals) and a valid synchronization pulse. Its main outputs include valid synchronized orthogonal electrical signals (i.e., synchronized output sine and cosine signals), synchronized output channel numbers, valid synchronized output pulses, and analog front-end selector control signals. These two orthogonal electrical signals are obtained by modulating and demodulating the output of the inductive coil sensor using an analog front-end (AFE) and a digital-to-analog converter (ADC).

[0034] The dual-channel signal rectifier has five operating modes: switching a small number of pole pairs at any time; a 1:∞ ratio between the effective number of small and large pole pairs; a 1:N ratio between small and large pole pairs; selecting only small pole pairs; and selecting only large pole pairs. These five operating modes can be selected based on the host configuration using the switching strategy selection signal.

[0035] The following combination Figure 3 This section describes the transition process of master state machine 2. During the reset phase after chip power-up, master state machine 2 enters the IDLE state and then directly enters the pre-jump state. In this state, it jumps to one of five operating modes, corresponding to strategies 1 through 5, based on the received switching strategy selection signal. If the operating mode is modified at any time, master state machine 2 jumps to the pre-jump state and then to the modified operating mode. The operating mode of master state machine 2 determines the transition logic of the connected slave state machine 3, directly affecting the three state transitions of slave state machine 3: the duration and number of times the slave state machine 3 remains in the L channel (corresponding to the few-pole pair) state and the M channel (corresponding to the many-pole pair) state.

[0036] Figure 4 The jump process of the slave state machine 3 according to one embodiment is shown. Taking the master state machine 2 in the working mode of "the ratio of the few pole pairs to the many pole pairs is 1:N" as an example, the slave state machine 3 first enters the data waiting state (or data invalid state), waits for the timer 4 to end, and then enters the L channel data acquisition state. During this period, if a group of valid L channel data is input, the slave state machine 3 jumps to the data waiting state, waits for the timer to end, and then enters the M channel data acquisition state. After waiting for N valid M channel input data, it returns to the initial data waiting state. In this cycle, the jump of the slave state machine 3 meets the requirements. Figure 4The state transition process is shown in the figure. Here, the link delay signal received by timer 4 controlling slave state machine 3 can be the precise delay test results of the analog front-end link obtained through tape-out, thereby accurately quantifying the channel switching delay and making it more suitable for high-real-time control scenarios. By adopting the solution of precise timer 4 + analog selector 9, the present invention has significant advantages in speed, flexibility, and scalability.

[0037] During the transition process of slave state machine 3, each time it transitions from the L channel to the data waiting state or from the M channel to the data waiting state, the analog front-end selector control signal changes accordingly, controlling analog selector 9 to make the appropriate selection, ensuring that the sine and cosine signals input to the dual-channel signal rectifier meet the channel requirements. When slave state machine 3 is in the data acquisition state, the orthogonal signal stream carries a valid synchronization pulse signal and enters the dual-channel signal rectifier. First, edge extraction module 5 performs edge extraction on the input valid synchronization pulse based on the state of slave state machine 3, facilitating the acquisition of valid and stable sine and cosine data. If slave state machine 3 is in the data waiting state (i.e., an invalid state), edge extraction module 5 will not operate. The data stream is output through signal exchange circuit 7 and interpolator 10, and then through valid synchronization pulse generation circuit 8 to output a valid synchronization output pulse. Simultaneously, channel number generation circuit 11 outputs the synchronization output channel number to indicate the data channel information, facilitating the subsequent modules to obtain valid data and information. Simultaneously, analog front-end controller 12 generates analog front-end selector control signals based on the transition from slave state machine 3 and inputs them to analog selector 9. The signal handshake circuit 7 is used to bind the rotation direction to the phase relationship of the electrical signal, preventing errors caused by incorrectly connecting the arc / cosine signal. When switching from the standby state to the corresponding channel, the analog front-end selector control signal for the corresponding channel is generated, thereby obtaining the channel number information.

[0038] If the slave state machine 3 is in the data waiting state, the circuit will shield the input data, and no other circuits will work except the slave state machine 3 and the internal timer 4 to reduce power consumption.

[0039] In addition, the dual-channel signal rectifier also supports receiving absolute position positioning software instructions (i.e., software positioning pulses) generated by the processor at any time, facilitating absolute position positioning through code channel sharing at any time.

[0040] On the input side of the dual-channel signal rectifier, the switching strategy selection signal, switching ratio selection signal, link delay, software positioning pulse signal, and interpolator enable signal can be configured by an embedded program designed by engineers through the embedded RISC-V microprocessor core. In the actual chip, these signals can be configured by the processor via the AHB bus. On the output side, the synchronous output channel number, effective synchronous output pulse, synchronous output sine signal, and synchronous output cosine signal are directly output to the subsequent digital signal processing algorithm module.

[0041] In summary, compared with the prior art, the dual-channel signal rectifier of the present invention adopts CMOS technology to realize dual-channel sharing, and has the characteristics of high integration, low power consumption and high robustness. It can realize a compact and highly flexible hardware-specific circuit solution for dual-channel sharing, which is more competitive in terms of integration, configurability and economy. The present invention has the following advantages: 1) It supports multiple switching strategies and allows dynamic adjustment of the sampling timing. The dedicated hardware circuit is extremely suitable for high-real-time application scenarios of channel switching. 2) The integrated circuit integrates the functions of error signal shielding, channel switching, ID generation and generation of analog multi-channel selection control signals, without relying on external components, and the system complexity is low. 3) Through the collaborative design of software and hardware, low-cost, high-real-time dual-channel shared sensor signal conditioning is achieved, which has significant advantages in flexibility, integration and efficiency.

Claims

1. A dual-channel signal rectifier for switching and outputting dual-channel signals, wherein each set of channel signals comprises a set of signals with a small number of pole pairs or a set of signals with a large number of pole pairs, characterized in that: The dual-channel signal rectifier comprises at least a master state machine, a slave state machine, a timer, an edge extraction circuit and a counter; The main state machine is used to receive a switching strategy selection signal to enter different working modes, each working mode defines obtaining a first number of small-pole pair signals and a second number of large-pole pair signals from a certain code channel signal, wherein the first number and the second number are arbitrary integers from 0 to infinity, the small-pole pair signals correspond to the L channel, and the large-pole pair signals correspond to the M channel; The slave state machine is used to switch between the data waiting state, the L channel data acquisition state, and the M channel data acquisition state according to the working mode of the master state machine; The timer is used to provide timing signals to the slave state machine based on the link delay, where: Each time the slave state machine jumps to the data waiting state, it generates an analog front-end selector control signal corresponding to the next data acquisition state of the slave state machine, so that the input signal meets the channel requirements; when the slave state machine is in the data waiting state, the input signal is shielded, and only the slave state machine and the timer work; the slave state machine jumps from the data waiting state to the next data acquisition state according to the timing signal; When the slave state machine is in the L-channel or M-channel data acquisition state, the edge extraction circuit is used to extract the edge of the valid synchronization pulse in the input signal, and the L-channel or M-channel signal in the input signal is output after processing. The counter is used to count the valid synchronization pulses, and when the count value reaches a first number or a second number, the slave state machine jumps to the data waiting state.

2. The dual-channel signal rectifier according to claim 1, wherein: The invention also includes a clock selection circuit for selecting a low-frequency clock signal or a high-frequency clock signal to be input to the main state machine and the timer.

3. The dual-channel signal rectifier according to claim 1, wherein: The link delay is an accurate delay test result of an analog front-end link obtained by tape-out, so that the timing signal accurately quantifies the channel switching delay.

4. The dual-channel signal rectifier according to claim 1, wherein: It also includes an analog front-end controller connected to the slave state machine, which is used to generate and output the analog front-end selector control signal to the analog front-end selector to make the input signal conform to the selected code channel and the selected channel.

5. The dual-channel signal rectifier according to claim 1, wherein: It also includes a signal exchange circuit and an interpolation circuit. When the slave state machine is in the L-channel or M-channel data acquisition state, the L-channel or M-channel signal in the input signal is output after passing through the signal exchange circuit and the interpolator. The signal exchange circuit is used to ensure the accuracy of the signal phase, and the interpolation circuit includes an interpolator for interpolating the L-channel or M-channel signal to improve the data throughput.

6. The dual-channel signal rectifier according to claim 5, wherein: The interpolation circuit further includes an integrator and a comb, which are used to perform smoothing processing on the signal to remove high-frequency components introduced during the interpolation process.

7. The dual-channel signal rectifier according to claim 1, wherein: It also includes an effective synchronization pulse generating circuit connected to the slave state machine and the edge extraction circuit, which is used to output an effective synchronization output pulse while outputting the processed L channel or M channel signal.

8. The dual-channel signal rectifier according to claim 1, wherein: The system also includes a channel number generating circuit connected to the slave state machine, which is used to generate and output a channel number indicating the channel where the output signal is located.

9. The dual-channel signal rectifier according to claim 1, wherein: The slave state machine is also used to receive software positioning pulse signals, so as to realize absolute position positioning through code channel sharing at any time.

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