Zero cross detection circuit, chip and converter

Abstract

The invention discloses a zero-cross detection circuit, a chip and a converter, and relates to the field of current zero-cross detection.The zero-cross detection circuit comprises a signal comparison module and a slope compensation module, the signal comparison module comprises a first comparator and a second comparator, the first input end of the first comparator is connected with the first output end of the second comparator, and the second input end of the second comparator is connected with the slope compensation module; the second input end of the first comparator is connected with the second output end of the second comparator, and the first comparator is used for outputting a high level when detecting that the voltage of the first output end of the second comparator is greater than the voltage of the second output end of the second comparator; the slope compensation module comprises a first capacitor and a first resistor, one end of the first capacitor is connected with the second reverse input end of the second comparator and the first resistor, and the other end of the first capacitor is grounded. And signals with different current peak values can be detected when current zero crossing occurs.

Description

Technical Field

[0001] The present application relates to the field of current zero-crossing detection, and in particular to a zero-crossing detection circuit, chip, and converter. Background Art

[0002] In the prior art, when performing current zero-crossing detection on a switching power supply chip, the measured current will cause different delays in triggering the current zero-crossing due to different current peak values. It is possible that the delay in triggering the current zero-crossing is less than the comparator transmission delay, resulting in the current zero-crossing state being unable to be detected, which may cause damage to the switching power supply chip. Summary of the Invention

[0003] The present application aims to solve at least one of the technical problems existing in the prior art. To this end, the present application proposes a zero-crossing detection circuit, chip, and converter that can ensure that the delay of triggering the current zero crossing is always greater than the transmission delay of the comparator.

[0004] The zero-crossing detection circuit of the embodiment of the first aspect of the present application includes: a signal comparison module, the signal comparison module includes a first comparator and a second comparator, the first input terminal of the first comparator is connected to the first output terminal of the second comparator, the second input terminal of the first comparator is connected to the second output terminal of the second comparator, the first positive input terminal of the second comparator is used to connect to the measured current, the first reverse input terminal of the second comparator is used to connect to the reference current, the second positive input terminal of the second comparator is used to connect to the measured current, and the first comparator is used to output a high level when detecting that the voltage of the first output terminal of the second comparator is greater than the voltage of the second output terminal of the second comparator; a slope compensation module, the slope compensation module includes a first capacitor and a first resistor, one end of the first capacitor is respectively connected to the second reverse input terminal of the second comparator and the first resistor, and the other end is grounded, the first capacitor is used to output a compensation current to the second reverse input terminal of the second comparator when discharging, and the second comparator is used to control the first output terminal of the second comparator to output a voltage greater than the second output terminal of the second comparator when detecting that the measured current is less than the difference between the reference current and the compensation current, so that the first comparator outputs a high level.

[0005] According to the zero-crossing detection circuit of the embodiment of the present application, there are at least the following beneficial effects: by setting a second comparator, the measured current and the reference current are compared, so as to facilitate the judgment of whether the measured current has a current zero crossing situation, and the first comparator converts the comparison result of the second comparator into a high level or a low level, so as to facilitate the control of subsequent components to make corresponding responses; and the first capacitor and the first resistor are set to form a slope compensation circuit, so that when the measured current is detected, the current first charges the first capacitor through the first resistor, and when the current starts to decrease and decreases to a certain extent, the first capacitor starts to discharge the second comparator and the first resistor, and the discharge rate of the first capacitor is fixed according to the values of the first capacitor and the first resistor, so that the discharge time of the first capacitor is also fixed, which is the result of the multiplication of the value of the first capacitor and the value of the first resistor. The result is that the time for the measured signal to be transmitted to the second comparator is fixed, so that by adjusting the values of the first resistor and the first capacitor, the delay of the trigger current crossing zero is always kept greater than the transmission delay of the second comparator. The specific principle of the zero-crossing detection circuit of the present application is: the measured current first charges the first capacitor through the first resistor, and after the charging is completed, the first capacitor starts to slowly discharge the second comparator for a fixed time, so that the delay of the measured current passing to the second comparator is fixed, ensuring that the delay of the trigger current crossing zero can always be greater than the transmission delay of the comparator. When the second comparator detects that the input measured current is less than the difference between the reference current and the compensation current, it is judged that the current crosses zero. At this time, the voltage of the first output terminal of the second comparator is greater than the voltage of the second output terminal, and then the first comparator is controlled to output a high level. It can be seen from this that the zero-crossing detection circuit of the present application adjusts the values of the first capacitor and the first resistor so that the delay when the current triggers the current crossing zero with different peak values can be kept fixed and can also be always greater than the transmission delay of the second comparator, thereby avoiding the current zero-crossing state from being missed, thereby ensuring that the current zero-crossing state can be accurately detected.

[0006] According to some embodiments of the present application, the slope compensation module also includes a second capacitor and a third capacitor, one end of the second capacitor is connected to the first positive input terminal of the second comparator, and the other end is grounded, one end of the third capacitor is connected to the second positive input terminal of the second comparator, and the other end is grounded, wherein the value of the second capacitor is equal to the value of the third capacitor, and the sum of the value of the second capacitor and the value of the third capacitor is equal to the value of the first capacitor.

[0007] According to some embodiments of the present application, it also includes a pulse width modulation module, a first field effect transistor and a level shifter, the input end of the pulse width modulation module is used to connect to the measured current, the output end of the pulse width modulation module is connected to the gate of the first field effect transistor, the drain and source of the first field effect transistor are respectively connected to the level shifter, and the level shifter is connected to the first positive input end, the second positive input end, the first reverse input end and the second reverse input end of the second comparator.

[0008] According to some embodiments of the present application, the level shifter includes a second field-effect transistor, a third field-effect transistor, a fourth field-effect transistor, a fifth field-effect transistor, a first transistor, a second transistor, a third transistor, a fourth transistor and a first current source, the source of the second field-effect transistor is connected to the drain of the first field-effect transistor, the drain of the second field-effect transistor is connected to the bases of the first transistor, the second transistor and the third transistor respectively, the source of the fourth field-effect transistor is connected to the source of the first field-effect transistor, the drain of the fourth field-effect transistor is connected to the base of the fourth transistor, the source of the third field-effect transistor is connected to the source of the first field-effect transistor, the drain of the third field-effect transistor is connected to the drain of the second field-effect transistor, the source of the fifth field-effect transistor is connected to the first current source, and the drain of the fifth field-effect transistor is connected to the first inverting input terminal of the second comparator.

[0009] According to some embodiments of the present application, the level shifter further includes a second resistor and a third resistor, the drain of the first field effect transistor is connected to the source of the second field effect transistor through the second resistor, and the source of the fourth field effect transistor is connected to the source of the first field effect transistor through the third resistor.

[0010] According to some embodiments of the present application, the second comparator includes a second current source, a sixth field-effect transistor, a seventh field-effect transistor, an eighth field-effect transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a fourth resistor and a fifth resistor, the source of the sixth field-effect transistor is connected to a power supply, the drain of the sixth field-effect transistor is respectively connected to the second current source, the gate of the sixth field-effect transistor, the gate of the seventh field-effect transistor, and the gate of the eighth field-effect transistor, the drain of the seventh field-effect transistor is respectively connected to the emitter of the fifth transistor and the sixth transistor, the drain of the eighth field-effect transistor is respectively connected to the emitter of the seventh transistor and the eighth transistor, the collector of the fifth transistor is respectively connected to the collector of the seventh transistor, the second input terminal of the first comparator, and the fourth resistor, the collector of the sixth transistor is respectively connected to the collector of the eighth transistor, the first input terminal of the first comparator, and the fifth resistor, wherein the base of the fifth transistor is used to connect to the measured current, the base of the sixth transistor is used to connect to the reference current, the base of the seventh transistor is used to connect to the measured current, and the eighth transistor is used to connect to the compensation current.

[0011] According to some embodiments of the present application, the device further includes a first delay unit, a second delay unit, a first NAND gate, and a first NOT gate. The output end of the pulse width modulation module is connected to the first input end of the first NAND gate through the first delay unit and the second delay unit in sequence. The output end of the pulse width modulation module is also connected to the second input end of the first NAND gate, the gate of the second field-effect transistor, and the gate of the fifth field-effect transistor through the first delay unit. The output end of the pulse width modulation module is also connected to the gate of the third field-effect transistor through the first delay unit and the first NOT gate in sequence. The output end of the first NAND gate is connected to the power supply end of the first comparator.

[0012] According to some embodiments of the present application, a logic control module is further included, wherein the output end of the first comparator is connected to the logic control module, the output end of the pulse width modulation module is connected to the logic control module, and the output end of the logic control module is connected to the gate of the first field effect transistor. The logic control module is used to control the first field effect transistor to be turned off when it is detected that the first comparator outputs a high level.

[0013] A chip according to an embodiment of the second aspect of the present application includes:

[0014] A zero-crossing detection circuit according to an embodiment of the first aspect of the present application.

[0015] A converter according to an embodiment of the third aspect of the present application includes:

[0016] Multiple chips according to the second embodiment of the present application are connected in parallel with each other through the corresponding zero-crossing detection circuits of the first embodiment of the present application.

[0017] According to the chip of the embodiment of the present application, there are at least the following beneficial effects: by setting a second comparator, the measured current and the reference current are compared, thereby facilitating the determination of whether the measured current has a current zero crossing, and the first comparator converts the comparison result of the second comparator into a high level or a low level, so as to facilitate the control of subsequent components to make corresponding responses; and the first capacitor and the first resistor are set to form a slope compensation circuit, so that when the measured current is detected, the current first charges the first capacitor through the first resistor, and when the current begins to decrease and decreases to a certain extent, the first capacitor begins to discharge the second comparator and the first resistor, and the discharge rate of the first capacitor is fixed according to the values of the first capacitor and the first resistor, so that the discharge time of the first capacitor is also fixed, which is the result of multiplying the value of the first capacitor by the value of the first resistor. Thus, the time when the measured signal is transmitted to the second comparator is fixed, so that by adjusting the values of the first resistor and the first capacitor, the delay of the trigger current crossing zero is always kept greater than the transmission delay of the second comparator. The specific principle of the zero-crossing detection circuit of the present application is: the measured current first charges the first capacitor through the first resistor, and after the charging is completed, the first capacitor starts to perform a slow discharge operation on the second comparator for a fixed time, so that the delay of the measured current passing to the second comparator is fixed, ensuring that the delay of the trigger current crossing zero can always be greater than the transmission delay of the comparator. When the second comparator detects that the input measured current is less than the difference between the reference current and the compensation current, it is judged that the current crosses zero. At this time, the voltage of the first output terminal of the second comparator is greater than the voltage of the second output terminal, and then the first comparator is controlled to output a high level. It can be seen from this that the zero-crossing detection circuit of the present application adjusts the values of the first capacitor and the first resistor so that the delay when the current triggers the current crossing zero with different peak values can be kept fixed and can also be always greater than the transmission delay of the second comparator, avoiding the current zero-crossing state from being missed, thereby ensuring that the current zero-crossing state can be accurately detected. By introducing the zero-crossing detection circuit of the present application, the current zero-crossing situation can be accurately detected to avoid damage to the device under test.

[0018] Additional aspects and advantages of the present application will be given in part in the description below, and in part will become obvious from the description below, or will be learned through practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The above and / or additional aspects and advantages of the present application will become apparent and easily understood from the description of the embodiments in conjunction with the following drawings, in which:

[0020] Figure 1Schematic diagram of a zero-crossing detection circuit according to an embodiment of the present application;

[0021] Figure 2 for Figure 1 The structural block diagram of zero-crossing detection is shown;

[0022] Figure 3 is a circuit schematic diagram of a second comparator according to an embodiment of the present application;

[0023] Figure 4 This is a circuit diagram of a logic control module according to an embodiment of the present application;

[0024] Figure 5 for Figure 4 Shows the waveform diagram of some signals in the logic control module;

[0025] Figure 6 This is a schematic diagram of multiple zero-crossing detection circuits connected in parallel according to an embodiment of the present application. DETAILED DESCRIPTION

[0026] The following describes in detail embodiments of the present application. Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application and are not to be construed as limiting the present application.

[0027] In the description of this application, it should be understood that descriptions involving orientations, such as up, down, front, back, left, right, etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, they cannot be understood as limitations on this application.

[0028] In the description of this application, "several" means one or more, "many" means more than two, "greater than," "less than," and "exceed" are understood to exclude the number itself, while "above," "below," and "within" are understood to include the number itself. The terms "first" and "second" are used solely to distinguish technical features and are not to be construed as indicating or implying relative importance, or as implicitly specifying the number or order of the technical features indicated.

[0029] In the description of this application, unless otherwise clearly defined, terms such as setting, installing, and connecting should be understood in a broad sense, and technicians in the relevant technical field can reasonably determine the specific meanings of the above terms in this application based on the specific content of the technical solution.

[0030] At present, when using the traditional method to detect the zero crossing of the switching power supply chip, a reference current is usually set. When the measured current is lower than the reference current, the comparator will flip and then determine that the switching power supply chip is in the current zero crossing state. However, the peak current output by the switching power supply chip is different, which may cause different delays in triggering the current zero crossing. When the delay in triggering the current zero crossing is lower than the transmission delay of the comparator, the current zero crossing will not be detected, which may cause damage to the switching power supply chip.

[0031] Based on this, the present application proposes a zero-crossing detection circuit, chip and converter, which aim to increase and fix the delay of the measured current triggering the current zero crossing through a compensation module, so that the delay of the current zero crossing triggered by currents with different peak values is the same.

[0032] The following references Figure 1 The zero-crossing detection circuit according to an embodiment of the present application is described.

[0033] It can be understood that: the zero-crossing detection circuit of the embodiment of the present application includes a signal comparison module and a slope compensation module, the signal comparison module includes a first comparator and a second comparator, the first input terminal of the first comparator is connected to the first output terminal of the second comparator, the second input terminal of the first comparator is connected to the second output terminal of the second comparator, the first positive input terminal of the second comparator is used to connect to the measured current, the first reverse input terminal of the second comparator is used to connect to the reference current, the second positive input terminal of the second comparator is used to connect to the measured current, and the first comparator is used to output a high level when detecting that the voltage of the first output terminal of the second comparator is greater than the voltage of the second output terminal of the second comparator; the slope compensation module includes a first capacitor and a first resistor, one end of the first capacitor is respectively connected to the second reverse input terminal and the first resistor of the second comparator, and the other end is grounded, the first capacitor is used to output a compensation current to the second reverse input terminal of the second comparator when discharging, and the second comparator is used to control the first output terminal of the second comparator to output a voltage greater than the second output terminal of the second comparator when detecting that the measured current is less than the difference between the reference current and the compensation current, so that the first comparator outputs a high level.

[0034] The beneficial effects of the zero-crossing detection circuit of the embodiment of the present application can be manifested as follows: by setting a second comparator, the measured current and the reference current are compared, thereby facilitating the determination of whether the measured current crosses zero, and the first comparator converts the comparison result of the second comparator into a high level or a low level, so as to facilitate the control of subsequent components to make corresponding responses; and the first capacitor and the first resistor are set to form a slope compensation circuit, so that when the measured current is detected, the current first charges the first capacitor through the first resistor, and when the current begins to decrease and decreases to a certain extent, the first capacitor begins to discharge the second comparator and the first resistor, and the discharge rate of the first capacitor is fixed according to the values of the first capacitor and the first resistor, so that the discharge time of the first capacitor is also fixed, which is the result of multiplying the value of the first capacitor by the value of the first resistor. Thus, the time when the measured signal is transmitted to the second comparator is fixed, so that by adjusting the values of the first resistor and the first capacitor, the delay of the trigger current crossing zero is always kept greater than the transmission delay of the second comparator. The specific principle of the zero-crossing detection circuit of the present application is: the measured current first charges the first capacitor through the first resistor, and after the charging is completed, the first capacitor starts to perform a slow discharge operation on the second comparator for a fixed time, so that the delay of the measured current passing to the second comparator is fixed, ensuring that the delay of the trigger current crossing zero can always be greater than the transmission delay of the comparator. When the second comparator detects that the input measured current is less than the difference between the reference current and the compensation current, it is judged that the current crosses zero. At this time, the voltage of the first output terminal of the second comparator is greater than the voltage of the second output terminal, and then the first comparator is controlled to output a high level. It can be seen from this that the zero-crossing detection circuit of the present application adjusts the values of the first capacitor and the first resistor so that the delay when the current triggers the current crossing zero with different peak values can be kept fixed and can also be always greater than the transmission delay of the second comparator, avoiding the current zero-crossing state from being missed, thereby ensuring that the current zero-crossing state can be accurately detected.

[0035] For example, in some embodiments, reference Figure 1In this embodiment, R0 is the first resistor, ZCD_Comp1 is the first comparator, ZCD_Comp2 is the second comparator, C3 is the first capacitor, DRN and DRN1 are equal and are both measured currents, DVDT is the compensation current, VOS is the reference current, and the zero-crossing detection circuit of the present application detects the sinusoidal wave signal output by the switching power supply chip, one end of the first capacitor is grounded, and the other end is connected between one end of the first resistor and the second inverting input end of the second comparator, and the other end of the first resistor is connected to the current waveform of the component under test. The first resistor and the first capacitor form an RC network. When the current passes through the first resistor, the first capacitor is charged. Since the input is a sinusoidal current, when the current begins to decrease to a certain extent, for example: the current continues to rise at the beginning, reaches the peak and then drops to a certain extent, or the current continues to drop at the beginning, reaches the lowest point and then rises to a certain extent, the first capacitor begins to charge the first capacitor. A discharge operation is performed at a resistor and a second inverting input terminal of a second comparator. Since the values of the first resistor and the first capacitor are fixed, the time required for the first capacitor to discharge will also be a fixed time constant. Therefore, the measured current is not directly transmitted to the second comparator, but is transmitted to the second comparator after the transmitted current is delayed through the RC network. Then, when the current crosses zero, the delay for triggering the current to cross zero can be fixed, and the delay can be increased by adjusting the values of the first resistor and the first capacitor, so that the delay for triggering the current to cross zero can always be kept greater than the comparator transmission delay. In this way, even if the current input has different peak values, it can be ensured that it is transmitted to the second comparator after the same delay, so that the trigger delay of the current crossing zero is basically the same. Then, by adjusting the first capacitor and the first resistor, the delay for the current to be transmitted to the second comparator is greater than the transmission delay inside the second comparator, thereby avoiding missed detection of the current zero-crossing signal.

[0036] It should be noted that the duration of the discharge operation of the first capacitor is expressed as follows:

[0037] t = RC;

[0038] In this formula, t is the time constant of the discharge operation of the first capacitor, R is the resistance value of the first resistor, and C is the capacitance value of the first capacitor.

[0039] It can be understood that: the slope compensation module also includes a second capacitor and a third capacitor, one end of the second capacitor is connected to the first positive input terminal of the second comparator, and the other end is grounded, one end of the third capacitor is connected to the second positive input terminal of the second comparator, and the other end is grounded, wherein the value of the second capacitor is equal to the value of the third capacitor, and the sum of the value of the second capacitor and the value of the third capacitor is equal to the value of the first capacitor.

[0040] For example, in some embodiments, reference Figure 1In this embodiment, C1 is a second capacitor, C2 is a third capacitor, one end of the second capacitor, one end of the third capacitor, and one end of the first capacitor are connected in parallel and grounded, the other end of the second capacitor is connected to the first positive input terminal of the second comparator, and the other end of the third capacitor is connected to the second positive input terminal of the second comparator. The setting of the second capacitor and the third capacitor facilitates noise elimination or filtering of the input measured current. At the same time, the second capacitor value is equal to the third capacitor value, which facilitates providing the same delay for the reference current and the measured current, and further facilitates the second comparator to compare the sum of the reference current and the compensation current with the measured current, thereby avoiding false triggering of the second comparator due to delay error. The sum of the second capacitor and the third capacitor is equal to the first capacitor, thereby suppressing common-mode interference.

[0041] It can be understood that: the zero-crossing detection circuit also includes a pulse width modulation module, a first field effect transistor and a level shifter, the input end of the pulse width modulation module is used to connect to the measured current, the output end of the pulse width modulation module is connected to the gate of the first field effect transistor, the drain and source of the first field effect transistor are respectively connected to the level shifter, and the level shifter is connected to the first positive input end, the second positive input end, the first reverse input end and the second reverse input end of the second comparator.

[0042] For example, in some embodiments, reference Figure 2 and Figure 6 In this embodiment, the main electrode is a first field-effect transistor, DRAIN is the drain of the first field-effect transistor, and SOURCE is the source of the first field-effect transistor. The zero-crossing detection module includes a level shifter, a signal comparison module, and a slope compensation module. The source and drain of the first field-effect transistor are connected to the level shifter in the zero-crossing detection module. The pulse width modulation module transmits the measured current signal to the gate of the first field-effect transistor through driving. When the pulse width modulation module outputs the ONMOS signal at a high level, the first field-effect transistor turns on and transmits the measured current to the level shifter to ensure stable current transmission. The measured current is transmitted to the second comparator through the level shifter, which facilitates the conversion of the measured current into a signal suitable for reading by the second comparator, thereby facilitating the normal operation of subsequent modules of the zero-crossing detection circuit.

[0043] It can be understood that: the level shifter includes a second field-effect transistor, a third field-effect transistor, a fourth field-effect transistor, a fifth field-effect transistor, a first transistor, a second transistor, a third transistor, a fourth transistor and a first current source, the source of the second field-effect transistor is connected to the drain of the first field-effect transistor, the drain of the second field-effect transistor is connected to the bases of the first transistor, the second transistor and the third transistor respectively, the source of the fourth field-effect transistor is connected to the source of the first field-effect transistor, the drain of the fourth field-effect transistor is connected to the base of the fourth transistor, the source of the third field-effect transistor is connected to the source of the first field-effect transistor, the drain of the third field-effect transistor is connected to the drain of the second field-effect transistor, the source of the fifth field-effect transistor is connected to the first current source, and the drain of the fifth field-effect transistor is connected to the first inverting input terminal of the second comparator.

[0044] For example, in some embodiments, reference Figure 1 In this embodiment, S1 is a second field effect transistor, S2 is a third field effect transistor, S3 is a fourth field effect transistor, S4 is a fifth field effect transistor, Q1 is a first transistor, Q2 is a second transistor, Q3 is a third transistor, Q4 is a fourth transistor, A1 is a first current source, and the level shifter further includes a third current source, a fourth current source, a fifth current source, and a sixth current source, A2 is a third current source, A3 is a fourth current source, A4 is a fifth current source, and A5 is a sixth current source, wherein the first transistor, the second transistor, the third transistor, and the fourth transistor are the same transistor, and the saturation current The current is the same, and other parameters are also completely consistent. The third current source is respectively connected to the emitter of the fourth transistor and the first inverting input terminal of the second comparator, the fourth current source is respectively connected to the emitter of the third transistor and the second positive input terminal of the second comparator, the fifth current source is respectively connected to the emitter of the second transistor and the second inverting input terminal of the second comparator, and the sixth current source is respectively connected to the emitter of the first transistor and the first positive input terminal of the second comparator, thereby providing stable current for the first transistor, the second transistor, the third transistor and the fourth transistor to ensure operation in a stable working state. At the same time, the collectors of the first transistor, the second transistor, the third transistor and the fourth transistor are all connected to the source of the first field-effect transistor to facilitate the access of the measured current signal.

[0045] It should be noted that the first current source provides a current of (K-1)I, where K is a constant that can be preset based on the desired proportional relationship between the first, third, fourth, and fifth current sources, and I is a preset fixed current, such as 10μA. The third current source provides a current of I, and the fourth, fifth, and sixth current sources each provide a current of kI. k is the Boltzmann constant, a physical constant related to temperature and energy, with a value of 1.380649×10^-23 J / K (joules per Kelvin).

[0046] It can be understood that the level shifter further includes a second resistor and a third resistor, the drain of the first field effect transistor is connected to the source of the second field effect transistor through the second resistor, and the source of the fourth field effect transistor is connected to the source of the first field effect transistor through the third resistor.

[0047] For example, in some embodiments, reference Figure 1 In this embodiment, R1 is the second resistor, R2 is the third resistor, the drain of the first field effect transistor is connected to the source of the second field effect transistor through the second resistor, and the source of the first field effect transistor is connected to the source of the fourth field effect transistor through the third resistor, so as to facilitate current limiting of the input measured current and prevent damage to the circuit caused by excessive current. One end of the third resistor connected to the source of the first field effect transistor is also connected to the collectors of the first transistor, the second transistor, the third transistor, and the fourth transistor, and the other end is connected to the base of the fourth transistor through the fourth field effect transistor. The second resistor is connected to the bases of the first transistor, the second transistor, and the third transistor through the second field effect transistor. At the same time, the resistance value of the third resistor is equal to three times the resistance value of the second resistor to ensure that the current input to the bases of the first transistor, the second transistor, the third transistor, and the fourth transistor is consistent. At the same time, the current value of the measured current transmitted to the comparator after passing through the first transistor, the second transistor, the third transistor, and the fourth transistor can be expressed by the formula:

[0048]

[0049] DRN=DRAIN+V BE1 ;

[0050] DRN1=DRAIN+V BE2 ;

[0051]

[0052] At room temperature (normal temperature);

[0053] In this formula, V BE1 is the voltage between the base and emitter of the first transistor, V BE2 is the voltage between the base and emitter of the second transistor, V BE3 is the voltage between the base and emitter of the third transistor, V BE4is the voltage between the base and the emitter of the fourth transistor, DRN is the current input to the first positive input terminal of the second comparator, VOS is the current input to the first negative input terminal of the second comparator, DRN1 is the current input to the second positive input terminal of the second comparator, DVDT is the current input to the second negative input terminal of the second comparator, K is a preset constant, I is a preset fixed current, k is the Boltzmann constant, q is the unit charge, T is the Kelvin temperature, and Is is the saturation current of the transistor (the saturation currents of the first transistor, the second transistor, the third transistor and the fourth transistor are all the same).

[0054] Therefore, combining the above formula, we can derive the following relationship between the current at the second comparator input terminal when the current passes through zero:

[0055] DRN <VOS-DVDT;

[0056]

[0057] In this formula, DRN is the current input to the first positive input terminal of the second comparator, VOS is the current input to the first negative input terminal of the second comparator, DRN1 is the current input to the second positive input terminal of the second comparator, and DVDT is the current input to the second negative input terminal of the second comparator.

[0058] It can be understood that: the second comparator includes a second current source, a sixth field-effect transistor, a seventh field-effect transistor, an eighth field-effect transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a fourth resistor and a fifth resistor, the source of the sixth field-effect transistor is connected to the power supply, the drain of the sixth field-effect transistor is respectively connected to the second current source, the gate of the sixth field-effect transistor, the gate of the seventh field-effect transistor, and the gate of the eighth field-effect transistor, the drain of the seventh field-effect transistor is respectively connected to the emitters of the fifth transistor and the sixth transistor, the drain of the eighth field-effect transistor is respectively connected to the emitters of the seventh transistor and the eighth transistor, the collector of the fifth transistor is respectively connected to the collector of the seventh transistor, the second input terminal of the first comparator, and the fourth resistor, the collector of the sixth transistor is respectively connected to the collector of the eighth transistor, the first input terminal of the first comparator, and the fifth resistor, wherein the base of the fifth transistor is used to connect to the measured current, the base of the sixth transistor is used to connect to the reference current, the base of the seventh transistor is used to connect to the measured current, and the eighth transistor is used to connect to the compensation current.

[0059] For example, in some embodiments, reference Figure 3 and Figure 1In this embodiment, P1 is the sixth field-effect transistor, P2 is the seventh field-effect transistor, P3 is the eighth field-effect transistor, Ipb2uA is the second current source, Q5 is the fifth transistor, Q6 is the sixth transistor, Q7 is the seventh transistor, and Q8 is the eighth transistor. RSA is the fourth resistor, and RSB is the fifth resistor. The second current source is connected to the drain and gate of the sixth field-effect transistor, respectively. The gate of the sixth field-effect transistor is connected to the gates of the seventh field-effect transistor and the eighth field-effect transistor, respectively. This facilitates the second current source to provide bias current to the fifth, sixth, seventh, and eighth transistors, maintaining them in a stable operating state. The sources of the sixth, seventh, and eighth field-effect transistors are connected to the power supply VDRV. The fourth and fifth resistors have the same resistance value to ensure circuit balance and stability. When the current zero crossing is detected, the voltage signal NetP1 at the first output terminal of the second comparator is greater than the voltage signal NetN1 at its second output terminal. That is, the voltage signal IP1 at the first input terminal of the first comparator is greater than the voltage signal IN1 at its second input terminal, prompting the first comparator to output a high level.

[0060] It can be understood that: the zero-crossing detection circuit also includes a first delay unit, a second delay unit, a first NAND gate and a first NOT gate, the output end of the pulse width modulation module is connected to the first input end of the first NAND gate through the first delay unit and the second delay unit in sequence, the output end of the pulse width modulation module is further connected to the second input end of the first NAND gate, the gate of the second field-effect transistor, and the gate of the fifth field-effect transistor through the first delay unit, the output end of the pulse width modulation module is further connected to the gate of the third field-effect transistor through the first delay unit and the first NOT gate in sequence, and the output end of the first NAND gate is connected to the power supply end of the first comparator.

[0061] For example, in some embodiments, reference Figure 1In this embodiment, Lon is the signal output by the pulse width modulation module after passing through the first delay unit, XLON is the output signal of the first NOT gate, and the XLON signal is opposite to the LON signal, G1 is the first NAND gate, G2 is the first NOT gate, t2 is the second delay unit, and the output end of the first NAND gate is connected to the power supply end of the first comparator. Therefore, when the first NAND gate outputs a high level, the first comparator can work normally, and the pulse width adjustment module is connected to the first input end of the first NAND gate through the first delay unit and the second delay unit in sequence, which facilitates shielding the current and thus more accurately detects the current zero crossing. For example: when what needs to be detected is the downward opening part of the sine waveform, because the zero crossing detection of the switching power supply chip mainly detects the measured current from high to low passing through the reference voltage The process of current flow, and before that, the current will also pass through the reference current during the rising process, which will cause certain interference to the current zero-crossing detection. Therefore, when the pulse width modulation module outputs a high level to turn on the first field effect tube, its output signal passes through the first delay unit and the second delay unit and is connected to the first input end of the first NAND gate. The pulse width modulation module is also connected to the second output end of the first NAND gate after passing through the first delay unit. Therefore, the time when the first NAND gate outputs a high level has a certain delay compared to the time when the first field effect tube is turned on. By adjusting the first delay unit and the second delay unit, it is ensured that the first comparator starts to work only after the current rises and passes through the reference current, thereby shielding the rising current, avoiding the false detection of the current zero crossing, and thus realizing the accurate detection of the current zero crossing.

[0062] For example, in some embodiments, reference Figure 1 In this embodiment, the output of the pulse width modulation module is also connected to the gates of the second and fifth field-effect transistors via a first delay unit. When the LON signal is high and the XLON signal is low, the second field-effect transistor is turned on, while the third, fourth, and fifth field-effect transistors are turned off. The signal at the drain of the first field-effect transistor is transmitted to the first positive input, second positive input, and second negative input of the second comparator via the first, second, and third transistors, respectively. The signal at the source of the first field-effect transistor is transmitted to the first negative input of the second comparator. When the LON signal is low and the XLON signal is high, the second field-effect transistor is turned off, the third field-effect transistor is turned on, the fourth field-effect transistor is turned on, and the fifth field-effect transistor is turned off. The current of the fourth transistor is equal to that of the first, second, and third transistors, thus equalizing the voltages at the emitters and bases of the first, second, third, and fourth transistors, thereby maintaining the circuit in a steady state.

[0063] It can be understood that the zero-crossing detection circuit also includes a logic control module, the output end of the first comparator is connected to the logic control module, the output end of the pulse width modulation module is connected to the logic control module, the output end of the logic control module is connected to the gate of the first field effect transistor, and the logic control module is used to control the first field effect transistor to turn off when it is detected that the first comparator outputs a high level.

[0064] For example, in some embodiments, reference Figure 2 and Figure 6 In this embodiment, the zero-crossing detection module also includes a logic control module. The output end of the first comparator is connected to the logic control module. When the logic control module receives a high level output from the first comparator, the logic control module also outputs a corresponding signal to the gate of the first field-effect transistor, thereby turning off the first field-effect transistor in time, reducing power consumption and avoiding excessive waste.

[0065] For example, in some embodiments, reference Figure 6 In this embodiment, the zero-crossing detection circuit further includes a first AND gate, wherein the output end of the first AND gate is connected to the gate of the first field-effect transistor, the output end of the pulse width modulation module is connected to the second input end of the first AND gate, and the output end of the logic control module is connected to the first input end of the first AND gate. G3 is the first AND gate, wherein the output end of the pulse width modulation module is connected to the second input end of the first AND gate, and the output end of the logic control module is connected to the first input end of the first AND gate. Therefore, when the logic control module outputs a low level, the first AND gate outputs a low level, thereby driving the first field-effect transistor to be turned off to reduce power consumption.

[0066] For example, in some embodiments, referring to Figure 4 In this embodiment, the logic control module further includes a first buffer Buff1, a second buffer Buff2, a second NOT gate Inv1, a third NOT gate Inv2, a fourth NOT gate Inv3, and a fifth NOT gate Inv4. A sixth NOT gate Inv5, a seventh NOT gate Inv6, a second NAND gate Nand1, a third NAND gate Nand2, a fourth NAND gate Nand3, a fifth NAND gate Nand4, a second AND gate And1, a first NOR gate Nor1, a third delay unit t3, a fourth delay unit t4, a first latch SR_Latch and a second latch, a sixth resistor R, a seventh resistor R Pu, an eighth resistor RP d, a ninth resistor R Puo, a ninth field effect transistor P4, a tenth field effect transistor P5, an eleventh field effect transistor N1, and a twelfth field effect transistor N2. Figure 1 and Figure 2A specific analysis of the logic control module is as follows: the input of the fourth NOT gate is connected to the output of the pulse width modulation module, the second input of the fifth NAND gate is connected to the output of the first comparator, ZCD is an external pin, an input / output pin, used to output the signal of the logic control module, the output signal of ZCD remains high when the current does not cross zero, ZCD outputs the signal to the second input of the first NOR gate to form the feedback signal FB_ZCD, the eleventh field-effect transistor acts as a pull-down field-effect transistor, and the eighth resistor acts as a pull-down resistor;The ninth field effect transistor and the tenth field effect transistor serve as pull-up field effect transistors, the seventh resistor serves as a pull-up resistor, and the ninth resistor is a fixed resistor that pulls the voltage up to the external power supply voltage. The ONMOS signal is output by the pulse width modulation module. Under the action of the fourth NOT gate, the third NAND gate, the third delay unit, the second NOT gate, and the second NAND gate, the ONMOS signal prompts the second NAND gate to output the signal ZCDTgWD. Only when the ZCDTgWD output is high will it trigger the current zero-crossing detection, and then further screen the current in the logic control module, and then detect the current that passes the reference current but does not belong to the current zero-crossing state. Part of the current is shielded to improve the accuracy of current zero-crossing detection. At the same time, the output end of the second NAND gate is also connected to the input end of the third NAND gate, the output end of the third NAND gate is connected to the second input end of the second AND gate, and the output end of the third NAND gate is also connected to the first input end of the second AND gate through the fourth delay unit, so that the second AND gate outputs the ZCDPuWD signal. Only when ZCDPuWD outputs a high level will the ZCD signal be pulled up. When zero-crossing detection occurs, that is, when the output signal CompZCD of the first comparator is high, the output signal PdZCD of the seventh NAND gate is high, so that the eleventh field-effect transistor is turned on, and the circuit is turned on. And pull the ZCD signal to a low level. During the release of the ZCD signal, after a dead time, that is, after the ZCD signal slowly pulls up, the output terminal output signal PuZCD of the fourth NAND gate outputs a low level, causing the ninth field effect tube and the tenth field effect tube to be turned on, and the seventh resistor is used to keep the ZCD signal in a pull-up state. When the ZCD signal is pulled to a preset value, the output signal of ZCD becomes a high level, and the feedback signal FB_ZCD fed back to the second input terminal of the first NOR gate also becomes a high level, and then the PuZCD signal is converted to a high level through the first NOR gate and the fourth NAND gate. A high level causes the ninth and tenth field-effect transistors to turn off, releasing the ZCD signal. However, the ninth resistor maintains the pull-up state of the ZCD. The output of the ZCD is connected to the first input of the first AND gate via a second latch. The second latch is used to output the previous state of the ZCD output signal. When the output signal of the ZCD changes from a low level to a high level, the second latch receives the high level output by the ZCD and outputs a low level to the first input of the first AND gate, shielding the output signal ONMOS of the pulse width modulation module connected to the second input of the first AND gate, causing the first AND gate to output a low level. This in turn controls the shutdown of the first field-effect transistor, reducing power consumption.

[0067] refer to Figure 5, and further analysis, ZCD_OS is the threshold value of zero-crossing detection, IL is the current signal of the first field effect tube, when the falling current of the IL signal passes through the ZCD_OS signal, the current zero-crossing occurs, at this time the output signal CompZCD of the first comparator outputs a high level, and the ZCD signal then switches from a high level to a low level, ZCDWD is the signal at the output end of the first NAND gate, when the ZCDWD signal is high, the current zero-crossing signal can be detected, avoiding the current zero-crossing judgment triggered when the rising current of the IL signal passes through the ZCD_OS signal, LatchZCD is the signal output by the output end of the second latch, so as to control The first field effect tube is closed, ZCDTgWD is the signal output by the second NAND gate, and the current zero crossing signal is detected only when ZCDWD and ZCDTgWD are high, thereby generating a pull-down signal of ZCD, that is, the current zero crossing can be detected only when both ZCDWD and ZCDTgWD signals are high. The ZCDPuWD signal is the pull-up signal of ZCD, and the ZCD signal will be pulled up only when the ZCDPuWD signal is high. There is a dead time between the pull-up signal and the pull-down signal, which is the circled part in the figure, to avoid logical confusion caused by the simultaneous existence of the pull-up signal and the pull-down signal. During the dead time, the ZCD signal is slowly pulled up by the ninth resistor.

[0068] The chip according to the embodiment of the second aspect of the application includes the zero-crossing detection circuit of the embodiment of the first aspect of the application.

[0069] According to the chip of the embodiment of the present application, a second comparator is set to compare the measured current with the reference current, thereby facilitating the determination of whether the measured current crosses zero, and the first comparator converts the comparison result of the second comparator into a high level or a low level, thereby facilitating the control of subsequent components to make corresponding responses; and the first capacitor and the first resistor are set to form a slope compensation circuit, so that when the measured current is detected, the current first charges the first capacitor through the first resistor, and when the current begins to decrease and decreases to a certain extent, the first capacitor begins to discharge the second comparator and the first resistor, and the discharge rate of the first capacitor is fixed according to the values of the first capacitor and the first resistor, so that the discharge time of the first capacitor is also fixed, which is the result of multiplying the value of the first capacitor by the value of the first resistor, thereby making the measured current The time when the measured signal is transmitted to the second comparator is fixed, so that by adjusting the values of the first resistor and the first capacitor, the delay of the trigger current crossing zero is always kept greater than the transmission delay of the second comparator. The specific principle of the zero-crossing detection circuit of the present application is: the measured current first charges the first capacitor through the first resistor, and after the charging is completed, the first capacitor starts to perform a slow discharge operation on the second comparator for a fixed time, so that the delay of the measured current passing to the second comparator is fixed, ensuring that the delay of the trigger current crossing zero can always be greater than the transmission delay of the comparator. When the second comparator detects that the input measured current is less than the difference between the reference current and the compensation current, it is judged that the current crosses zero. At this time, the voltage of the first output terminal of the second comparator is greater than the voltage of the second output terminal, thereby controlling the first comparator to output a high level. It can be seen from this that the zero-crossing detection circuit of the present application adjusts the values of the first capacitor and the first resistor so that the delay when the current triggers the current crossing zero with different peak values can be kept fixed and can also be always greater than the transmission delay of the second comparator, thereby avoiding the current zero-crossing state from being missed, thereby ensuring that the current zero-crossing state can be accurately detected. By introducing the zero-crossing detection circuit of the present application, the current zero-crossing situation can be accurately detected to avoid damage to the device under test.

[0070] Since the chip includes the zero-crossing detection circuit of the first aspect embodiment, the corresponding contents of the zero-crossing detection circuit in the first aspect embodiment can be applied to the chip of the second aspect, and have the same implementation principles and technical effects. In order to avoid redundant description, it will not be described in detail here.

[0071] The converter according to the third aspect embodiment of the application includes multiple chips of the second aspect embodiment of the application, and the multiple chips of the second aspect embodiment of the application are connected in parallel with each other through the corresponding zero-crossing detection circuit of the first aspect embodiment of the application.

[0072] For example, in some embodiments, referring to Figure 6In this embodiment, the converter of the present application includes multiple chips of the present application, and multiple chips of the present application are used in parallel through corresponding zero-crossing detection circuits. Multiple zero-crossing detection circuits can be connected in parallel, and the output ends of multiple ZCD pins are connected to each other. When one of the zero-crossing detection circuits detects that the current crosses zero, the ZCD pin of the circuit will send a signal to other parallel ZCD pins, that is, the ZCD pin can both output and receive signals, and then the first field-effect transistors corresponding to all parallel zero-crossing detection circuits will be turned off to reduce power consumption.

[0073] The embodiments described in the embodiments of this application are intended to more clearly illustrate the technical solutions of the embodiments of this application and do not constitute a limitation on the technical solutions provided by the embodiments of this application. Those skilled in the art will appreciate that with the evolution of technology and the emergence of new application scenarios, the technical solutions provided in the embodiments of this application are also applicable to similar technical problems.

[0074] Those skilled in the art will understand that the technical solutions shown in the figures do not constitute a limitation on the embodiments of the present application, and may include more or fewer steps than shown in the figures, or a combination of certain steps, or different steps.

[0075] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate, i.e., they may be located in one place or distributed across multiple network units. Some or all of the modules may be selected based on actual needs to achieve the objectives of this embodiment.

[0076] Those skilled in the art will appreciate that all or some of the steps in the methods, systems, and functional modules / units in the devices disclosed above may be implemented as software, firmware, hardware, or appropriate combinations thereof.

[0077] The terms "first", "second", "third", "fourth", etc. (if any) in the specification of the present application and the above-mentioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequential order. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0078] It should be understood that in this application, "at least one (item)" means one or more, and "plurality" means two or more. "And / or" is used to describe the association relationship of associated objects, indicating that three relationships may exist. For example, "A and / or B" can mean: only A exists, only B exists, and A and B exist at the same time, where A and B can be singular or plural. The character " / " generally indicates that the previous and next associated objects are in an "or" relationship. "At least one of the following items" or similar expressions refers to any combination of these items, including any combination of single items or plural items. For example, at least one of a, b or c can mean: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, c can be single or multiple.

[0079] In the several embodiments provided in this application, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are merely schematic. For example, the division of the above-mentioned units is only a logical function division. In actual implementation, there may be other division methods, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0080] The units described above as separate components may or may not be physically separate, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of these units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0081] In addition, the functional units in the various embodiments of the present application may be integrated into a single processing unit, or each unit may exist physically separately, or two or more units may be integrated into a single unit. The aforementioned integrated units may be implemented in the form of hardware or software functional units.

[0082] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art, or all or part of the technical solution can be embodied in the form of a software product, which is stored in a storage medium and includes multiple instructions for enabling a computer device (which can be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of various embodiments of the present application. The aforementioned storage medium includes: various media that can store programs, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk.

[0083] The preferred embodiments of the present invention are described above with reference to the accompanying drawings, but are not intended to limit the scope of the present invention. Any modifications, equivalent substitutions, and improvements made by those skilled in the art without departing from the scope and essence of the present invention should be within the scope of the present invention.

Claims

1. A zero-crossing detection circuit, characterized in that: include: a signal comparison module, the signal comparison module comprising a first comparator and a second comparator, wherein a first input terminal of the first comparator is connected to a first output terminal of the second comparator, a second input terminal of the first comparator is connected to a second output terminal of the second comparator, a first positive input terminal of the second comparator is used to connect to a measured current, a first negative input terminal of the second comparator is used to connect to a reference current, and a second positive input terminal of the second comparator is used to connect to the measured current, and the first comparator is used to output a high level when detecting that a voltage at the first output terminal of the second comparator is greater than a voltage at the second output terminal of the second comparator; A slope compensation module, the slope compensation module including a first capacitor and a first resistor, one end of the first capacitor being respectively connected to the second inverting input terminal of the second comparator and the first resistor, and the other end being grounded, the first capacitor being configured to output a compensation current to the second inverting input terminal of the second comparator during discharge, and the second comparator being configured to control the first output terminal of the second comparator to output a voltage greater than the second output terminal of the second comparator when detecting that the measured current is less than the difference between the reference current and the compensation current, so that the first comparator outputs a high level.

2. The zero-crossing detection circuit according to claim 1, characterized in that The slope compensation module also includes a second capacitor and a third capacitor, one end of the second capacitor is connected to the first positive input terminal of the second comparator, and the other end is grounded, one end of the third capacitor is connected to the second positive input terminal of the second comparator, and the other end is grounded, wherein the value of the second capacitor is equal to the value of the third capacitor, and the sum of the values of the second capacitor and the third capacitor is equal to the value of the first capacitor.

3. The zero-crossing detection circuit according to claim 1, wherein: The device further includes a pulse width modulation module, a first field effect transistor, and a level shifter. The input end of the pulse width modulation module is used to connect to the measured current. The output end of the pulse width modulation module is connected to the gate of the first field effect transistor. The drain and source of the first field effect transistor are respectively connected to the level shifter. The level shifter is connected to the first positive input end, the second positive input end, the first reverse input end, and the second reverse input end of the second comparator.

4. The zero-crossing detection circuit according to claim 3, characterized in that: The level shifter includes a second field-effect transistor, a third field-effect transistor, a fourth field-effect transistor, a fifth field-effect transistor, a first transistor, a second transistor, a third transistor, a fourth transistor and a first current source. The source of the second field-effect transistor is connected to the drain of the first field-effect transistor, the drain of the second field-effect transistor is connected to the bases of the first transistor, the second transistor and the third transistor respectively, the source of the fourth field-effect transistor is connected to the source of the first field-effect transistor, the drain of the fourth field-effect transistor is connected to the base of the fourth transistor, the source of the third field-effect transistor is connected to the source of the first field-effect transistor, the drain of the third field-effect transistor is connected to the drain of the second field-effect transistor, the source of the fifth field-effect transistor is connected to the first current source, and the drain of the fifth field-effect transistor is connected to the first inverting input terminal of the second comparator.

5. The zero-crossing detection circuit according to claim 4, characterized in that: The level shifter further includes a second resistor and a third resistor. The drain of the first field effect transistor is connected to the source of the second field effect transistor through the second resistor. The source of the fourth field effect transistor is connected to the source of the first field effect transistor through the third resistor.

6. The zero-crossing detection circuit according to claim 1, characterized in that: The second comparator includes a second current source, a sixth field-effect transistor, a seventh field-effect transistor, an eighth field-effect transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a fourth resistor, and a fifth resistor. The source of the sixth field-effect transistor is connected to a power supply, the drain of the sixth field-effect transistor is respectively connected to the second current source, the gate of the sixth field-effect transistor, the gate of the seventh field-effect transistor, and the gate of the eighth field-effect transistor, the drain of the seventh field-effect transistor is respectively connected to the emitters of the fifth and sixth transistors, the drain of the eighth field-effect transistor is respectively connected to the emitters of the seventh and eighth transistors, the collector of the fifth transistor is respectively connected to the collector of the seventh transistor, the second input terminal of the first comparator, and the fourth resistor, the collector of the sixth transistor is respectively connected to the collector of the eighth transistor, the first input terminal of the first comparator, and the fifth resistor, wherein the base of the fifth transistor is used to connect to the measured current, the base of the sixth transistor is used to connect to the reference current, the base of the seventh transistor is used to connect to the measured current, and the eighth transistor is used to connect to the compensation current.

7. The zero-crossing detection circuit according to claim 4, characterized in that: The device further includes a first delay unit, a second delay unit, a first NAND gate, and a first NOT gate. The output end of the pulse width modulation module is connected to the first input end of the first NAND gate through the first delay unit and the second delay unit in sequence. The output end of the pulse width modulation module is also connected to the second input end of the first NAND gate, the gate of the second field-effect transistor, and the gate of the fifth field-effect transistor through the first delay unit. The output end of the pulse width modulation module is also connected to the gate of the third field-effect transistor through the first delay unit and the first NOT gate in sequence. The output end of the first NAND gate is connected to the power supply end of the first comparator.

8. The zero-crossing detection circuit according to claim 3, characterized in that: It also includes a logic control module, the output end of the first comparator is connected to the logic control module, the output end of the pulse width modulation module is connected to the logic control module, and the output end of the logic control module is connected to the gate of the first field effect transistor. The logic control module is used to control the first field effect transistor to be turned off when it is detected that the first comparator outputs a high level.

9. A chip, characterized in that: include: The zero-crossing detection circuit according to any one of claims 1 to 8.

10. A converter, characterized in that: include: A plurality of chips as claimed in claim 9, wherein the plurality of chips are connected in parallel with each other through the corresponding zero-crossing detection circuits.

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