Multi-channel synchronous impedance measurement system and impedance measurement method

Abstract

The invention discloses a multichannel synchronous impedance measurement system and an impedance measurement method, the multichannel synchronous impedance measurement system comprises a signal generation module, a multichannel signal acquisition module, a control module and a display and operation module. The signal generation module comprises a DDS chip and a programmable control operational amplifier and is used for applying current excitation signals to two ends of a to-be-tested system, the multi-channel signal acquisition module comprises at least two multi-channel ADCs and realizes synchronous acquisition through a synchronous trigger circuit, and the control module realizes ADC data receiving and real-time calibration algorithm through an FPGA. And the display and operation module realizes measurement mode selection and result display. The method has the characteristics of high measurement precision and low single-channel power consumption, and signal leakage of adjacent channels is detected; 0.1%, 8 channels synchronously acquire time sequence deviation lt; the temperature drift is 1t after continuous working for 24 hours in 50ns; and 10 ppm.

Description

Technical Field

[0001] The present invention belongs to the field of electronic technology, and in particular relates to a multi-channel synchronous impedance measurement system and an impedance measurement method. Background Art

[0002] In industrial testing, biomedicine, material analysis and other fields, impedance measurement technology is widely used in material property analysis, equipment status monitoring and system performance evaluation.

[0003] When faced with the requirements of complex systems or multi-point synchronous measurement, existing technologies have the following limitations:

[0004] 1) Traditional multi-channel EIS equipment:

[0005] Using multiple independent single-channel EIS devices in parallel and switching the measurement channels through mechanical relays makes the system bulky and expensive.

[0006] 2) Analog switch switching solution:

[0007] Using an analog multiplexer (such as the ADG1408) to switch sensor channels suffers from channel-to-channel crosstalk (>1% signal interference) and bandwidth limitations (<100kHz).

[0008] 3) Distributed collection architecture:

[0009] Each channel is equipped with independent signal generation and acquisition circuits, with high power consumption (single channel >50mW), making it difficult to support large-scale channel expansion. Summary of the Invention

[0010] The present invention aims to solve the above-mentioned technical problems existing in the prior art and to provide a multi-channel synchronous impedance measurement system and an impedance measurement method.

[0011] In order to solve the above technical problems, the present invention adopts the following technical solutions:

[0012] A multi-channel synchronous impedance measurement system, characterized by comprising a signal generation module, a multi-channel signal acquisition module, a control module, and a display and operation module. The signal generation module includes a DDS chip and a programmable control operational amplifier, used to apply a current excitation signal across the system under test. The multi-channel signal acquisition module includes at least two multi-channel ADCs, which achieve synchronous acquisition via a synchronous trigger circuit. The control module implements ADC data reception and real-time calibration algorithms via an FPGA. The display and operation module enables measurement mode selection and result display.

[0013] Furthermore, the synchronous trigger circuit of the multi-channel signal acquisition module adopts: a trigger signal distribution network with star topology or differential transmission to start conversion on all channels simultaneously; the CONVST pins of three ADCs are connected in parallel to achieve 6-channel synchronous sampling; and the FPGA receives 18-channel data through a parallel bus or SerDes module.

[0014] Furthermore, the DDS chip of the signal generation module adopts AD9834, and the programmable control operational amplifier adopts AD8014ARZ. A current excitation signal is applied to the first and last ends of the series battery. The frequency of the current excitation signal is 0.1Hz~1MHz, and the amplitude resolution is 12bit.

[0015] Furthermore, it also includes an excitation circuit and a differential wiring acquisition circuit. The excitation circuit adopts a four-layer PCB design, including an alternating arrangement structure of signal layers and ground layers, a matching network and a GuardRing structure. The alternating arrangement structure of signal layers and ground layers is designed as a top layer signal, a second layer ground, a third layer power supply, and a bottom layer signal. The GuardRing structure is set on the top and bottom layers. The GuardRing structure includes a ring-shaped ground surrounding structure and a via array; the differential wiring acquisition circuit realizes common-mode interference suppression.

[0016] Furthermore, the GuardRing structure also includes a double ground ring: the inner ring is connected to the analog ground plane and the outer ring is connected to the digital ground plane.

[0017] Furthermore, the anti-common-mode interference design of the acquisition circuit is as follows: based on ADC, differential wiring, to resist common-mode interference; use of high-precision and low-temperature drift reference voltage; single-battery power supply combined with USB charging mode; LDO step-down module.

[0018] Furthermore, the real-time calibration algorithm executed by the control module includes:

[0019] 1) Switch the reference resistor via a relay or MOSFET switch.

[0020] 2) Apply a standard excitation signal and measure the actual impedance value.

[0021] 3) Calculate the calibration coefficient K = Z ref / Z meas and applied to subsequent measurements, where Z meas is the actual impedance value, Z ref is the theoretical value.

[0022] 4) When the temperature change exceeds the threshold, automatic calibration is triggered.

[0023] Furthermore, the control module also adopts: digital phase-locked amplification technology, generating orthogonal reference signals through the DDS chip, and performing multiplication and filtering; sliding average filtering algorithm to make the system signal-to-noise ratio >80dB.

[0024] An impedance measurement method for a multi-channel synchronous impedance measurement system, characterized by comprising the following steps:

[0025] S1, dynamic compensation step: measuring the high impedance channel according to the temperature and feedback signal amplitude;

[0026] S2, synchronous acquisition step: start multi-channel ADC synchronous conversion through a unified trigger pulse;

[0027] S3, noise suppression step: combining DLIA with sliding average filtering to extract effective signals.

[0028] Furthermore, the channel expansion step is also included:

[0029] 1) Through cascade expansion, the ADC chip can achieve 8-64 channel expansion;

[0030] 2) Maintain channel isolation >80dB@100kHz and timing deviation <50ns.

[0031] The present invention has the following beneficial effects due to the adoption of the above technical solution:

[0032] (1) Performance indicators:

[0033] 1) Number of channels: supports 8-64 channels;

[0034] 2) Channel isolation: >80dB@100kHz;

[0035] 3) Measurement accuracy: impedance amplitude error ±0.5%, phase error ±0.2°;

[0036] 4) Single-channel power consumption: <15mW, 70% lower than traditional solutions.

[0037] (2) Actual measurement comparison:

[0038] 1) Crosstalk test: Under 1MHz excitation, adjacent channel signal leakage is <0.1%, while the traditional solution is >1.5%;

[0039] 2) Synchronicity test: 8-channel synchronous acquisition timing deviation <50ns;

[0040] 3) Long-term stability: Temperature drift <10ppm after 24 hours of continuous operation.

[0041] (3) Application cases:

[0042] In lithium-ion battery module testing, there is no delay between measurement channels. The error in power battery pack consistency assessment is ≤1%, while the error of traditional methods is ≥3%. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] The present invention will be further described below in conjunction with the accompanying drawings:

[0044] Figure 1 This is the system architecture diagram;

[0045] Figure 2 For the excitation circuit;

[0046] Figure 3 It is an acquisition solution to resist common mode interference;

[0047] Figure 4 Acquire timing waveforms for multiple channels synchronously;

[0048] Figure 5 A diagram showing the connections between modules in the system;

[0049] Figure 6 This is the circuit diagram for differential wiring. DETAILED DESCRIPTION

[0050] The multi-channel synchronous impedance measurement system of the present invention,

[0051] 1. Hardware architecture design Figure 1 As shown, the core modules include: signal generation module, multi-channel signal acquisition module, control module, display and operation module.

[0052] Signal generation module:

[0053] A DDS chip (AD9834) is used in conjunction with a programmable control operational amplifier (AD8014ARZ). A current excitation signal is applied to the first and last ends of the series-connected batteries. The frequency range is 0.1Hz to 1MHz, and the amplitude resolution is 12bit.

[0054] Multi-channel signal acquisition module:

[0055] Using three 6-channel ADCs (AD7565), it supports up to 18 channels of simultaneous acquisition with a sampling rate of 250kSPS.

[0056] The AD7656 features six independent successive approximation register (SAR) analog-to-digital converters. Conversion processing and data accuracy are controlled by the CONVST signal and an internal crystal oscillator. Three CONVST pins allow independent and simultaneous sampling of three ADCs. When all three CONVST pins are connected together, six channels can be sampled simultaneously. The AD7656 features high-speed parallel and serial interfaces, allowing it to interface with microprocessors and DSPs. When using the serial interface mode, the AD7656's daisy-chain feature allows multiple ADCs to be connected to a single serial interface.

[0057] The control module generates a unified trigger pulse through an FPGA or dedicated timing controller and distributes it to the trigger pins of the three AD7565s using a star topology or differential transmission (LVDS), ensuring that all channels start conversion simultaneously. The AD7565 supports parallel output mode, and the six-channel data of each ADC can be transmitted to the FPGA via a 16-bit parallel bus. The FPGA must allocate sufficient I / O resources to receive data from the three ADCs (total data rate: 18 channels × 250kSPS × 16 bits = 72Mbps). If a serial interface (such as SPI) is used, the FPGA's SerDes module must be used for high-speed serial-to-parallel conversion, and the number of interfaces must be reduced by daisy-chaining.

[0058] Display and operation module:

[0059] It uses a 5-inch touch screen and supports functions such as selecting measurement mode, uploading measurement data, and displaying test results.

[0060] The connection relationship between each module is as follows Figure 5 shown.

[0061] 2. Key circuit design: excitation circuit and acquisition circuit

[0062] 2.1 Excitation circuit, such as Figure 2 As shown:

[0063] (1) Four-layer PCB design: The structure of a four-layer board is generally the top layer (signal), the second layer (ground), the third layer (power), and the bottom layer (signal). The signal layer and the ground layer are arranged alternately.

[0064] (2) Set up a matching network in the excitation circuit to reduce signal reflection.

[0065] (3) Use Guard Ring technology to surround sensitive analog traces, place them on the top and bottom layers, surround the sensitive traces, and connect to the ground plane. Guard Ring design specifications:

[0066] 1) Annular ground structure: Use 0.5mm line width copper foil to surround the sensitive area on the top and bottom layers.

[0067] 2) Via hole array: spacing λ / 20 (λ is the wavelength of the interference signal), typical value is 2mm spacing and 1mm aperture via hole.

[0068] 3) Three-dimensional connection: vertically connect the ground planes of each layer through the via matrix to form a Faraday cage effect

[0069] 4) Special processing: Add a double guard ring (inner ring analog ground / outer ring digital ground) at the ADC analog input.

[0070] 2.2 Collection circuit, such as Figure 3 As shown:

[0071] Acquisition solution to resist common mode interference:

[0072] (1) Based on AD7565, differential wiring, resistance to common mode interference, differential wiring circuit design such as Figure 6 shown.

[0073] (2) Use high-precision and low-temperature drift reference voltage to improve acquisition accuracy.

[0074] (3) Power management solution: Powered by a single battery and rechargeable via USB.

[0075] (4) LDO step-down module: The power supply architecture is simple and the cost is low. LDO is very common, for example, the TPS7A4700 (3.3V / 1A, 4μVRMS noise, 70dB PSRR@1kHz) can be used.

[0076] 3. Intelligent control algorithm

[0077] 3.1 Acquisition compensation strategy: Dynamic compensation is performed based on the temperature and amplitude of the feedback signal, and high-impedance channels are measured first to reduce the impact of crosstalk.

[0078] 3.2 Real-time calibration algorithm: Automatically inject a known reference impedance (e.g. 1kΩ±0.1%) before each measurement to correct the measurement deviation.

[0079] Hardware design: A high-precision reference resistor (1kΩ±0.1%) is connected in parallel or series in the measurement loop and switched to the measurement path via a relay or MOSFET switch.

[0080] Specific steps:

[0081] (1) Switch to reference impedance: The control signal triggers the switch to connect the reference resistor to the circuit.

[0082] (2) Excitation signal application: Apply standard AC / DC excitation (such as 1kHz sine wave, amplitude 1V)

[0083] (3) Signal acquisition and processing: Measure the voltage / current across the reference resistor and calculate the actual impedance value Z meas and the theoretical value Z ref Compare and calculate the calibration coefficient K=Z ref / Z meas .

[0084] (4) Coefficient application: Multiply K by the measured value of the subsequent measured impedance to correct the system gain error.

[0085] (5) Switch back to the channel being measured: disconnect the reference resistor and resume normal measurement.

[0086] (6) Periodic calibration: Calibration is performed before each measurement or triggered when the temperature changes beyond a threshold.

[0087] 3.3 Noise suppression technology: Combining digital lock-in amplifier (DLIA) with sliding average filtering, the signal-to-noise ratio is >80dB.

[0088] Implementation method:

[0089] Reference Signal Generation: Direct Digital Synthesis (DDS) is used to generate quadrature reference signals, sin(2πft) and cos(2πft), synchronized with the excitation. The input signal Vin is multiplied by the reference signals to yield I = Vin * sin(2πft) and Q = Vin * cos(2πft). The resulting products are low-pass filtered (e.g., using a moving average or IIR filter) to extract the DC components X (in-phase) and Y (quadrature).

[0090] Noise suppression: Out-of-band noise is suppressed through narrowband filtering (retaining only the excitation frequency component), and the signal-to-noise ratio can be improved by more than 80dB.

[0091] The present invention has the following beneficial effects due to the adoption of the above technical solution:

[0092] (1) Performance indicators:

[0093] 1) Number of channels: supports 8-64 channels;

[0094] 2) Channel isolation: >80dB@100kHz;

[0095] 3) Measurement accuracy: impedance amplitude error ±0.5%, phase error ±0.2°;

[0096] 4) Single-channel power consumption: <15mW (70% lower than traditional solutions).

[0097] (2) Actual measurement comparison:

[0098] 1) Crosstalk test: Under 1MHz excitation, adjacent channel signal leakage is <0.1%, while the traditional solution is >1.5%;

[0099] 2) Synchronicity test: 8-channel synchronous acquisition timing deviation <50ns;

[0100] 3) Long-term stability: Temperature drift <10ppm after 24 hours of continuous operation.

[0101] (3) Application cases, such as Figure 4 As shown:

[0102] In lithium-ion battery module testing, there is no delay between measurement channels. The error in power battery pack consistency assessment is ≤1%, while the error of traditional methods is ≥3%.

[0103] The above are only specific embodiments of the present invention, but the technical features of the present invention are not limited thereto. Any simple changes, equivalent substitutions, or modifications based on the present invention to solve substantially the same technical problems and achieve substantially the same technical effects are all included in the scope of protection of the present invention.

Claims

1. Multi-channel synchronous impedance measurement system, characterized in that: include: A signal generating module, comprising a DDS chip and a programmable control operational amplifier, for applying a current excitation signal across the system under test; A multi-channel signal acquisition module, comprising at least two multi-channel ADCs, which realize synchronous acquisition through a synchronous trigger circuit; A control module, wherein the control module implements ADC data reception and real-time calibration algorithm through FPGA; The display and operation module realizes measurement mode selection and result display.

2. The multi-channel synchronous impedance measurement system according to claim 1, characterized in that: The synchronous trigger circuit of the multi-channel signal acquisition module adopts: A trigger signal distribution network with star topology or differential transmission is used to start conversion on all channels simultaneously; The CONVST pins of three ADCs are connected in parallel to achieve 6-channel synchronous sampling; The FPGA receives 18 channels of data via a parallel bus or SerDes module.

3. The multi-channel synchronous impedance measurement system according to claim 1, characterized in that: The DDS chip of the signal generating module adopts AD9834, and the programmable control operational amplifier adopts AD8014ARZ. The current excitation signal is applied to the first and last ends of the series-connected batteries. The frequency of the current excitation signal is 0.1Hz-1MHz, and the amplitude resolution is 12bit.

4. The multi-channel synchronous impedance measurement system according to claim 1, wherein: Also includes: The excitation circuit adopts a four-layer PCB design, including a structure with alternating signal and ground layers, a matching network, and a guard ring structure. The structure of alternating signal and ground layers is designed as a top signal layer, a second ground layer, a third power layer, and a bottom signal layer. The guard ring structure is set on the top and bottom layers, and the guard ring structure includes a ring-shaped ground surrounding structure and a via array. Acquisition circuit to achieve common mode interference suppression.

5. The multi-channel synchronous impedance measurement system according to claim 4, characterized in that: The GuardRing structure also includes a double ground ring: an inner ring connected to the analog ground plane and an outer ring connected to the digital ground plane.

6. The multi-channel synchronous impedance measurement system according to claim 4, characterized in that: The anti-common mode interference design of the acquisition circuit is: Based on ADC, differential wiring, resistance to common mode interference; Use high-precision, low-temperature drift reference voltage; Single battery power supply combined with USB charging mode; LDO step-down module.

7. The multi-channel synchronous impedance measurement system according to claim 1, characterized in that: The real-time calibration algorithm executed by the control module includes: 1) Connect the reference resistor via a relay or MOSFET switch; 2) Apply a standard excitation signal and measure the actual impedance value; 3) Calculate the calibration coefficient K = Z ref / Z meas and applied to subsequent measurements, where Z meas is the actual impedance value, Z ref is the theoretical value; 4) When the temperature change exceeds the threshold, automatic calibration is triggered.

8. The multi-channel synchronous impedance measurement system according to claim 1, characterized in that: The control module also uses: Digital phase-locked amplification technology generates orthogonal reference signals through the DDS chip, and performs multiplication and filtering; The sliding average filtering algorithm makes the system signal-to-noise ratio >80dB.

9. The impedance measurement method according to any one of claims 1 to 8, characterized in that: The steps include: S1, dynamic compensation step: measuring the high impedance channel according to the temperature and feedback signal amplitude; S2, synchronous acquisition step: start multi-channel ADC synchronous conversion through a unified trigger pulse; S3, noise suppression step: combining DLIA with sliding average filtering to extract effective signals.

10. The impedance measurement method according to claim 9, wherein: Also includes channel expansion steps: 1) Through cascade expansion, the ADC chip can achieve 8-64 channel expansion; 2) Maintain channel isolation >80dB@100kHz and timing deviation <50ns.

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