SiC MOSFET third quadrant characteristic test circuit and method considering channel dynamic response

Abstract

The invention discloses a SiC MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) third quadrant characteristic test circuit and method considering channel dynamic response, and the circuit comprises a photoelectric isolation interface, an adjustable bias three-state drive circuit, a low-resistance electronic switch array, and a tested device interface, the input end of the photoelectric isolation interface is connected with the I / O port of a DSP (Digital Signal Processor) controller; the output end of the adjustable bias three-state driving circuit is connected with the input ends of the adjustable bias three-state driving circuit and the low-resistance electronic switch array, and the output end of the adjustable bias three-state driving circuit is connected with the grid electrode of the tested device; the method comprises the following steps: applying pretreatment excitation to a SiC MOSFET grid, so that a device channel enters an activated state; applying test excitation to the tested device to obtain third quadrant current data; and adjusting the bias of the gate-source voltage and the drain-source voltage, and repeating the measurement to obtain the third quadrant characteristic of the SiC MOSFET considering the dynamic response of the channel. According to the technical scheme, by increasing grid voltage preprocessing excitation, the operation characteristics of the device under the actual working condition of the converter are restored to the maximum extent, and the test precision of the third quadrant characteristics of the SiC MOSFET is improved.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor device testing, and in particular relates to a SiC MOSFET third quadrant characteristic testing circuit and method taking into account channel dynamic response. Background Art

[0002] As a representative wide-bandgap power semiconductor device, SiC MOSFETs feature high voltage, high temperature, high speed, and high frequency. They contribute to the advancement of power electronics towards higher power density and operating efficiency, and are expected to completely replace Si-based IGBTs. However, due to their extremely fast switching speeds, testing SiC MOSFET characteristics at nanosecond timescales is extremely challenging. Unlike Si-based IGBTs, SiC MOSFETs can operate in the third quadrant, with both their body diode and channel capable of conducting reverse current. SiC MOSFETs can operate in either freewheeling mode or synchronous rectification mode to reduce third-quadrant conduction losses. Accurately testing and evaluating SiC MOSFET third-quadrant conduction characteristics is key to fully leveraging the device's high-frequency advantages.

[0003] The traditional method for testing the third-quadrant characteristics of SiC MOSFETs uses a fixed gate-source voltage, applies a pulsed voltage across the source and drain of the device, and reads the on-current. While this method is simple, it suffers from poor measurement accuracy. This is because traditional testing methods fail to account for the switching behavior of SiC MOSFETs in actual converters. Due to manufacturing process limitations, SiC MOSFETs possess numerous interface state traps at the SiC / SiO2 gate oxide interface. These traps trap holes under positive gate voltages, attracting more inverted electrons when the channel is on, thereby increasing the device's conductivity. Conversely, negative gate voltages reduce the device's conductivity. Traditional testing methods typically negatively bias the SiC MOSFET gate before testing, resulting in an underestimation of the third-quadrant on-current. This error is particularly significant at high gate voltages.

[0004] SiC MOSFET devices are generally in a switching state during the actual operation of the converter, and the gate voltage is repeatedly subjected to AC excitation. Correctly considering the dynamic response of the channel is the key to accurately describing the third quadrant characteristics of SiC MOSFET devices. Summary of the Invention

[0005] The purpose of the present invention is to provide a circuit and method for testing the third-quadrant characteristics of SiC MOSFETs that takes into account the dynamic response of the channel. By adding gate voltage preconditioning excitation, the operating characteristics of the device under actual converter operating conditions are restored to the greatest extent possible, thereby improving the test accuracy of the third-quadrant characteristics of SiC MOSFETs.

[0006] In order to achieve the above object, the solution of the present invention is:

[0007] A SiC MOSFET third-quadrant characteristic test circuit that considers channel dynamic response includes an optoelectronic isolation interface, an adjustable bias three-state drive circuit, and a low-resistance electronic switch array. The optoelectronic isolation interface has an input connected to an I / O port of a DSP controller, and an output connected to the input of the adjustable bias three-state drive circuit. The optoelectronic isolation interface converts the digital signal level of the DSP controller into an input level recognizable by the adjustable bias three-state drive circuit and sends the converted signal to the adjustable bias three-state drive circuit. The output of the adjustable bias three-state drive circuit is connected to the gate of a device under test and outputs a high-level voltage, a low-level voltage, or a high-resistance signal based on the input level. The output of the optoelectronic isolation interface is also connected to the input of the low-resistance electronic switch array, converting a command signal from the DSP controller into an input level recognizable by the low-resistance electronic switch array and sending the converted signal to the low-resistance electronic switch array. The low-resistance electronic switch array is turned on or off under the control of the input level. When the low-resistance electronic switch array is turned on, a test excitation voltage is applied between the source and drain of the device under test, causing the device to generate a source-drain current; otherwise, no current is generated.

[0008] The above-mentioned optoelectronic isolation interface includes a first optoelectronic isolation interface chip, a second optoelectronic isolation interface chip and an isolation driver chip. The first input port of the first optoelectronic isolation interface chip is connected to the I / O port of the DSP controller, the second input port of the first optoelectronic isolation interface chip is connected to the input pulse signal, and the output end of the first optoelectronic isolation interface chip is connected to the adjustable bias three-state drive circuit; the first input port of the second optoelectronic isolation interface chip is connected to an external high-level or low-level signal, the second input port of the second optoelectronic isolation interface chip is connected to the inverted signal of the input pulse signal, and the output end of the second optoelectronic isolation interface chip is connected to the adjustable bias three-state drive circuit; the input port of the isolation driver chip is connected to the input pulse signal, and the output end of the isolation driver chip is connected to the low-resistance electronic switch array.

[0009] The above-mentioned adjustable bias three-state drive circuit includes a first three-state drive chip, a second three-state drive chip, a first pull-up resistor, a second pull-up resistor, a first output drive resistor and a second output drive resistor, wherein the input end of the first three-state drive chip is connected to the output end of the first optoelectronic isolation interface chip via the first pull-up resistor, and the output end of the first three-state drive chip is connected to the gate of the device under test via the first output drive resistor; the input end of the second three-state drive chip is connected to the output end of the second optoelectronic isolation interface chip via the second pull-up resistor, and the output end of the second three-state drive chip is connected to the gate of the device under test via the second output drive resistor.

[0010] The low-resistance electronic switch array includes three parallel-connected low-on-resistance SiMOSFETs. The drain of the SiMOSFET is connected to the source of the device under test, and its source is connected to the negative pole of the DC bus. The gate of each SiMOSFET is connected to the optoelectronic isolation interface through a driving resistor.

[0011] A method for testing the third quadrant characteristics of a SiC MOSFET taking into account a channel dynamic response comprises the following steps:

[0012] Step 1: Apply pre-conditioning stimulus to the gate of the device under test, SiC MOSFET, so that the channel of the device under test enters an active state;

[0013] Step 2: Apply test excitation to the device under test to obtain third quadrant current data;

[0014] Step 3: Adjust the gate-source voltage bias and drain-source voltage bias, and repeat steps 1-2 to obtain multiple sets of third-quadrant current data corresponding to different gate-source voltage biases and source-drain voltage biases, that is, the third-quadrant characteristics of the SiC MOSFET considering the dynamic response of the channel.

[0015] The test method further includes, when adjusting the gate-source voltage bias and the drain-source voltage bias, simultaneously adjusting the temperature bias of the device under test.

[0016] After adopting the above solution, the present invention sets the photoelectric isolation interface chip U 1-1 Receives the command signal from DSP and connects to the three-state driver chip U with adjustable bias 1-2 Cooperate to realize the pre-treatment excitation of the SiC MOSFET under test, so that the device channel enters the activation state and the gate oxide interface carrier movement enters the dynamic balance; chip U 2-1 with U 2-2 Cooperate to realize the test stimulus for the device under test; the isolation driver chip U3 is responsible for turning on the low-resistance electronic switch array to ensure that the DC voltage V dc This voltage is applied across the DUT, generating a third-quadrant current. By adjusting the preconditioning voltage and the excitation voltage, third-quadrant characteristic data can be obtained that takes into account the dynamic response of the channel. This test method, through the preconditioning step, accounts for the conductivity hysteresis caused by channel interface state effects, significantly improving measurement accuracy.

[0017] The beneficial effects of the present invention are as follows: by adding a pre-processing excitation link, the present invention can restore the operating characteristics of the device in the actual operation of the converter to the greatest extent, reduce the measurement error caused by interface state traps, and improve the test accuracy of the third quadrant characteristics, which helps device manufacturers and users to accurately evaluate the characteristics of devices and converters. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1It is a test circuit diagram of the present invention;

[0019] Figure 2 It is the equivalent circuit diagram of the test circuit;

[0020] Figure 3 It is the signal timing diagram and the excitation waveform diagram;

[0021] Figure 4 It is the excitation waveform diagram under different driving conditions;

[0022] Figure 5 This is a schematic diagram of the third quadrant characteristics of the tested SiC MOSFET. DETAILED DESCRIPTION

[0023] The technical solutions and beneficial effects of the present invention will be described in detail below with reference to the accompanying drawings and specific embodiments.

[0024] The present invention provides a SiC MOSFET third quadrant characteristic test circuit considering the dynamic response of the channel, comprising a photoelectric isolation interface, an adjustable bias three-state drive circuit, a low-resistance electronic switch array, and a device under test interface. The photoelectric isolation interface input end is connected to the DSP controller I / O port, the output end is connected to the adjustable bias three-state drive circuit and the input end of the low-resistance electronic switch array, and the output end of the adjustable bias three-state drive circuit is connected to the gate of the device under test; the photoelectric isolation interface is used to receive various command signals from the DSP, reduce the risk of system interference and malfunction by means of photoelectric isolation, and convert the digital signal level of the DSP into a signal for the subsequent drive circuit. Identifiable input level; the adjustable bias three-state circuit is used to drive the SiCMOSFET under test. It receives the command signal transmitted from the optoelectronic isolation interface and has three outputs: high-level voltage, low-level voltage, and high-resistance, corresponding to the three states of the device under test: on, off, and gate floating; the low-resistance electronic switch array is used to control whether the test excitation voltage is connected between the source and drain of the device under test. If the array is turned on, the device under test will generate source-drain current, otherwise it will not; the device under test interface is used to connect the device under test to the surrounding circuit and can freely adjust the device's case temperature.

[0025] Wherein, the photoelectric isolation interface includes a photoelectric isolation interface chip U 1-1 、U 2-1 And isolation driver chip U3, U 1-1 The No. 1 input port is connected to the V1 signal of the DSP, and the No. 2 input port is connected to the V EN Connected, U 2-1 Port 1 is connected to V2, and port 2 is connected to V EN The inverting signal of U3 is connected to the input port of V EN Connected; U 1-1 、U 2-1The typical optoelectronic isolation interface chip TLP2168 is used, which has two independent input / output channels. When the photoelectric LED of a certain input channel is lit, the output of the corresponding channel outputs a low-level voltage through an open-drain structure. Conversely, when the LED is off, the output outputs a high-level voltage through a pull-up resistor. The high-level voltage value is the pull-up voltage value. Due to the limited output current capability of TLP2168, it cannot directly drive SiCMOSFET and needs to be used in conjunction with a driver chip. U3 uses the typical isolation driver chip ACPL-W349, which has an optocoupler structure between the input and output sides. The output side has a bunch of complementary push-pull circuit structures, which can be used to directly drive SiCMOSFET. When the input photoelectric LED is lit, the push-pull output is V cc The output is a high-level voltage at the GND terminal, otherwise the output is a low-level voltage at the GND terminal.

[0026] V1 is a square wave signal with fixed frequency and duty cycle, V EN is a pulse signal with adjustable width, V2 is a constant high or low level signal, and the chip U 1-1 、U 2-1 The negative poles of the input terminals of U3 are both connected to the ground of the DSP.

[0027] The adjustable bias three-state drive circuit includes a three-state drive chip U 1-2 、U 2-2 , external adjustable regulated power supply V GG1-S 、V EE1-S 、V GG2-S 、V EE2-S , pull-up resistor R up , output drive resistance R g1 、R g2 , its input terminals are respectively 1-1 、U 2-1 The output terminals are connected to the gate of the device under test through driving resistors. 1-2 、U 2-2 The typical three-state driver chip, IXDD609SI, features two inputs (IN and EN), one output (OUT), and positive and negative power supply terminals. When EN is low, OUT is in a high-impedance state. When EN is high, the chip is enabled. If IN is high, OUT outputs a positive supply voltage, and vice versa. Adjusting the chip's supply voltage adjusts the OUT output voltage. Clearly, the device under test has three driven states: on, off, and with the gate floating.

[0028] The low-resistance electronic switch array includes three parallel-connected low-on-resistance Si MOSFETs, each of which has a gate connected to a driving resistor. The drain of the SiMOSFET is connected to the source of the device under test, and its source is connected to the negative pole of the DC bus. All Si MOSFETs are driven by the isolation driver chip U3.

[0029] The device under test interface is used to connect the SiC MOSFET under test, the low-resistance electronic switch array, and the external DC regulated power supply V dc , the DC bus positive pole is connected to the drain of the device under test, the negative pole is connected to the source of the electronic switch, and the bus capacitance C dc Connect in parallel with V dc Between the positive and negative electrodes, the heating platform is responsible for regulating the device junction temperature T c .

[0030] The present invention also provides a method for testing the third quadrant characteristics of a SiC MOSFET taking into account the dynamic response of the channel, comprising the following steps:

[0031] Step 1: Apply pre-conditioning stimulus to the SiC MOSFET gate to activate the device channel.

[0032] Step 2: Apply test excitation to the device under test to obtain third quadrant current data;

[0033] Step 3: Adjust the gate-source voltage and source-drain voltage bias. The user selects the voltage bias step size based on the resolution requirements for the device's third quadrant characteristics. It is recommended to set the gate-source voltage step size to 2V and the source-drain voltage bias step size to 0.5V. In addition, during the test, it is necessary to ensure that the source-drain current does not exceed the rated value of the device to ensure that the device does not fail due to overcurrent.

[0034] Step 4: Repeat steps 1-3 to obtain the source-drain current values of the device under different gate-source voltages and source-drain voltage biases, that is, the third quadrant characteristics of the SiC MOSFET considering the dynamic response of the channel.

[0035] Chip U 1-1 and U 1-2 Cooperate to realize the gate voltage pre-processing excitation of the SiC MOSFET under test, and continuously apply square wave excitation to the gate of the device. The high level is V GG1-S , low level is V EE1-S , Chip U 2-1 and U 2-2 Cooperate to realize the test excitation of the SiC MOSFET under test. The optional test voltage is V GG2-S or V EE2-S First, by V ENSelect whether to apply gate voltage preconditioning stimulus or test stimulus to the SiC MOSFET under test. When gate voltage preconditioning stimulus is applied, V EN When the test stimulus is applied, V EN is high level.

[0036] Three parallel Si MOSFETs are driven simultaneously by chip U3, and a source-drain voltage V is applied to the SiC MOSFET under test during the test. dc To obtain the third quadrant current I SD .

[0037] Adjust the source-drain bias V of the device under test SD , gate-source bias V GS and temperature bias T c , repeat the above test steps to obtain the complete third quadrant characteristics.

[0038] In this embodiment of the present invention, a single optoelectronic isolation interface chip and a tri-state driver chip form a single driver module. Two sets of driver module outputs are connected in parallel to the gate of the SiC MOSFET under test. The first set of driver modules applies gate voltage preconditioning stimulus to the device under test, while the second set of driver modules applies test stimulus to the device under test. Both the positive and negative drive voltages of each driver module are adjustable, with the values determined by the user based on the actual converter settings. The switching between gate voltage preconditioning stimulus and test stimulus is determined by the enable pin of the tri-state driver chip.

[0039] After the gate voltage pre-conditioning excitation causes the channel of the device under test to enter the activated state, the test excitation is applied. That is, the isolation driver chip excites the low-resistance electronic switch array and applies a fixed DC pulse to the source and drain of the device under test to generate source-drain current. The current is read and recorded, and the above operation is repeated.

[0040] This test method can realize the third-quadrant characteristic test of SiC MOSFET taking into account the dynamic response of the channel. Specifically, the gate voltage preconditioning excitation simulates the switching state of the device before natural commutation or synchronous rectification, ensuring that the current data obtained by the test excitation has sufficient accuracy.

[0041] During the test, the SiC MOSFET is heated to a certain value T by the heating platform. c And ensure sufficient thermal balance. According to the actual working condition of the converter, the external adjustable regulated power supply V GG1-S 、V EE1-S 、V GG2-S 、V EE2-S Value. V GG1-S is the positive gate voltage for the gate voltage pre-conditioning excitation of the device, V EE1-S is the negative gate voltage for the gate voltage preconditioning of the device, V GG2-Sis the positive bias of the device gate voltage test stimulus, V EE2-S It is the negative bias of the device gate voltage test stimulus. During the test, V GG2-S and V EE2-S Choose only one.

[0042] Figure 2 This is the equivalent circuit diagram of the test platform. a is the gate voltage test excitation signal, which is equal to V GG2-S or V EE2-S . V b It is the gate voltage pre-processing excitation signal, which is high level V GG1-S , low level V EE1-S AC square wave. V EN The switching signal controls the closing / opening of switch S1 and the switching of switch S2. When the S2 switch selects V2 and the S1 switch is open, a gate voltage pre-conditioning stimulus is applied to the device under test to simulate the switching behavior of the SiC MOSFET in the converter. At this time, the channel enters a dynamic equilibrium stage, and the number of electrons / holes captured and discharged at the gate oxide interface is stable. When the S2 switch selects V1 and the S1 switch is closed, a test stimulus is applied to the device under test, and a DC voltage V is connected to the source and drain of the device. dc , read the third quadrant current I SD .

[0043] Figure 3 It is the signal timing diagram and excitation waveform diagram. V1 is a square wave excitation, and its duty cycle and frequency are determined according to the actual working conditions of the converter. V2 is kept at a high level or a low level. EN From low level to high level, the test circuit enters the test stage from the pre-processing stage. EN From high level to low level, the test circuit returns to the pre-processing stage and waits for the next test stage. In the pre-processing stage, the gate-source voltage V GS V GG1-S and V EE1-S Alternating square wave. During the test phase, V GS V GG2-S and V EE2-S First, at the end of the test phase, read the source-drain current I of the device. SD And record.

[0044] Figure 4 The excitation waveforms under different driving conditions show that the amplitude, frequency and duty cycle of the pre-processing excitation can be set according to the actual needs of the user. By adding gate voltage pre-processing excitation, the actual working conditions of the converter are restored to the greatest extent.

[0045] Figure 5Schematic diagram of the third quadrant characteristics of the tested SiC MOSFET. Fixed a certain pre-processing condition and fixed the test excitation amplitude, changing the DC voltage V dc And record I SD By adjusting the test excitation amplitude and repeating the above steps, the third quadrant characteristics at different gate-source voltages can be obtained. By adjusting the heater set temperature and repeating the above steps, the third quadrant characteristics at different junction temperatures can be obtained.

[0046] It will be understood by those skilled in the art that the embodiments of the present invention may be provided as methods, systems, or computer program products. Therefore, the present invention may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Furthermore, the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code. The solutions in the embodiments of the present invention may be implemented in various computer languages, for example, the object-oriented programming language Java and the interpreted scripting language JavaScript.

[0047] The present invention is described with reference to flowcharts and / or block diagrams of methods, devices (systems), and computer program products according to embodiments of the present invention. It should be understood that each process and / or block in the flowcharts and / or block diagrams, as well as combinations of processes and / or blocks in the flowcharts and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowcharts and / or block diagrams. Figure 1 a process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0048] These computer program instructions may also be stored in a computer readable memory that can direct a computer or other programmable data processing device to work in a specific manner, so that the instructions stored in the computer readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 a process or multiple processes and / or boxes Figure 1 The function specified in one or more boxes.

[0049] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operational steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing the instructions executed on the computer or other programmable device for implementing the process. Figure 1 a process or multiple processes and / or boxes Figure 1 A step that specifies a function in one or more boxes.

[0050] Although the preferred embodiments of the present invention have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present invention.

[0051] Obviously, those skilled in the art may make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if such changes and modifications fall within the scope of the claims and their equivalents, the present invention is intended to include such changes and modifications.

Claims

1. A SiC MOSFET third quadrant characteristic test circuit considering channel dynamic response, characterized by: The device comprises an optoelectronic isolation interface, an adjustable bias three-state drive circuit, and a low-resistance electronic switch array. The optoelectronic isolation interface has an input connected to an I / O port of a DSP controller and an output connected to the input of the adjustable bias three-state drive circuit. The optoelectronic isolation interface converts the digital signal level of the DSP controller into an input level recognizable by the adjustable bias three-state drive circuit and sends the converted signal to the adjustable bias three-state drive circuit. The output of the adjustable bias three-state drive circuit is connected to the gate of the device under test and outputs a high-level voltage, a low-level voltage, or a high-resistance signal according to the input level. The output of the optoelectronic isolation interface is also connected to the input of the low-resistance electronic switch array and converts the command signal of the DSP controller into an input level recognizable by the low-resistance electronic switch array and sends the converted signal to the low-resistance electronic switch array. The low-resistance electronic switch array is turned on or off under the control of the input level. When the low-resistance electronic switch array is turned on, a test excitation voltage is applied between the source and drain of the device under test, causing the device under test to generate a source-drain current. Otherwise, no current is generated.

2. The test circuit according to claim 1, wherein: The photoelectric isolation interface includes a first photoelectric isolation interface chip, a second photoelectric isolation interface chip and an isolation driver chip, wherein a first input port of the first photoelectric isolation interface chip is connected to an I / O port of the DSP controller, a second input port of the first photoelectric isolation interface chip is connected to an input pulse signal, and an output end of the first photoelectric isolation interface chip is connected to an adjustable bias three-state driver circuit; The first input port of the second photoelectric isolation interface chip is connected to an external high-level or low-level signal, the second input port of the second photoelectric isolation interface chip is connected to an inverted signal of the input pulse signal, and the output end of the second photoelectric isolation interface chip is connected to an adjustable bias three-state drive circuit; The input port of the isolation driving chip is connected to the input pulse signal, and the output end of the isolation driving chip is connected to the low-resistance electronic switch array.

3. The test circuit according to claim 2, wherein: The adjustable bias three-state drive circuit includes a first three-state drive chip, a second three-state drive chip, a first pull-up resistor, a second pull-up resistor, a first output drive resistor, and a second output drive resistor, wherein the input end of the first three-state drive chip is connected to the output end of the first optoelectronic isolation interface chip via the first pull-up resistor, and the output end of the first three-state drive chip is connected to the gate of the device under test via the first output drive resistor; the input end of the second three-state drive chip is connected to the output end of the second optoelectronic isolation interface chip via the second pull-up resistor, and the output end of the second three-state drive chip is connected to the gate of the device under test via the second output drive resistor.

4. The test circuit according to claim 1, wherein: The low-resistance electronic switch array includes three parallel-connected low-on-resistance Si MOSFETs, the drain of the Si MOSFET is connected to the source of the device under test, and the source is connected to the negative pole of the DC bus. The gate of each Si MOSFET is connected to the optoelectronic isolation interface via a driving resistor.

5. A method for testing the third quadrant characteristics of SiC MOSFET considering the dynamic response of the channel, characterized in that The steps include: Step 1: Apply pre-conditioning stimulus to the gate of the device under test, SiC MOSFET, so that the channel of the device under test enters an active state; Step 2: Apply test excitation to the device under test to obtain third quadrant current data; Step 3: Adjust the gate-source voltage bias and drain-source voltage bias, and repeat steps 1-2 to obtain multiple sets of third-quadrant current data corresponding to different gate-source voltage biases and source-drain voltage biases, that is, the third-quadrant characteristics of the SiC MOSFET considering the dynamic response of the channel.

6. The testing method according to claim 5, wherein: The method also includes adjusting the temperature bias of the device under test simultaneously when adjusting the gate-source voltage bias and the drain-source voltage bias.

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