A self-diagnosis method and system for passive balancing circuit

Abstract

This invention discloses a self-diagnostic method and system for a passive balancing circuit, belonging to the field of circuit diagnostic technology. The invention constructs a self-diagnostic circuit by connecting a balancing state diagnostic resistor in series between the balancing resistor and the voltage acquisition input terminal. It transforms short-circuit faults in the passive balancing circuit into intuitive voltage data changes, freeing the diagnostic process from traditional complex detection methods. By simply comparing the voltage of a single cell after each balancing cycle is turned on and off with the voltage before the last balancing cycle, short-circuit faults can be quickly and accurately located based on a preset voltage ratio, significantly improving diagnostic efficiency and accuracy. The self-diagnostic circuit can acquire cell voltages when the passive balancing circuit is not in operation, and also acquires voltages after each balancing cycle is turned on and off, covering different circuit operating states. This enables real-time monitoring of the passive balancing circuit throughout its entire lifecycle, effectively preventing safety accidents and applicable to various BMS systems employing passive balancing schemes.

Description

Technical Field

[0001] This invention belongs to the field of circuit diagnostic technology, and specifically relates to a self-diagnostic method and system for passive equalization circuits. Background Technology

[0002] The replacement of lead-acid batteries with lithium batteries as backup power for communication base stations has become a major trend. Compared with lead-acid batteries, lithium batteries have significant advantages such as higher energy density, larger discharge-charge rate, and the ability to operate at relatively high temperatures. With the widespread adoption of lithium batteries in recent years, actual battery modules are high-voltage, high-capacity systems composed of individual cells connected in parallel and series. To solve the consistency problem between different strings in long-term use, BMS products on the market usually use passive balancing solutions.

[0003] In lithium-ion battery management systems (BMS), inconsistencies between cells can affect battery performance and cycle life. However, existing passive balancing technologies have several drawbacks. On the one hand, current passive balancing methods lack diagnostics for the state of the balancing transistors. If a short-circuit fault occurs in the balancing transistor, the BMS cannot detect and warn in time, leading to a constantly open balancing circuit, prolonged over-discharge of the cells, irreversible damage, economic losses, and even safety accidents.

[0004] On the other hand, existing methods for diagnosing the state of equalization transistors, such as detection by adding optocouplers, require adding an optocoupler to each cell and configuring a separate I / O port at the receiver, which not only makes the circuit complex but also increases the cost of the devices. Summary of the Invention

[0005] To address the aforementioned problems, this invention discloses a self-diagnostic method for a passive equalization circuit, comprising:

[0006] A self-diagnostic circuit is formed by connecting a balancing resistor in the passive balancing circuit and a balancing state diagnostic resistor connected to the voltage acquisition input terminals of the individual cells.

[0007] The voltage of each individual cell is collected using the voltage acquisition input terminal in the self-diagnostic circuit when the passive equalization circuit is not activated, and the voltage VT1 of the individual cell is collected after each equalization is activated and deactivated.

[0008] The current cell voltage VT1 is compared with the cell voltage VT0 collected before the last equalization was activated. When VT1 and VT0 meet the preset voltage ratio, a short circuit fault is diagnosed in the passive equalization circuit.

[0009] Furthermore, the resistance value of the equalization state diagnostic resistor is the same as the resistance value of the acquisition input current limiting resistor in the passive equalization circuit.

[0010] Furthermore, the preset voltage ratio relationship includes:

[0011] 0.4 × previous single cell voltage VT0 ≤ current single cell voltage VT1 ≤ 0.6 × previous single cell voltage VT0.

[0012] Furthermore, the self-diagnostic method also includes setting a verification mechanism, which involves performing multi-cycle review and verification when diagnosing a short-circuit fault in the passive equalization circuit.

[0013] Furthermore, the method also includes setting an alarm mechanism, which triggers an alarm and notifies maintenance personnel when a short circuit fault occurs in the diagnostic result equalization circuit.

[0014] On the other hand, the present invention proposes a self-diagnostic system for a passive equalization circuit, comprising:

[0015] The self-diagnostic circuit includes a passive equalization circuit with an equalization resistor and a voltage acquisition input terminal connected to the positive and negative terminals of a single cell, as well as an equalization state diagnostic resistor connected in series between the equalization resistor and the voltage acquisition input terminal.

[0016] The acquisition chip is used to acquire the voltage VT0 of each cell when the passive equalization circuit is not turned on, and the voltage VT1 of the cell after each equalization is turned on and off.

[0017] The control diagnostic unit is used to compare the current cell voltage VT1 with the cell voltage VT0 collected before the last equalization was turned on. When VT1 and VT0 meet the preset voltage ratio, the passive equalization circuit is diagnosed as having a short circuit fault.

[0018] Furthermore, the voltage acquisition input terminal includes a positive voltage acquisition input terminal connected to the positive terminal of a single cell and a negative voltage acquisition input terminal connected to the negative terminal of a single cell. The equalization state diagnostic resistor is connected in series between the equalization diagnostic resistor and the positive voltage acquisition input terminal, and the other end of the equalization resistor is connected to the positive terminal of the cell.

[0019] Furthermore, the self-diagnostic circuit also includes a core equalization circuit and a voltage divider network;

[0020] The core equalization circuit consists of an equalization resistor and an equalization transistor connected in series. One end of the equalization resistor is connected to the positive terminal of a single cell, and the other end is connected to the collector of the equalization transistor.

[0021] The voltage divider network includes a positive input current-limiting resistor, a negative input current-limiting resistor, an equalization drive current-limiting resistor, and an input filter capacitor.

[0022] The positive electrode acquisition input current limiting resistor is connected in series between the positive electrode of the single cell and the corresponding positive electrode voltage acquisition input terminal.

[0023] The negative electrode acquisition input current-limiting resistor is connected in series between the negative electrode of the single cell and the corresponding negative electrode voltage acquisition input terminal.

[0024] One end of the equalization drive current-limiting resistor is connected to the base of the equalization transistor, and the other end is connected to the negative voltage acquisition input terminal.

[0025] The input filter capacitor is connected in parallel between the positive voltage acquisition input terminal and the negative voltage acquisition input terminal.

[0026] Furthermore, the resistance value of the equalization state diagnostic resistor in the self-diagnostic circuit is the same as the resistance values ​​of the positive input current limiting resistor and the negative input current limiting resistor.

[0027] Furthermore, the control diagnostic unit has a built-in verification mechanism: when the fault diagnosis module diagnoses a short circuit fault in the passive equalization circuit, the fault diagnosis module is activated to perform multi-cycle review and verification.

[0028] Furthermore, the equalization transistor includes an NPN transistor, a PNP transistor, an N-type metal-oxide-semiconductor (NMOS) transistor, or a P-type metal-oxide-semiconductor (PMOS) transistor.

[0029] The beneficial effects of this invention are:

[0030] This invention constructs a unique self-diagnostic circuit by connecting a balancing state diagnostic resistor in series between the balancing resistor and the voltage acquisition input terminal. It transforms short-circuit faults in the passive balancing circuit into intuitive voltage data changes, freeing the diagnostic process from traditional complex detection methods. By simply comparing the voltage of a single cell after each balancing cycle is initiated and discontinued with the voltage before the last balancing cycle, short-circuit faults can be quickly and accurately located based on a preset voltage ratio, significantly improving diagnostic efficiency and accuracy. The self-diagnostic circuit can acquire cell voltages when the passive balancing circuit is not initiated, and also after each balancing cycle is initiated and discontinued, covering different states of circuit operation and achieving real-time monitoring of the passive balancing circuit throughout its entire lifecycle. Compared to detection only under specific operating conditions, this continuous monitoring mechanism can promptly capture early signs of faults, provide early warning of potential short-circuit risks, and provide a solid guarantee for the safe operation of the circuit. This invention enables timely diagnosis and early warning of short-circuit faults in the balancing circuit, identifies abnormal battery modules and BMS, prevents the continued deterioration of battery module consistency leading to unusable batteries, reduces losses, and avoids direct economic losses caused by over-discharge of cells. Meanwhile, early warning and intervention can prevent safety accidents caused by long-term lack of maintenance due to over-discharge of battery cells, and ensure the safe and stable operation of lithium batteries.

[0031] Other features and advantages of the present invention will be described in the following description, and in part will become apparent from the description, or will be understood by practicing the present invention. The purpose and other advantages of the present invention can be realized and obtained by the structures pointed out in the description, claims and drawings. Attached Figure Description

[0032] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following is a brief introduction to the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0033] Figure 1 A schematic diagram of the passive equalization circuit in an embodiment of the present invention is shown;

[0034] Figure 2 This diagram illustrates a circuit diagram of adding an optocoupler to a passive equalization circuit for circuit diagnosis in an embodiment of the present invention.

[0035] Figure 3 A flowchart of a self-diagnostic method for a passive equalization circuit proposed in an embodiment of the present invention is shown;

[0036] Figure 4 This diagram illustrates a circuit diagram of adding an equalization state diagnostic resistor to the passive equalization circuit for circuit diagnosis in an embodiment of the present invention.

[0037] Figure 5 This diagram illustrates the passive equalization circuit in an embodiment of the present invention when the switching transistor in the passive equalization circuit is a MOS.

[0038] Figure 6 The diagram shows a passive equalization circuit in an embodiment of the present invention when the switching transistor in the passive equalization circuit is a PNP transistor. Detailed Implementation

[0039] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0040] by Figure 1The passive equalization circuit shown is illustrated, including the battery cell, resistors, capacitors, transistors, and voltage sampling input. The diagram uses the first battery cell as an example; the positive terminal is B1, and the negative terminal is B0.

[0041] The voltage acquisition input terminals include VC1 acquisition input terminal (VC1) and VC0 acquisition input terminal (VC0), which are used to acquire the voltages of B1 and B0.

[0042] The resistors include the input current-limiting resistor, the equalization resistor, and the equalization drive current-limiting resistor, specifically including:

[0043] B1 Input Current Limiting Resistor (RA1): One end of RA1 is connected to B1, and the other end is connected to VC1. It is used to limit the current flowing into VC1.

[0044] Equalizing resistor (RB1): One end of RB1 is connected to B1, and the other end is connected to the collector of the equalizing transistor (Q1), which serves as the equalizing circuit.

[0045] Equalization drive current limiting resistor (RD1): One end of RD1 is connected to the base of Q1, and the other end is connected to the input filter capacitor (CA1) of VC1.

[0046] B0 sampling input current limiting resistor (RA0): One end of RA0 is connected to B0, and the other end is connected to VC0, limiting the current flowing into VC0.

[0047] The VC1 input filter capacitor (CA1) is connected to VC0 at one end and to VC1 at the other end, and is used to filter out noise in the VC1 input signal.

[0048] The transistor (Q1) has its collector connected to RB1, its emitter connected to B0, and its base connected to RD1. The conduction and cutoff between the collector and emitter are controlled by the base current, thereby achieving functions such as circuit balance control.

[0049] When the voltage of the first cell reaches a high enough level to trigger equalization, the acquisition IC activates the equalization process for the first cell. The voltage of VCO becomes higher than that of B0, causing Q1 to conduct. At this time, RB1 is connected to the circuit, flowing through Q1 and into the terminals B0 and B1 of the first cell. The current flowing through RB1 consumes the charge of the first cell, reducing its voltage and capacity, thus achieving equalization. If Q1 is disconnected, the connection between RB1 and the cell is broken, and the equalization process stops. To achieve diagnostics, the circuit needs further expansion and control logic design.

[0050] The above circuit design only requires a diagnostic resistor in each battery cell, eliminating the need for optocouplers, thus saving on separate I / O ports for detection, resulting in a simple layout and no overhead on the MCU's hardware resources. For example, if the passive equalization circuit's diagnostics are implemented by adding an optocoupler (U18), the circuit design would be as follows: Figure 2As shown, U18 is added to the existing circuit. The input terminals of U18 (pins 1 and 2) are connected as follows: pin 1 is connected to B1 via RA1, and pin 2 is connected to the collector of QB1. The output terminals of U18 (pins 3 and 4) are connected as follows: pin 3 is grounded, and pin 4 outputs an electrical signal (e.g., 3.3V) to the AD port, which is subsequently connected to the processing unit (not shown in detail). In addition, there are auxiliary components such as resistors R1 and R2. One end of R2 is connected between the output terminal of U18 and the AD port, and the other end is grounded. One end of R1 is connected to the input terminal of U18, and the other end is connected to the connection point of RA1 and VC1.

[0051] The impact of component switching on and off on the circuit: Under normal circumstances, when Q1 is on, current flows through the input of U18, the optocoupler is on, and the AD port receives a 3.3V signal. If Q1 is short-circuited, U18 will continue to conduct, and the AD port will continuously output a 3.3V signal. This signal can be converted into visual signals such as sound and light to provide early warning of equalization circuit faults. If Q1 is off normally, U18 is off, and the AD port has no 3.3V signal input (assuming no other interference). However, this method requires an additional optocoupler and a separate I / O port for each battery cell, resulting in higher costs and a more complex circuit.

[0052] Based on the circuit design that eliminates the need for optocouplers, this embodiment proposes a self-diagnostic method for passive equalization circuits. This method involves adding an equalization state diagnostic resistor to the passive equalization circuit, such as... Figure 3 As shown, it includes the following steps:

[0053] A self-diagnostic circuit is formed by connecting a balancing resistor in the passive balancing circuit and a balancing state diagnostic resistor connected to the voltage acquisition input terminals of the individual cells in series. Specifically, the balancing state diagnostic resistor is used to divide the voltage input to the individual cells. By monitoring the voltage change across the balancing state diagnostic resistor and combining the different states when balancing is on and off, it is determined whether the passive balancing circuit is working properly.

[0054] The voltage of each individual cell is acquired using the voltage acquisition input terminal in the self-diagnostic circuit when the passive equalization circuit is not activated, and the voltage VT1 of the individual cell is acquired after each equalization is activated and deactivated; and the acquired voltage signal is input to the acquisition chip.

[0055] The current cell voltage VT1 is compared with the cell voltage VT0 collected before the last equalization was initiated. When VT1 and VT0 meet a preset voltage ratio, a short circuit fault in the passive equalization circuit is diagnosed. The preset voltage ratio includes: current cell voltage VT1 = (0.8~1.2) times 1 / 2 of the previous cell voltage VT0, that is, 0.4 × previous cell voltage VT0 ≤ current cell voltage VT1 ≤ 0.6 × previous cell voltage VT0.

[0056] The self-diagnostic method also includes setting a verification mechanism and an alarm mechanism. The verification mechanism is to perform multi-cycle review and verification when a short circuit fault is diagnosed in the passive equalization circuit. The alarm mechanism is to trigger an alarm and notify maintenance personnel when the diagnosis result indicates that a short circuit fault has occurred in the passive equalization circuit.

[0057] Based on the same inventive concept as the above self-diagnosis method, this embodiment proposes a passive equalization self-diagnosis system, including:

[0058] The self-diagnostic circuit includes a passive equalization circuit with an equalization resistor and a voltage acquisition input terminal connected to the positive and negative terminals of a single cell, as well as an equalization state diagnostic resistor connected in series between the equalization resistor and the voltage acquisition input terminal.

[0059] The acquisition chip is used to acquire the voltage VT0 of each cell when the passive equalization circuit is not turned on, and the voltage VT1 of the cell after each equalization is turned on and off.

[0060] The control diagnostic unit compares the current cell voltage VT1 with the cell voltage VT0 collected before the last equalization was initiated. When VT1 and VT0 meet a preset voltage ratio, a short-circuit fault is diagnosed in the passive equalization circuit. The preset voltage ratio includes:

[0061] The voltage of this single cell is (0.8~1.2) times half of the voltage of the previous single cell VT0.

[0062] Specifically, the control diagnostic unit has a built-in verification mechanism: when the fault diagnosis module diagnoses a short circuit fault in the passive equalization circuit, the fault diagnosis module is activated to perform multi-cycle review and verification.

[0063] The self-diagnostic system also includes a monitoring terminal for receiving diagnostic results from the control diagnostic unit, monitoring the short-circuit fault status of the passive equalization circuit, and forming a complete monitoring and control loop. An alarm mechanism is also set up; specifically, when the fault diagnosis module diagnoses a short-circuit fault in the passive equalization circuit, the alarm module is activated to trigger an alarm and notify maintenance personnel. Specifically, after a short-circuit fault in the equalization circuit is diagnosed, a combination of a specific audible and visual alarm system or a dedicated protocol alarm is used to notify maintenance personnel to intervene.

[0064] The self-diagnostic circuit also includes a core equalization circuit and a voltage divider network;

[0065] The core equalization circuit consists of an equalization resistor and an equalization transistor connected in series. One end of the equalization resistor is connected to the positive terminal of a single cell, and the other end is connected to the collector of the equalization transistor.

[0066] The voltage divider network includes a positive input current-limiting resistor, a negative input current-limiting resistor, an equalization drive current-limiting resistor, and an input filter capacitor.

[0067] The positive electrode acquisition input current limiting resistor is connected in series between the positive electrode of the single cell and the corresponding positive electrode voltage acquisition input terminal.

[0068] The negative electrode acquisition input current-limiting resistor is connected in series between the negative electrode of the single cell and the corresponding negative electrode voltage acquisition input terminal.

[0069] One end of the equalization drive current-limiting resistor is connected to the base of the equalization transistor, and the other end is connected to the negative voltage acquisition input terminal.

[0070] The input filter capacitor is connected in parallel between the positive voltage acquisition input terminal and the negative voltage acquisition input terminal.

[0071] In an exemplary embodiment of the present invention, the self-diagnostic circuit is as follows: Figure 4 As shown, the self-diagnostic circuit includes a passive equalization circuit with an equalization resistor (RB1) and a voltage acquisition input terminal (VC1) connected to the positive terminal B1 of a single cell, as well as an equalization state diagnostic resistor (RC1) connected in series between RB1 and VC1. The positive terminal of a single cell is B1, and the negative terminal is B0. The core equalization circuit consists of an equalization resistor (RB1) and an equalization transistor (Q1) connected in series. One end of RB1 is connected to B1, and the other end is connected to B0 through Q1. When Q1 is turned on, RB1 is connected to the circuit, consuming the charge of B1 and reducing its voltage, thus achieving equalization. The collector of Q1 is connected to RB1, the emitter is connected to B0, and the base is connected to RB1. The base current controls the conduction and cutoff between the collector and emitter, realizing the circuit's equalization control and other functions.

[0072] The voltage acquisition input terminal includes a VC1 acquisition input terminal (VC1) and a VC0 acquisition input terminal (VC0). VC1 is connected to B1 and VC0 is connected to B0, and is used to acquire the voltage of B1.

[0073] The voltage divider network includes an input current-limiting resistor (RA1), an input current-limiting resistor (RA0), an equalization drive current-limiting resistor (RD1), and a VC1 input filter capacitor (CA1). RC1 is connected in series between RB1 and VC1, with the same resistance value as RA0 and RA1. One end of RA1 is connected to B1, and the other end is connected to VC1 to limit the current flowing into VC1. One end of RB1 is connected to B1, and the other end is connected to the collector of Q1, serving as an equalization circuit. One end of RD1 is connected to the base of Q1, and the other end is connected to the VC1 input filter capacitor (CA1). One end of RA0 is connected to B0, and the other end is connected to VC0 to limit the current flowing into VC0. The VC1 input filter capacitor (CA1) is connected in parallel with VC1, with one end connected to the connection point between RD1 and the emitter of Q1, and the other end connected to the connection point between RA1 and VC1, used to filter out noise in the VC1 input signal.

[0074] Under normal circumstances, VC1 reflects the real-time voltage VB1 of B1, and VC0 reflects the real-time voltage VB0 of B0. When Q1 is short-circuited, RC1 and RB1 divide the voltage, causing VC1 to become (B1-B0) / 2, forming a characteristic voltage difference. The base of Q1 is connected to the acquisition chip through RD1, and the voltage information obtained by the acquisition chip is transmitted to the control and diagnostic unit for diagnosis. When the signal from the acquisition chip is high, Q1 is turned on, and equalization is enabled; when it is low, it is turned off, and equalization is stopped. The emitter of Q1 is connected to B0, and the collector is connected to RB1. The conduction and cutoff between the collector and emitter are controlled by the base current, realizing the circuit's equalization control and other functions.

[0075] When Q1 is short-circuited and cannot be disconnected, the voltage of VC1 relative to B0 is 1 / 2 (VB1-VB0), and the voltage of VC0 is the same as the voltage of B0 (VB0). That is, the voltage between VC1 and VC0 is half the voltage between B1 and B0.

[0076] During normal BMS operation, when equalization is not enabled, the voltage VT0 of each individual cell is backed up in real time. Each time equalization is enabled and then disabled, the acquired individual cell voltage VT1 is compared with the previously acquired individual cell voltage VT0 before equalization was enabled. If VT1 = 0.8 to 1.2 times 1 / 2VT0, a short circuit fault is diagnosed in the passive equalization circuit. To avoid certain misjudgments, multiple consecutive cycles of review can be performed, and the number of reviews can be defined according to the actual scenario.

[0077] In an exemplary embodiment of the present invention, the equalization transistor Q1 is replaced with a MOS transistor (QB1). In this case, the self-diagnostic circuit of the passive equalization circuit is as follows: Figure 5As shown, the drain (D) of QB1 is connected to one end of RB1, the source (S) is grounded, and the gate (G) is connected to the control signal (such as CAL) through RD1. The connections of other components remain unchanged, such as RC1, RA1, RA0, CA1, etc. Figure 3 same.

[0078] The impact of component switching on and off on the circuit: When the control signal turns on the MOSFET, RB1 is connected to the circuit. Current flows from the battery cell through RB1 and QB1's drain and source terminals to form a loop, consuming battery charge to achieve equalization. Since the loop voltage drop across QB1's drain and source terminals is smaller than that of a transistor, a larger equalization current can be obtained under the same conditions, improving equalization efficiency. When QB1 is turned off, the equalization process stops. If a short-circuit fault occurs in QB1, the circuit voltage characteristics will change. Figure 4 The same applies when a transistor is short-circuited, which changes the voltage relationship between VC1 and VC0.

[0079] Diagnostic Implementation Method: The diagnostic method is also similar to... Figure 4 The basic structure is the same: the acquisition chip and equalization control diagnostic unit collect voltage data from VC0 and VC1, and the software logic determines whether the MOSFET is short-circuited based on a preset voltage relationship. Because the software control and diagnostic logic remains unchanged, the diagnosis is still achieved by monitoring voltage differences and combining this with multi-cycle review.

[0080] In an exemplary embodiment of the present invention, a PNP transistor and a P-type metal-oxide-semiconductor (PMOS) are used as alternatives. In this case, the self-diagnostic circuit of the passive equalization circuit is as follows: Figure 6 As shown, the emitter of the PNP transistor (QB1) is connected to the battery cell, the base is connected to the control signal (such as CAL) via RD1, and the collector is connected to one end of RB1. RC1 is connected between RB1 and other relevant nodes (such as a position similar to VCO). If a PMOS is used instead of QB1, the source of the PMOS is connected to the battery cell, the drain is connected to RB1, and the gate is connected to the control signal.

[0081] The impact of component switching on and off on the circuit: When the control signal turns QB1 on, current flows from the battery cell through QB1 and RB1, consuming battery cell charge for equalization. If QB1 is turned off, equalization stops. If a short-circuit fault occurs in QB1, it will also affect the voltage of related nodes in the circuit, changing the voltage relationship between components like VC1 and VCO (assuming corresponding sampling points). When replacing with a PMOS, the working principle is similar, only the conduction characteristics of the PMOS are different from those of the PNP transistor, but the impact on circuit voltage is consistent in the diagnostic principle.

[0082] Diagnostic implementation method: with Figure 4 , Figure 5The diagnostic method is similar, involving collecting voltage data from relevant nodes (such as VC0 and VC1 collection points) and using software logic to compare the voltages with preset short-circuit fault voltage relationships for judgment. The software's control and diagnostic logic remain unchanged, and multi-cycle review is still used to improve diagnostic accuracy.

[0083] Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A self-diagnostic method for a passive equalization circuit, characterized in that, include: A self-diagnostic circuit is formed by connecting a balancing resistor in the passive balancing circuit and a balancing state diagnostic resistor connected to the voltage acquisition input terminals of the individual cells. The resistance value of the equalization state diagnostic resistor is the same as the resistance value of the current-limiting resistor in the passive equalization circuit. The voltage acquisition input terminal includes a positive voltage acquisition input terminal connected to the positive terminal of the individual cell and a negative voltage acquisition input terminal connected to the negative terminal of the individual cell. The self-diagnostic circuit also includes a core equalization circuit and a voltage divider network. The core equalization circuit consists of an equalization resistor and an equalization transistor connected in series. One end of the equalization resistor is connected to the positive terminal of the individual cell, and the other end is connected to the collector of the equalization transistor. The voltage divider network includes a positive acquisition input current-limiting resistor, a negative acquisition input current-limiting resistor, an equalization drive current-limiting resistor, and an input filter capacitor. The positive acquisition input current-limiting resistor is connected in series between the positive terminal of the individual cell and the corresponding positive voltage acquisition input terminal. The negative acquisition input current-limiting resistor is connected in series between the negative terminal of the individual cell and the corresponding negative voltage acquisition input terminal. One end of the equalization drive current-limiting resistor is connected to the base of the equalization transistor, and the other end is connected to the negative voltage acquisition input terminal. The input filter capacitor is connected in parallel between the positive voltage acquisition input terminal and the negative acquisition input terminal. The voltage of each individual cell is collected using the voltage acquisition input terminal in the self-diagnostic circuit when the passive equalization circuit is not activated, and the voltage VT1 of the individual cell is collected after each equalization is activated and deactivated. The current cell voltage VT1 is compared with the cell voltage VT0 collected before the last equalization was started. When VT1 and VT0 meet the preset voltage ratio, a short circuit fault is diagnosed in the passive equalization circuit. The preset voltage ratio includes: 0.4 × previous cell voltage VT0 ≤ current cell voltage VT1 ≤ 0.6 × previous cell voltage VT0.

2. The self-diagnostic method for the passive equalization circuit according to claim 1, characterized in that, The self-diagnostic method also includes setting a verification mechanism, which involves performing multi-cycle review and verification when diagnosing a short-circuit fault in the passive equalization circuit.

3. The self-diagnostic method for the passive equalization circuit according to claim 1 or 2, characterized in that, The method also includes setting an alarm mechanism, which triggers an alarm and notifies maintenance personnel when a short-circuit fault occurs in the diagnostic result equalization circuit.

4. A self-diagnostic system for a passive equalization circuit, characterized in that, include: The self-diagnostic circuit includes an equalization resistor in a passive equalization circuit and voltage acquisition input terminals connected to the positive and negative terminals of a single battery cell, as well as an equalization state diagnostic resistor connected in series between the equalization resistor and the voltage acquisition input terminals. The resistance value of the equalization state diagnostic resistor is the same as the resistance value of the acquisition input current-limiting resistor in the passive equalization circuit. The voltage acquisition input terminals include a positive voltage acquisition input terminal connected to the positive terminal of the single battery cell and a negative voltage acquisition input terminal connected to the negative terminal of the single battery cell. The self-diagnostic circuit also includes a core equalization circuit and a voltage divider network. The core equalization circuit consists of an equalization resistor and an equalization transistor connected in series, with one end of the equalization resistor... The voltage divider network is connected to the positive terminal of a single battery cell and the collector of the equalization transistor at the other end. It includes a positive input current-limiting resistor, a negative input current-limiting resistor, an equalization drive current-limiting resistor, and an input filter capacitor. The positive input current-limiting resistor is connected in series between the positive terminal of the single battery cell and the corresponding positive voltage input terminal. The negative input current-limiting resistor is connected in series between the negative terminal of the single battery cell and the corresponding negative voltage input terminal. One end of the equalization drive current-limiting resistor is connected to the base of the equalization transistor, and the other end is connected to the negative voltage input terminal. The input filter capacitor is connected in parallel between the positive voltage input terminal and the negative voltage input terminal. The acquisition chip is used to acquire the voltage VT0 of each cell when the passive equalization circuit is not turned on, and the voltage VT1 of the cell after each equalization is turned on and off. The control diagnostic unit is used to compare the current cell voltage VT1 with the cell voltage VT0 collected before the last equalization was turned on. When VT1 and VT0 meet the preset voltage ratio, the passive equalization circuit is diagnosed as having a short circuit fault. The preset voltage ratio includes: 0.4 × previous cell voltage VT0 ≤ current cell voltage VT1 ≤ 0.6 × previous cell voltage VT0.

5. The self-diagnostic system for the passive equalization circuit according to claim 4, characterized in that, The equalization state diagnostic resistor is connected in series between the equalization resistor and the positive voltage acquisition input terminal, and the other end of the equalization resistor is connected to the positive terminal of the battery cell.

6. The self-diagnostic system for the passive equalization circuit according to claim 5, characterized in that, The resistance value of the equalization state diagnostic resistor in the self-diagnostic circuit is the same as the resistance values ​​of the positive input current limiting resistor and the negative input current limiting resistor.

7. The self-diagnostic system for the passive equalization circuit according to any one of claims 4-6, characterized in that, The control diagnostic unit has a built-in verification mechanism: when the fault diagnosis module diagnoses a short circuit fault in the passive equalization circuit, the fault diagnosis module is activated to perform multi-cycle review and verification.

8. The self-diagnostic system for the passive equalization circuit according to claim 5, characterized in that, The equalization transistor includes an NPN transistor, a PNP transistor, an N-type metal-oxide-semiconductor (NMOS) transistor, or a P-type metal-oxide-semiconductor (PMOS) transistor.

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