A phased-control transmission system used in sonar and its synchronous control method

Abstract

This invention discloses a phased-control transmission system for sonar and its synchronous control method, belonging to the field of sonar phased-control technology. Through a delayed trigger mechanism controlled by address bits, the invention achieves high-precision synchronization and flexible phase control between multiple transmitting boards, avoiding the complex phase calculation and calibration processes in traditional systems. The system boasts a simple structure and strong scalability, making it suitable for multi-channel, high-precision sonar detection applications. A cascaded approach and homologous clock design reduce system complexity, improve beam control response speed and pointing accuracy, and meet the requirements of modern sonar systems for fast scanning and high-resolution detection.

Description

Technical Field

[0001] The present invention belongs to the technical field of sonar phase control, and in particular relates to a phase control transmitting system used in sonar and a synchronous control method thereof. Background Art

[0002] The technical principle of sonar transmission phase control is based on phased array theory. By precisely controlling the phase difference and amplitude of the sound waves emitted by each transducer (element) in the array, directional transmission, dynamic focusing, and scanning of the beam are achieved. Its core principles can be divided into the following key links:

[0003] 1. Physical basis of beamforming:

[0004] When multiple array elements transmit sound waves simultaneously, they superimpose in space. By controlling the emission timing (phase delay) of each element, the sound waves can be made to superimpose in phase in a specific direction (enhancing the signal) while canceling out of phase in other directions (suppressing interference), forming a directional beam. Wavefront control: By adjusting the phase differences between array elements, a wavefront (such as a plane wave or spherical wave) can be artificially constructed in a specific direction to achieve beam pointing control.

[0005] 2. Core technologies of launch phased control:

[0006] Delay addition method: Calculate the time difference (delay) of the sound wave emission of each array element according to the target direction, compensate for the sound path difference, and ensure that the beam is coherently enhanced in the specified direction.

[0007] Amplitude weighting and sidelobe suppression;

[0008] Amplitude control: By adjusting the transmit amplitude of each array element (such as using Chebyshev window, Taylor weighting, etc.), the beam sidelobe level is reduced and interference is reduced.

[0009] 3. Key technologies for hardware implementation:

[0010] Direct Digital Synthesis (DDS): Generates high-precision, phase-adjustable multi-channel sinusoidal signals through a digital frequency synthesizer.

[0011] FPGA / ASIC control: Utilizes programmable logic devices to implement real-time phase adjustment and delay compensation of multi-channel signals, ensuring signal synchronization accuracy (e.g., nanosecond-level synchronization error).

[0012] Disadvantages and technical problems of existing sonar phased array systems:

[0013] 1. Beam control rigidity:

[0014] Mechanical scanning is slow, and active phased arrays require dynamic phase adjustment, which is computationally complex. For example, beam scanning relies on array element movement or reconfiguration, making "static and dynamic scanning" impossible.

[0015] 2. High maintenance and deployment costs:

[0016] Mechanical scanning components (such as the pan / tilt) and redundant circuits drive up manufacturing costs and make maintenance difficult. In contrast, modular designs allow for single-point failure replacement but rely on high-end FPGA / ADC chips.

[0017] 3. Signal processing accuracy:

[0018] Traditional systems have shortcomings in precision control. On the contrary, phased angle error has higher accuracy. Summary of the Invention

[0019] In view of the above-mentioned deficiencies in the prior art, the present application provides a phased-control transmission system and a synchronous control method thereof for use in sonar.

[0020] In a first aspect, the present application proposes a phased control transmission system for use in sonar, comprising a main control unit and a plurality of cascaded transmitting units, wherein the main control unit sends configuration parameters and synchronization trigger signals to each transmitting unit via a serial communication protocol;

[0021] The multiple transmitting units identify their respective levels through address coding, and each transmitting unit uses the same clock reference source;

[0022] Each transmitting unit selects a clock input path according to the address code and determines a transmitting time based on a preset delay calculation logic;

[0023] After receiving the synchronization trigger signal, the transmitting unit returns status information in sequence according to the set time difference and outputs a transmission signal at the calculated transmission time.

[0024] In some embodiments, each of the transmitting units is distinguished by two external address bits, which are used to determine the clock path switching and delay parameter calculation logic. The first-level transmitting board unit uses an internal crystal oscillator to provide a 20MHz clock input, and generates an 80MHz system clock through a PLL, while outputting the 20MHz clock to the next-level transmitting unit. The remaining transmitting board units select the external input clock through the address bit to maintain clock cascade synchronization.

[0025] In some embodiments, the address encoding is binary encoding, and each transmitting unit determines its address through a combination of two configurable address pin levels, and the address is used to control clock path selection and delay parameter calculation logic.

[0026] In some embodiments, the plurality of cascaded transmitting units are configured with different return trigger times according to address bits, including:

[0027] The address of the first-level transmitting unit is 00, and after receiving the synchronous trigger signal, it immediately returns the trigger signal and starts timing;

[0028] The second-level transmitting unit address is 01, and the timing starts after a delay of 1.5ms;

[0029] The address of the third-level transmitter unit is 10, and the timing starts after a delay of 3ms;

[0030] The address of the fourth-level transmitting unit is 11, and the timing starts after a delay of 4.5ms.

[0031] In some embodiments, the delay parameter calculation logic is based on the set central time point t center The transmitting unit triggers the transmitting signal corresponding to the channel delay value tdelay control, including:

[0032] The emission time of the first-stage emission unit is t center -t delay ;

[0033] The emission time of the second-stage emission unit is t center -(t delay >>1);

[0034] The emission time of the third-stage emission unit is t center ;

[0035] The emission time of the fourth-stage emission unit is t center +(t delay >>1);

[0036] Among them, when t delay When it is a negative value, the trigger time of each level of transmitting unit will be moved forward accordingly.

[0037] In some embodiments, each of the transmitting units outputs 16 transmission signals, and the transmission signal types include CW signals and LFM signals.

[0038] In a second aspect, the present application proposes a synchronization control method for a phased-control transmission system in a sonar, comprising the following steps:

[0039] The main control unit sends configuration parameters and synchronization trigger signals to multiple cascaded transmitting units;

[0040] Each transmitting unit identifies its own level through address coding and selects the clock input path;

[0041] Each transmitting unit sets a different return delay time according to the address code, and the control unit identifies the status of each transmitting unit through the return signal;

[0042] Each transmitting unit triggers the transmission signal at different time points based on the preset central time point and channel delay value, thereby realizing phase control of multi-channel transmission signals.

[0043] In a third aspect, the present application proposes an electronic device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the steps of the above method when executing the computer program.

[0044] In a fourth aspect, the present application proposes a computer-readable storage medium, wherein the computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps of the above method are implemented.

[0045] Beneficial effects of the present invention:

[0046] This invention achieves high-precision synchronization and flexible phase control between multiple transmitting boards through a delayed trigger mechanism controlled by address bits, eliminating the complex phase calculation and calibration processes required in traditional systems. The system boasts a simple architecture and strong scalability, making it suitable for multi-channel, high-precision sonar detection applications. The cascaded design and co-sourced clock reduce system complexity, improve beam steering response speed and pointing accuracy, and meet the requirements of modern sonar systems for fast scanning and high-resolution detection. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] Figure 1 It is the overall flow chart of the present invention.

[0048] Figure 2 This is a system principle block diagram of the present invention. DETAILED DESCRIPTION

[0049] The following will describe exemplary embodiments of the present invention in more detail with reference to the accompanying drawings. Although exemplary embodiments of the present invention are shown in the accompanying drawings, it should be understood that the present invention can be implemented in various forms and should not be limited by the embodiments described herein; rather, these embodiments are provided to enable a more thorough understanding of the present invention and to fully convey the scope of the present invention to those skilled in the art.

[0050] In the first aspect, the present application proposes a phased-control transmission system for use in sonar, such as Figure 1 As shown, it includes a main control unit and multiple cascaded transmitting units, and the main control unit sends configuration parameters and synchronization trigger signals to each transmitting unit through a serial communication protocol;

[0051] The multiple transmitting units identify their respective levels through address coding, and each transmitting unit uses the same clock reference source;

[0052] Each transmitting unit selects a clock input path according to the address code and determines a transmitting time based on a preset delay calculation logic;

[0053] After receiving the synchronization trigger signal, the transmitting unit returns status information in sequence according to the set time difference and outputs a transmission signal at the calculated transmission time.

[0054] The main control unit is a control board that includes a microprocessor, serial communication interface, and control logic module. It is responsible for sending configuration parameters (signal type, frequency, bandwidth, pulse width, delay value, etc.) and synchronization trigger signals to each level of the transmitter board (transmitter unit).

[0055] Transmitter unit: There are four levels in total, with a maximum of one unit per level. Each transmitter board has 16 transmission channels. Each transmitter board contains:

[0056] FPGA chip, used to receive control instructions, process clock signals, and generate transmit signals;

[0057] 20MHz crystal oscillator (first stage only) or external clock input interface;

[0058] PLL module, used to multiply the 20MHz clock to the 80MHz system clock;

[0059] Address bit selection interface (two pins), used to set the transmitter board address (00, 01, 10, 11);

[0060] Serial communication interface, used to receive control board instructions;

[0061] A trigger signal processing module is used to set the return delay time according to the address bit;

[0062] A signal generation module, used to generate a CW or LFM transmission signal;

[0063] 16-channel transmission channel driver module, used to drive the transducer to transmit signals.

[0064] In some embodiments, the clock reference source is a multi-stage cascade structure, the first-stage transmitting unit includes a frequency source, and subsequent transmitting units at each stage receive the clock signal output by the previous-stage transmitting unit through a clock buffer circuit.

[0065] In some embodiments, each of the transmitting units is distinguished by two external address bits, which are used to determine the clock path switching and delay parameter calculation logic. The first-level transmitting board unit uses an internal crystal oscillator to provide a 20MHz clock input, and generates an 80MHz system clock through a PLL, while outputting the 20MHz clock to the next-level transmitting unit. The remaining transmitting board units select the external input clock through the address bit to maintain clock cascade synchronization.

[0066] Among them, the first-level transmitter board uses the internal 20MHz crystal oscillator as the clock input. The PLL module inside the transmitter board multiplies the 20MHz clock to an 80MHz system clock for use by the transmitter board at this level. At the same time, the 20MHz clock signal is output to the next-level transmitter board through a dedicated clock output pin. The second-level and subsequent transmitter boards use the address bit to determine whether to use the external input clock and use it as the system clock source at this level. The PLL is used again inside the transmitter board at each level to multiply the clock to an 80MHz system clock to ensure that the phases of the system clocks at each level are consistent.

[0067] In some embodiments, the address encoding is binary encoding, and each transmitting unit determines its address through a combination of two configurable address pin levels, and the address is used to control clock path selection and delay parameter calculation logic.

[0068] In some embodiments, the plurality of cascaded transmitting units are configured with different return trigger times according to address bits, including:

[0069] The address of the first-level transmitting unit is 00, and after receiving the synchronous trigger signal, it immediately returns the trigger signal and starts timing;

[0070] The second-level transmitting unit address is 01, and the timing starts after a delay of 1.5ms;

[0071] The address of the third-level transmitter unit is 10, and the timing starts after a delay of 3ms;

[0072] The address of the fourth-level transmitting unit is 11, and the timing starts after a delay of 4.5ms.

[0073] In some embodiments, the delay parameter calculation logic is based on the set central time point t center and channel delay value t delay Control the corresponding transmitting unit to trigger the transmission signal, including:

[0074] The emission time of the first-stage emission unit is t center -t delay ;

[0075] The emission time of the second-stage emission unit is t center -(t delay >>1);

[0076] The emission time of the third-stage emission unit is t center ;

[0077] The emission time of the fourth-stage emission unit is t center +(t delay >>1);

[0078] Among them, when t delayWhen it is a negative value, the trigger time of each level of transmitting unit will be moved forward accordingly.

[0079] The synchronization trigger mechanism is:

[0080] The control board sends a synchronous trigger signal to all transmitter boards. Each transmitter board determines whether to respond immediately or with a delay based on the address bit:

[0081] Address 00 (first level): immediately transmits the trigger signal back and starts timing.

[0082] Address 01 (second level): timing starts after a delay of 1.5ms.

[0083] Address 10 (third level): start timing after a delay of 3ms.

[0084] Address 11 (fourth level): start timing after a delay of 4.5ms.

[0085] Each transmitting board receives t center With t delay Parameters, calculate the emission time of each channel:

[0086] The first stage launch time is: t center -t delay ;

[0087] The second stage launch time is: t center -(t delay >>1);

[0088] The third stage launch time is: t center ;

[0089] The fourth stage launch time is: t center +(t delay >>1);

[0090] If t delay If it is a negative value, the emission time will be moved forward or backward accordingly to ensure the consistency of the overall emission timing.

[0091] In some embodiments, each of the transmitting units outputs 16 transmission signals, and the transmission signal types include CW signals and LFM signals.

[0092] The 16 transmission channels of each transmitting board independently control the transmission time according to their respective channel delay values. The signal type is set by the control board to CW or LFM signal:

[0093] CW signal: continuous wave with fixed frequency;

[0094] LFM signal: a frequency modulated signal whose frequency changes linearly with time;

[0095] Signal frequency, bandwidth, pulse width and other parameters are configured by the control board through the serial port protocol.

[0096] The start time of all transmitted signals is precisely controlled by an internal counter to ensure the phase consistency of the transmitted signals of each channel.

[0097] This invention provides a phased-control transmission system for sonar applications. Its core goal is to address the rigid beam control, slow mechanical scanning speed, and complex phase calculation issues of traditional sonar systems. This system achieves phase control and beamforming of multi-channel signals through the coordinated operation of a control board and multi-stage transmitting boards. It offers advantages such as high precision, low latency, and strong scalability. Specifically:

[0098] The system consists of one control board and four transmitter boards, connected in cascade mode. The control board sends configuration parameters and synchronization trigger signals to each transmitter board via a serial port protocol. These parameters include transmit signal type (CW or LFM), channel delay value, and transmit start time. After receiving the synchronization signal, the transmitter board sequentially transmits its status and parameter information back to the control board based on the address bit configuration, forming a closed-loop feedback loop.

[0099] To avoid data conflicts, the system adopts an address-driven return timing control strategy:

[0100] The first-stage transmitter board transmits back immediately when the synchronization is triggered;

[0101] The second-stage transmitter sends back a signal 1.5ms after the synchronization trigger.

[0102] The third-stage transmitter board transmits back 3ms after the synchronization trigger;

[0103] The fourth-stage transmitter board transmits back 4.5ms after the synchronization trigger.

[0104] The four transmitter boards are distinguished by two external pins as address bits, set to {00, 01, 10, 11}, respectively, through pull-up and pull-down resistors. The address bits are used to control clock path switching and delay parameter calculation.

[0105] To achieve high-precision synchronization between multiple transmitter boards, the system uses a single 20MHz clock as the clock input for all FPGAs. This clock is generated by the internal crystal oscillator of the first-stage transmitter board and transmitted to subsequent transmitter boards in a cascaded manner.

[0106] The working mode of the first-level transmitter board is as follows: the input is the internal crystal oscillator signal, which is multiplied by the internal PLL of the FPGA to generate an 80MHz system clock, and at the same time outputs a 20MHz clock for use by the next-level transmitter board.

[0107] The working modes of the remaining transmitter boards are as follows:

[0108] The input is the 20MHz clock output by the previous-stage transmitter board. The local crystal oscillator is no longer used and it is directly used as the system clock input. Since the 20MHz clock period is 50ns and the measured path delay of the system is at the nanosecond level, no additional path delay compensation is required to meet the nanosecond-level synchronization requirements.

[0109] The system controls the delay offset through the address bit to achieve phase difference control of multi-level transmission signals. Assume that the center time point is , the channel delay value is , then the triggering time of each transmitting board is as follows:

[0110] First stage launch pad: ;

[0111] Second stage launch pad: ;

[0112] Third stage launch pad: ;

[0113] Fourth stage launch pad: ;

[0114] when When it is a negative value, the triggering time of each level of the transmitting board is as follows:

[0115] First stage launch pad: ;

[0116] Second stage launch pad: ;

[0117] Third stage launch pad: ;

[0118] Fourth stage launch pad: .

[0119] Among them, it is assumed that the system sets the central time point , channel delay value , then the triggering time of each level of transmitting board is as follows:

[0120] First stage launch pad: ;

[0121] Second stage launch pad: ;

[0122] Third stage launch pad: ;

[0123] Fourth stage launch pad: ;

[0124] like , then the triggering time of each level of transmitting board is as follows:

[0125] First stage launch pad:

[0126] Second stage launch pad: ;

[0127] Third stage launch pad: ;

[0128] Fourth stage launch pad: .

[0129] The system adopts a cascaded design, with multi-level expansion achieved through address bit identification and clock cascading between transmitter boards. Each transmitter board configures the address bits through external pull-up and pull-down resistors, with the address bits (from left to right) being {00, 01, 10, 11}, ensuring address uniqueness and logical identifiability.

[0130] The clock path switching logic is as follows:

[0131] When the address bit is 00: the internal crystal oscillator input is selected, the PLL multiplies the frequency to generate an 80MHz system clock, and outputs a 20MHz clock;

[0132] When the address bit is not 00: select external input clock, PLL multiplies the frequency to generate 80MHz system clock, and does not output 20MHz clock;

[0133] This structure supports flexible expansion and can theoretically support the access of more transmitting boards, thereby increasing the number of system channels and beam control accuracy.

[0134] In this embodiment, the system realizes phase control and beamforming of multi-channel signals through key technologies such as the communication mechanism between the control board and the transmitter board, nanosecond-level synchronization, address bit-driven delay parameter calculation, transmission signal control and beamforming.

[0135] In the second aspect, the present application proposes a synchronous control method for a phased-control transmitting system in sonar, such as Figure 2 As shown, the following steps are included:

[0136] S100: The main control unit sends configuration parameters and synchronization trigger signals to multiple cascaded transmitting units;

[0137] S200: Each transmitting unit identifies its own level through address coding and selects a clock input path;

[0138] S300: Each transmitting unit sets a different return delay time according to the address code, and the control unit identifies the status of each transmitting unit through the return signal;

[0139] S400: Each transmitting unit triggers a transmitting signal at a different time point based on a preset central time point and a channel delay value, thereby achieving phase control of a multi-channel transmitting signal.

[0140] In a third aspect, the present application proposes an electronic device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the steps of the above method when executing the computer program.

[0141] In a fourth aspect, the present application proposes a computer-readable storage medium, wherein the computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps of the above method are implemented.

[0142] Those skilled in the art can clearly understand that, for the convenience and brevity of description, only the division of the above-mentioned functional units and modules is used as an example for illustration. In actual applications, the above-mentioned functions can be distributed and completed by different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above. The functional units and modules in the embodiment can be integrated into one processing unit, or each unit can exist physically alone, or two or more units can be integrated into one unit. The above-mentioned integrated unit can be implemented in the form of hardware or in the form of software functional units. In addition, the specific names of the functional units and modules are only for the convenience of distinguishing each other, and are not used to limit the scope of protection of this application. The specific working process of the units and modules in the above-mentioned system can refer to the corresponding process in the aforementioned method embodiment, and will not be repeated here.

[0143] In the above embodiments, the description of each embodiment has its own focus. For parts that are not described or recorded in detail in a certain embodiment, reference can be made to the relevant description of other embodiments.

[0144] Those skilled in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this disclosure.

[0145] In the embodiments provided in the present disclosure, it should be understood that the disclosed apparatus / computer equipment and methods can be implemented in other ways. For example, the apparatus / computer equipment embodiments described above are merely schematic. For example, the division of modules or units is merely a logical function division. In actual implementation, there may be other division methods. Multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed may be through some interfaces, indirect coupling or communication connection of the apparatus or unit, which may be electrical, mechanical or other forms.

[0146] Units described as separate components may or may not be physically separate, and components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of these units may be selected to achieve the purpose of this embodiment according to actual needs.

[0147] In addition, the functional units in the various embodiments of the present disclosure may be integrated into a single processing unit, or each unit may exist physically separately, or two or more units may be integrated into a single unit. The aforementioned integrated units may be implemented in the form of hardware or software functional units.

[0148] If the integrated module / unit is implemented as a software functional unit and sold or used as a standalone product, it can be stored in a computer-readable storage medium. Based on this understanding, the present disclosure can implement all or part of the process steps in the above-mentioned method embodiments by using a computer program to instruct the relevant hardware. The computer program can be stored in a computer-readable storage medium, and when executed by a processor, the computer program can implement the steps of each of the above-mentioned method embodiments. The computer program can include computer program code, which can be in source code form, object code form, executable file, or some intermediate form. Computer-readable media can include: any entity or device capable of carrying computer program code, recording media, USB flash drives, removable hard drives, magnetic disks, optical disks, computer memory, read-only memory (ROM), random access memory (RAM), electrical carrier signals, telecommunications signals, and software distribution media. It should be noted that the content included in computer-readable media can be appropriately increased or decreased based on the requirements of legislation and patent practice in a jurisdiction. For example, in some jurisdictions, based on legislation and patent practice, computer-readable media does not include electrical carrier signals and telecommunications signals.

[0149] The above are only preferred embodiments of the present invention. It should be pointed out that various modifications and improvements made by those skilled in the art without departing from the present technical solution should also be deemed to fall within the scope of protection required by this solution.

Claims

1. A phased-control transmission system used in sonar, characterized by: It includes a main control unit and multiple cascaded transmitting units, wherein the main control unit sends configuration parameters and synchronization trigger signals to each transmitting unit through a serial communication protocol; The multiple transmitting units identify their respective levels through address coding, and each transmitting unit uses the same clock reference source. The clock reference source is a multi-stage cascade structure. The first-stage transmitting unit includes a frequency source, and subsequent transmitting units at each stage receive the clock signal output by the previous-stage transmitting unit through a clock buffer circuit. Each transmitting unit selects a clock input path according to the address code and determines the transmission time based on the preset delay calculation logic. Each transmitting unit is distinguished by two external address bits, which are used to determine the clock path switching and delay parameter calculation logic. The first-level transmitting board unit uses an internal crystal oscillator to provide a 20MHz clock input and generates an 80MHz system clock through a PLL. At the same time, the 20MHz clock is output to the next-level transmitting unit. The remaining transmitting board units select external input clocks through address bits to maintain clock cascade synchronization. After receiving the synchronization trigger signal, the transmitting unit returns the status information in sequence according to the set time difference and outputs the transmission signal at the calculated transmission time. The multiple cascaded transmitting units set different return trigger times according to the address bits, including: The address of the first-level transmitting unit is 00, and after receiving the synchronous trigger signal, it immediately returns the trigger signal and starts timing; The second-level transmitting unit address is 01, and the timing starts after a delay of 1.5ms; The address of the third-level transmitter unit is 10, and the timing starts after a delay of 3ms; The address of the fourth-level transmitter unit is 11, and the timing starts after a delay of 4.5ms; The delay parameter calculation logic is based on the set central time point t center and channel delay value t delay Control the corresponding transmitting unit to trigger the transmission signal, including: The emission time of the first-stage emission unit is t center -t delay ; The emission time of the second-stage emission unit is t center -(t delay >>1); The emission time of the third-stage emission unit is t center ; The emission time of the fourth-stage emission unit is t center +(t delay >>1); Among them, when t delay When it is a negative value, the trigger time of each level of transmitting unit will be moved forward accordingly.

2. The system according to claim 1, wherein: The address code is a binary code. Each transmitting unit determines its address through a combination of two configurable address pin levels. The address is used to control clock path selection and delay parameter calculation logic.

3. The system according to claim 2, characterized in that: Each of the transmitting units outputs 16 transmission signals, and the transmission signal types include CW signals and LFM signals.

4. A synchronous control method for a phased array transmission system used in sonar, characterized in that: The following steps are involved: The main control unit sends configuration parameters and synchronization trigger signals to multiple cascaded transmitting units; Each transmitting unit identifies its own level through address coding and selects the clock input path; Each transmitting unit sets a different return delay time according to the address code, and the control unit identifies the status of each transmitting unit through the return signal; Each transmitting unit triggers the transmission signal at different time points based on the preset central time point and channel delay value, thereby realizing phase control of multi-channel transmission signals.

5. An electronic device comprising a memory, a processor, and a computer program stored in the memory and running on the processor, characterized in that: When the processor executes the computer program, the steps of the method according to claim 4 are implemented.

6. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps of the method according to claim 4 are implemented.

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