Array substrate, display panel, display module and display device

Abstract

The invention provides an array substrate, a display panel, a display module and a display device.The array substrate of one embodiment comprises a display area and a non-display area which are arranged on a substrate, the non-display area comprises a first binding area and a fan-out area which are arranged on the first side of the display area, and the first binding area comprises a plurality of bonding pad areas arranged in sequence; each bonding pad area comprises a first bonding pad, the fan-out area comprises a plurality of fan-out lines, and the fan-out lines comprise first fan-out lines located on the first conductive layer and second fan-out lines located on the second conductive layer. The plurality of bonding pad regions comprise a first region in which a first bonding pad is electrically connected with the first fan-out line and a second region in which the first bonding pad is electrically connected with the second fan-out line, and the distance from the surface, far away from the substrate, of the first region to the substrate is equal to the distance from the surface, far away from the substrate, of the second region to the substrate. According to the array substrate disclosed by the embodiment of the invention, good contact between the first bonding pad and the bonding pad to be bound is ensured.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to an array substrate, a display panel, a display module, and a display device. Background Art

[0002] Competition in today's display market is increasingly fierce, necessitating continuous product upgrades to enhance competitiveness. In recent years, narrow-bezel display products, such as televisions, have become a popular choice, particularly in the high-end market. For example, narrow-bezel designs offer numerous advantages, including a higher screen-to-body ratio, which not only creates a stronger sense of visual immersion but also enhances the overall aesthetics of the TV, making it more aesthetically pleasing when mounted on a wall. To enhance their brand's technological and premium image, major TV manufacturers are continuously pursuing a technologically advanced approach to reduce bezel width.

[0003] However, current narrow-border display products are difficult to meet user needs. Summary of the Invention

[0004] In order to solve at least one of the above problems, the first aspect of the present disclosure provides an array substrate, comprising: a display area provided on a base substrate and a non-display area surrounding the display area, wherein the non-display area includes a first binding area provided on a first side of the display area and a fan-out area provided between the first binding area and the display area.

[0005] The first bonding area includes: a plurality of pad areas arranged in sequence along a direction, each pad area including a first pad;

[0006] The fan-out area includes: a plurality of fan-out lines electrically connected to the plurality of first pads in a one-to-one correspondence,

[0007] The multiple fan-out lines include a first fan-out line and a second fan-out line, the portion of the first fan-out line close to the first pad electrically connected to it is located in the first conductive layer, the portion of the second fan-out line close to the first pad electrically connected to it is located in the second conductive layer, the first conductive layer and the second conductive layer are different, the multiple pad areas include a first area in which the first pad is electrically connected to the first fan-out line and a second area in which the first pad is electrically connected to the second fan-out line, the distance from the first area away from the surface of the substrate to the substrate is equal to the distance from the second area away from the surface of the substrate to the substrate.

[0008] Optionally, the first binding region includes: a first conductive layer, a first insulating layer, a second conductive layer, a passivation layer, and a planarization layer stacked on the base substrate.

[0009] The first region includes a base substrate, a first conductive layer, a first insulating layer, a passivation layer and a planarization layer stacked in sequence;

[0010] The second region includes: a base substrate, a first insulating layer, a second conductive layer, a passivation layer and a planarization layer stacked in sequence;

[0011] The plurality of first pads include a first sub-pad electrically connected to the first fan-out line and a second sub-pad electrically connected to the second fan-out line;

[0012] The first sub-pad is disposed in the first conductive layer of the first region, and the second sub-pad is disposed in the second conductive layer of the second region.

[0013] Optionally, the film layer included in the first region is the same as the film layer included in the second region.

[0014] Each of the first region and the second region includes: a base substrate, a first conductive layer, a first insulating layer, a second conductive layer and a passivation layer stacked in sequence;

[0015] The plurality of first pads include a first sub-pad electrically connected to the first fan-out line and a second sub-pad electrically connected to the second fan-out line;

[0016] The first sub-pad is disposed in the first conductive layer of the first region, and the second sub-pad is disposed in the second conductive layer of the second region.

[0017] Optionally, the first pads are provided on the first conductive layer, and the plurality of first pads include a first sub-pad electrically connected to the first fan-out line and a second sub-pad electrically connected to the second fan-out line;

[0018] The array substrate further includes a transfer area provided between the fan-out area and the first binding area, the transfer area including a plurality of first sub-transfer portions electrically connected to the first sub-pads in a one-to-one correspondence and a plurality of second sub-transfer portions electrically connected to the second sub-pads in a one-to-one correspondence;

[0019] The first sub-transfer portion is provided on a first conductive layer, the second sub-transfer portion includes a first sub-portion provided on the first conductive layer and a second sub-portion provided on the second conductive layer, a first end of the first sub-transfer portion is electrically connected to the first sub-pad, and the other end is electrically connected to the first fan-out line, a first end of the first sub-portion is electrically connected to the second sub-pad, and a second end is electrically connected to the first end of the second sub-portion via a via penetrating the second conductive layer, and a second end of the second sub-portion is electrically connected to the second fan-out line; or

[0020] The first sub-transfer portion includes a first sub-portion arranged on the second conductive layer and two second sub-portions arranged on the first conductive layer, the second sub-transfer portion includes a first sub-portion arranged on the second conductive layer and a second sub-portion arranged on the first conductive layer, the two ends of the first sub-portion of the first sub-transfer portion are respectively electrically connected to the two second sub-portions via vias passing through the second conductive layer, and the other ends of the two second sub-portions are respectively electrically connected to the first sub-pad and the first fan-out line, the first end of the first sub-portion of the second sub-transfer portion is electrically connected to one end of its second sub-portion via a via passing through the second conductive layer, the second end is electrically connected to the second fan-out line, and the other end of the second sub-portion is electrically connected to the second sub-pad.

[0021] Optionally, the first conductive layer is a gate layer, and the second conductive layer is a source-drain metal layer, or the first conductive layer is a source-drain metal layer, and the second conductive layer is a gate layer.

[0022] Optionally, the second region further includes: an active layer disposed between the first insulating layer and the second conductive layer, the first conductive layer is a gate layer, the second conductive layer is a source / drain metal layer, and the second conductive layer is in direct contact with the active layer.

[0023] Optionally, the first region includes a first via extending from the passivation layer to the first conductive layer, and the second region includes a second via extending from the passivation layer to the second conductive layer. The orthographic projection of each of the first and second vias on the substrate is serpentine.

[0024] A second aspect of the present disclosure provides a display panel, comprising the array substrate described above.

[0025] A third aspect of the present disclosure provides a display module, comprising: the display panel and flexible circuit board described above, wherein the flexible circuit board comprises a second pad area, the second pad area comprises a plurality of second pads, and the second pads are electrically connected to the first pads in a one-to-one correspondence.

[0026] A fourth aspect of the present disclosure provides a display device, comprising the display panel described above.

[0027] The beneficial effects of the present disclosure are as follows:

[0028] In response to the current existing problems, the present disclosure develops an array substrate, a display panel, a display module and a display device, and has a first binding area with multiple pad areas, the multiple pad areas include a first area and a second area, the pads arranged in the first area and the pads arranged in the second area are located in different conductive layers, and the surface heights of the first area and the second area are the same, so that the pads bound to the pad area have good contact, the binding yield is improved while performing a narrow frame design, and the yield of display products is improved, which has broad application prospects. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0030] Figure 1 A schematic diagram showing the structural layout of a typical array substrate is shown;

[0031] Figure 2 A cross-sectional view showing adjacent binding pins in the related art;

[0032] Figure 3 A cross-sectional electron microscope scanning image of adjacent binding pins in the related art is shown;

[0033] Figure 4 A schematic diagram showing an array substrate according to an embodiment of the present disclosure;

[0034] Figure 5 A schematic cross-sectional view showing a binding area of an array substrate according to an embodiment of the present disclosure;

[0035] Figure 6 A schematic diagram of a fan-out line structure of an array substrate according to an embodiment of the present disclosure is shown;

[0036] Figure 7 A schematic diagram showing a binding effect of a first pad of an array substrate and a corresponding pad to be bound according to an embodiment of the present disclosure is shown;

[0037] Figure 8 A diagram showing a binding effect of a binding area of an array substrate according to another embodiment of the present disclosure;

[0038] Figure 9 A schematic cross-sectional view showing a binding area of an array substrate according to another embodiment of the present disclosure;

[0039] Figure 10 A schematic diagram showing an array substrate according to another embodiment of the present disclosure;

[0040] Figure 11 Show Figure 10 A partial enlarged view of an array substrate of an embodiment of the structure shown;

[0041] Figure 12 Show satisfaction Figure 10 A partial enlarged view of an array substrate of another embodiment of the structure shown;

[0042] Figure 13 A schematic diagram showing a display module according to an embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0043] To more clearly illustrate the present disclosure, the present disclosure is further described below in conjunction with preferred embodiments and accompanying drawings. Similar components in the accompanying drawings are represented by the same or similar reference numerals. Those skilled in the art should understand that the specific description below is illustrative rather than restrictive and should not be used to limit the scope of protection of the present disclosure.

[0044] It should be noted that the terms “having”, “including”, “comprising”, etc. described in the present disclosure are all open-ended, that is, when describing a module as “having”, “including” or “comprising” a first element, a second element and / or a third element, it means that the module includes other elements in addition to the first element, the second element and / or the third element. In addition, ordinal numbers such as “first”, “second” and “third” in the present disclosure are not intended to limit a specific order, but are only used to distinguish between various parts. In the present disclosure, when describing layer A and layer B as “set on the same layer”, it means that layer A and layer B are made of the same material and the same process.

[0045] Figure 1 A view of a typical array substrate is shown, in which a binding area is set in the lower frame below the display area. The area between the binding area and the display area is a fan-out area, which is used to electrically connect the corresponding pins in the binding area with the signal lines in the display area to provide the signals connected to each pin to the display area or to lead the signals output in the display area from the pins to an external circuit, which can be, for example, a flexible printed circuit board.

[0046] The inventors have found that Figure 1 As shown in the figure, because the signal lines in the display area are not arranged as closely as the pins, the width of the binding area is narrower than the width of the display area. In other words, no matter how the fan-out area is wired, the actual wiring trend is Figure 1 The example in the inverted trapezoidal shape, or in other words, the overall orientation of the traces in the fan-out area is tilted. This trace layout results in trace width and the spacing between traces being the determining factors affecting the width of the bottom bezel. The sum of the width of a trace and the spacing between it and adjacent traces is called the trace pitch, also known as the fan-out pitch. The smaller the fan-out pitch, the less space the peripheral leads occupy, making it easier to achieve a narrow bezel.

[0047] However, due to process limitations, fan-out pitches cannot be made too small. Too small will result in thin leads that are prone to short circuits and prevent the photoresist from being exposed during the exposure process. Currently, most fan-out pitch designs for large-scale display processes in the industry are limited to 11.4µm. Currently, to further reduce the bezel within process limitations, adjacent traces are at least partially routed using different metal film layers, and the pins in the bonding area are also placed in the same metal film layer as the wiring extending to the pins.

[0048] Current approaches to routing on different metal layers include: ① alternating gate and source / drain (SD) layer routing and ② a double-layer 50% layer swapping method. Method ① alternates adjacent traces on different metal layers, reducing the size of the fan-out pitch. Method ② places half of each trace on the gate layer and the other half on the SD layer, with vias used to bridge the gaps and achieve layer swapping. However, each section of the adjacent traces remains on a different layer. This approach reduces the size of the fan-out pitch while also minimizing trace resistance differences caused by thickness differences between the gate and SD layers. However, both methods ① and ② suffer from a high incidence of poor bonding.

[0049] The inventors found that regardless of method ① or method ②, the adjacent wirings of the fan-out wiring connected to the pins are located in different metal layers, so the pins are also located in different metal layers. Figure 2 As shown, the number of film layers below is different when patterning the gate layer and the source and drain layer, resulting in different surface heights of the passivation layer on the pin surface. There is a height difference of ΔH between adjacent pins. The actual product effect is as follows Figure 3 As shown in the electron microscope scanning image, the pin acts as an intermediate bridge to the external signal. When the pin is connected to the pin to be bonded, the height difference causes inconsistent force on the pin. In severe cases, poor contact with the template to be bonded will cause poor bonding, which in turn leads to a high incidence of dark line defects in the surface.

[0050] Therefore, it is necessary to provide a display product design solution with high yield and narrow frame.

[0051] In view of this, an embodiment of the present disclosure provides an array substrate, comprising: a display area provided on a base substrate and a non-display area surrounding the display area, wherein the non-display area comprises a first binding area provided on a first side of the display area and a fan-out area provided between the first binding area and the display area.

[0052] The first bonding area includes: a plurality of pad areas arranged in sequence along a direction, each pad area includes a first pad,

[0053] The fan-out area includes: a plurality of fan-out lines electrically connected to the plurality of first pads in a one-to-one correspondence,

[0054] The plurality of fan-out lines include a first fan-out line and a second fan-out line, wherein a portion of the first fan-out line close to the first pad electrically connected thereto is located in a first conductive layer, and a portion of the second fan-out line close to the first pad electrically connected thereto is located in a second conductive layer, and the first conductive layer and the second conductive layer are different.

[0055] The plurality of pad regions include a first region in which a first pad is electrically connected to a first fan-out line and a second region in which a first pad is electrically connected to a second fan-out line,

[0056] The distance between the first region and the substrate substrate is equal to the distance between the first region and the substrate substrate.

[0057] In this embodiment, a first binding area having multiple pad areas is provided, and the multiple pad areas include a first area and a second area. The pads arranged in the first area and the pads arranged in the second area are located in different conductive layers, and the surface heights of the first area and the second area are the same, so that the pads bound to the pad area have good contact, thereby improving the binding yield while performing a narrow frame design.

[0058] The array substrate of the embodiment of the present disclosure is described in detail below with reference to specific examples.

[0059] In a specific example, referring to Figure 4 and Figure 5 As shown, the array substrate includes: a display area AA provided on a base substrate 500 and a non-display area NA surrounding the display area AA. The non-display area NA includes a first binding area 41 provided on a first side of the display area AA and a fan-out area 42 provided between the first binding area 41 and the display area AA.

[0060] The first binding area 41 includes: a plurality of pad areas arranged in sequence along a direction, each pad area including a first pad 401. It should be noted that "arranged in sequence along a direction" here is not limited to the first binding area including only one row of pad areas, but refers to a row of pad areas arranged in a direction or multiple pad areas arranged in a direction.

[0061] The fan-out region 42 includes a plurality of fan-out lines 402 electrically connected to the plurality of first pads 401. One end of the fan-out line 402 is electrically connected to the corresponding first pad 401, and the other end is electrically connected to the corresponding signal line in the display area AA, such as a data signal line, a power signal line, etc.

[0062] The plurality of fan-out lines 402 include a first fan-out line and a second fan-out line. The first fan-out line is located in a first conductive layer near the first pad electrically connected thereto, and the second fan-out line is located in a second conductive layer, which are different from each other.

[0063] Optionally, refer to Figure 6 As shown in the figure, the structures with the same fill pattern are located in the same layer. Figure 6 It can be seen that the first fan-out line 402-1 and the second fan-out line 402-2 are arranged adjacent to each other, and a portion of the first fan-out line 402-1 is located in the first conductive layer 501 and another portion is located in the second conductive layer 503, and the two portions are electrically connected together using a via TK. A portion of the second fan-out line 402-2 is located in the first conductive layer 501 and another portion is located in the second conductive layer 503, and the two portions are electrically connected together through another via TK. For the adjacent first fan-out line 402-1 and the second fan-out line 402-2, the portions extending in the same direction are located in different layers, thereby reducing the spacing between adjacent portions and thus reducing the pitch, achieving a narrow frame design. This setting can also reduce the resistance difference between the first fan-out line 402-1 and the second fan-out line 402-2, thereby improving signal uniformity. It should be understood that the via area in the figure is connected to the via TK by setting a widened transfer pad, which will not be described in detail herein.

[0064] It should be noted that in a solution that only considers the impact of the frame width, the first fan-out line can be entirely provided in the first conductive layer 501 and the second fan-out line can be entirely provided in the second conductive layer 503, and / or, a second fan-out line can be provided every plurality of first fan-out lines. In other words, the present disclosure is not limited to the wiring method shown in Figure 6. The portion of the first fan-out line close to the first pad 401 electrically connected thereto and the portion of the second fan-out line close to the first pad 401 electrically connected thereto are located in different conductive layers, which is protected by the present disclosure.

[0065] Combine Figure 5 and Figure 6 As shown, the plurality of pad regions include a first region 41-1 where a first pad 401 is electrically connected to a first fan-out line 402-1 and a second region 41-2 where the first pad 401 is electrically connected to a second fan-out line 402-2.

[0066] Specifically, the first binding region 41 includes: a first conductive layer 501, a first insulating layer 502, a second conductive layer 503, a passivation layer 504, and a planarization layer 505 stacked on a base substrate 500. The first region 41-1 includes: the base substrate 500, the first conductive layer 501, the first insulating layer 502, the passivation layer 504, and the planarization layer 505 stacked in sequence; the second region 41-1 includes: the base substrate 500, the first insulating layer 502, the second conductive layer 503, the passivation layer 504, and the planarization layer 505 stacked in sequence. The plurality of first pads 401 include a first sub-pad 401-1 electrically connected to the first fan-out line 402-1 and a second sub-pad 401-2 electrically connected to the second fan-out line 402-2. The first sub-pad 401-1 is disposed in the first conductive layer 501 of the first region 41-1, and the second sub-pad 401-2 is disposed in the second conductive layer 503 of the second region 41-2.

[0067] Optionally, in Figure 5 In the exemplary embodiment shown, the first conductive layer 501 is a gate layer and the second conductive layer 503 is a source-drain metal layer, but the present disclosure is not limited to this. In some other examples, the "first" and "second" in the first conductive layer and the second conductive layer are only intended to distinguish different conductive layers, which can indicate that the present disclosure includes an embodiment in which the second conductive layer is a gate layer and the first conductive layer is a source-drain metal layer, and it can also indicate that the present disclosure includes an embodiment in which the two are other suitable film layer combinations.

[0068] It can be seen that in this example, by adding a planarization layer 505 to the first binding area 41, and the planarization layer 505 is located above the passivation layer 504, the layer can be used to raise and level the overall height in the first binding area 41, so that the distance from the surface of the first area 41-1 away from the substrate substrate 500 to the substrate substrate 500 is equal to the distance from the surface of the second area 41-2 away from the substrate substrate 500 to the substrate substrate 500.

[0069] Reference Figure 7 As shown in the schematic binding effect diagram, when the first pad is bound to the corresponding pad to be bound, the first sub-pad 401-1 and the corresponding sub-pad to be bound Ld1 are crimped and bound, and the second sub-pad 401-2 and the corresponding sub-pad to be bound Ld2 are crimped and bound. Because the distance from the surface of the first zone and the second zone away from the base substrate 500 to the base substrate 500 is the same, the force on all crimping surfaces is consistent, which can effectively improve the binding yield.

[0070] From the perspective of process preparation, the planarization layer 505 can be prepared using the existing planarization film layer of the driving circuit layer in the display area AA and the non-display area NA, and the film layer that usually needs to be patterned and removed in the binding area and fan-out area below the non-display area is partially retained, and then the step of etching vias to expose the first pad is moved to etching after the planarization layer 505.

[0071] The above arrangement, by setting the first area of the first sub-pad and the second area of the second sub-pad in the first binding area to include a planarization layer, makes the binding surfaces of all the first pads the same distance from the substrate, so that the pads to be bound to the first pads are subjected to consistent force on the contact surfaces of the respective first pads, and does not add additional process steps, thereby improving the binding yield while ensuring the narrow frame design using different conductive layers to lay out the fan-out lines, avoiding in-plane dark line defects, and improving the product yield of narrow frame products.

[0072] It should be noted that the solution of the embodiment of the present disclosure can be applied to the first binding area of various film layer combinations.

[0073] For example, in Figure 5 In the example shown, the first region 41-1 may further include a first metal oxide layer 506, also known as 1ITO, disposed below the first conductive layer 501. This layer may be used to form a common electrode layer. Furthermore, the second region 41-2 may further include an active layer 507 disposed between the first insulating layer 502 and the second conductive layer 503. The second conductive layer 503 is in direct contact with the active layer 507.

[0074] From the perspective of manufacturing process, when the array substrate adopts a grayscale mask process (Half Tune) to pattern the first conductive layer 501 and the second conductive layer 503, the underlying film layer will be retained when patterning both.

[0075] Of course, those skilled in the art should understand that the present disclosure is not limited to this. If the array substrate adopts other patterning processes to prepare the first sub-pad 401-1 and the second sub-pad 401-2, the first metal oxide layer 506 in the first area 41-1 can be removed before preparing the first sub-pad 401-1, and the active layer 507 in the second area 41-2 can be removed before preparing the second sub-pad 401-2, which will not be elaborated here.

[0076] in addition, Figure 5The film layer composition of the bottom gate process is shown in , that is, the gate layer is located below the active layer. Those skilled in the art should understand that the present disclosure is not limited to this, and the film layer composition of the top gate process is also applicable to the embodiments of the present disclosure. The difference is that when the top gate process is adopted, the gate layer should be above the active layer, and there is an insulating layer between the gate layer and the active layer. In this case, if the array substrate is prepared using Half Tune, when the first conductive layer corresponding to the patterned gate layer is patterned, a patterned insulating layer will be retained underneath it, and there is no patterned active layer pattern in the first binding area, which will not be described in detail herein.

[0077] Optionally, continue with reference to Figure 5 As shown, in this example, the first region 41-1 may further include a pad protection layer 508 disposed on the planarization layer 505 to protect the first sub-pad 401-1 from oxidation due to contact with air, thereby improving the bonding yield. Simultaneously, the second region 41-2 also includes a pad protection layer 508 disposed on the planarization layer 505 to protect the second sub-pad 401-2 from oxidation due to contact with air, thereby improving the bonding yield. The pad protection layer 508 may be made of a metal oxide material. From a manufacturing process perspective, if the array substrate is a liquid crystal display panel, it may be made of a pixel electrode layer, but the present invention is not limited to this.

[0078] Continue to refer to Figure 5 As shown, the surface of the first area 41-1 away from the substrate substrate 500 is the surface of the pad protection layer 508 away from the substrate substrate 500, and the surface of the second area 41-2 away from the substrate substrate 500 is the surface of the pad protection layer 508 away from the substrate substrate 500. The distance from the surface of the first area 41-1 and the second area 41-2 away from the substrate 500 to the substrate substrate 500 is h1.

[0079] It can be seen that when the first binding area 41 includes the pad protection layer 508, this embodiment can still achieve that the distance between the surface of the first area away from the substrate and the substrate is equal to the distance between the surface of the second area away from the substrate and the substrate, thereby improving the binding yield and avoiding in-plane dark line defects, thereby improving the product yield of narrow-frame products.

[0080] Alternatively, in order to enhance the binding effect, the vias forming the binding connection are further patterned.

[0081] Combine Figure 8 Binding effect diagram and Figure 5 As shown, the first region 41-1 includes a first via TK1 extending from the planarization layer 505 to the first conductive layer 501, and the second region 41-2 includes a second via TK2 extending from the planarization layer 505 to the second conductive layer 503. The orthographic projection of each of the first via and the second via on the substrate base 500 is serpentine.

[0082] Through this arrangement, when the pad to be bound is bound to the first pad 401 , the contact area is increased, the bonding effect is improved, the binding effectiveness is improved, and thus the yield rate is improved.

[0083] In some other optional embodiments, referring to Figure 9 As shown, this embodiment differs from the above-described embodiment in that the film layers of all first pads are simultaneously raised in the first bonding area. The first bonding area includes a substrate, a first conductive layer, a first insulating layer, a second conductive layer, and a passivation layer. The first and second areas of the first conductive layer include the same film layers.

[0084] Specifically, refer to Figure 9 As shown, the first binding region 41 includes a substrate 500, a first conductive layer 501, a first insulating layer 502, a second conductive layer 503 and a passivation layer 504. The first conductive layer 501 may be a gate layer, and the second conductive layer 503 may be a source / drain metal layer. Figure 9 It can be seen that each of the first region 41-1' and the second region 41-2' includes a base substrate 500, a first conductive layer 501, a first insulating layer 502, a second conductive layer 503 and a passivation layer 504 stacked in sequence. The passivation layer 504 may also be called a PVX layer.

[0085] If this example also uses Figure 6 In the fan-out area wiring method shown, the plurality of first pads 401 include a first sub-pad 401-1 electrically connected to the first fan-out line 402-1 and a second sub-pad 401-2 electrically connected to the second fan-out line 402-2. The first sub-pad 401-1 is disposed in the first conductive layer 501 of the first area 41-1', and the second sub-pad 401-2 is disposed in the second conductive layer 503 of the second area 41-2'.

[0086] It should be noted that the wiring method used by the fan-out lines in the fan-out area of this embodiment is not limited to Figure 6 In the layer switching method shown, without considering the consistency of the wiring resistance, the first fan-out wiring 402-1 can be entirely located in the first conductive layer, and the second fan-out wiring 402-2 can be entirely located in the second conductive layer, which will not be described in detail herein.

[0087] specific Figure 9For example, the first conductive layer 501 further includes a first metal oxide layer 506 in direct contact with the first conductive layer 501 below, and the first region 41-1' and the second region 41-2' both include the first metal oxide layer 506. In addition, the second conductive layer 503 further includes an active layer 507 in direct contact with the second conductive layer 503 below, and the first region 41-1' and the second region 41-2' both include the active layer 507. From a manufacturing process perspective, when the array substrate uses a grayscale mask process (Half Tune) to pattern the first conductive layer 501 and the second conductive layer 503, the underlying film layer will be retained during patterning.

[0088] Of course, this embodiment is also applicable to an array substrate in which the first conductive layer and the second conductive layer are patterned using a non-grayscale mask process (HalfTune). In this case, the first binding region may not include the first metal oxide layer 506 and the active layer 507, which will not be described in detail here.

[0089] The above arrangement, by providing the first area with the first sub-pad and the second area with the second sub-pad in the first binding area, both include the same film layer, and the binding surfaces of all the first pads are at the same distance from the substrate, so that the pads to be bound to the first pads and the contact surfaces of each first pad are subjected to consistent force, thereby ensuring a narrow frame design in which fan-out lines are arranged using different conductive layers, improving the binding yield, avoiding in-plane dark line defects, and improving the product yield of narrow frame products.

[0090] In addition, from the perspective of the overall preparation process, in this example, when patterning the first conductive layer 501, the same Figure 5 In the embodiment of the present invention, different mask plates are used for patterning. The first and second areas in the first binding area use the same mask pattern to ensure that the first conductive layer and the film layer below the two areas are consistent. Accordingly, when the second conductive layer 503 is patterned, the same mask pattern will also be used. Figure 5 In the embodiment, different mask plates are patterned, and the first area and the second area in the first binding area use the same mask pattern to ensure that the second conductive layer and the film layer thereunder in the two areas are consistent.

[0091] Alternatively, refer to Figure 9 As shown, in this example, the first region 41-1' may further include a pad protection layer 508 disposed on the passivation layer 504 to protect the first sub-pad 401-1 from oxidation due to contact with air, thereby improving the bonding yield. Simultaneously, the second region 41-2' also includes a pad protection layer 508 disposed on the passivation layer 504 to protect the second sub-pad 401-2 from oxidation due to contact with air, thereby improving the bonding yield. The pad protection layer 508 may be made of a metal oxide material. From a manufacturing process perspective, if the array substrate is a liquid crystal display panel, it may be made of a pixel electrode layer, but the present invention is not limited to this.

[0092] Continue to refer to Figure 9 As shown, the surface of the first area 41-1' away from the base substrate 500 is the surface of the pad protection layer 508 away from the base substrate 500, and the surface of the second area 41-2' away from the base substrate 500 is the surface of the pad protection layer 508 away from the base substrate 500. The distance from the surface of the first area 41-1' and the second area 41-2' away from the substrate 500 to the base substrate 500 is h2.

[0093] It can be seen that when the first bonding area 41 includes the pad protection layer 508, this embodiment can still achieve the distance between the surface of the first area away from the substrate and the substrate being equal to the distance between the surface of the second area away from the substrate and the substrate, thereby improving the bonding yield and avoiding the dark line defect in the surface, thereby improving the product yield of the narrow frame product. The bonding diagram between the first bonding pad and the bonding pad to be bonded will be the same as Figure 7 The effects shown are similar and will not be described in detail here.

[0094] Alternatively, in order to enhance the binding effect, the vias forming the binding connection may also be further patterned.

[0095] Please refer to Figure 8 As shown in the binding effect diagram, the first area 41-1' may include a first via TK1 passing through the passivation layer 504 to the first conductive layer 501, and the second area 41-2' may include a second via TK2 passing through the passivation layer 504 to the second conductive layer 503, and the orthographic projection of each of the first via TK1 and the second via TK2 on the substrate base 500 is a snake.

[0096] Through this arrangement, when the pad to be bound is bound to the first pad 401 , the contact area is increased, the bonding effect is improved, the binding effectiveness is improved, and thus the yield rate is improved.

[0097] In some other optional embodiments, referring to Figure 10 and 11 As shown, this embodiment is different from the embodiment described above in that the first pads 401 are all arranged on the first conductive layer 503, and the multiple first pads 401 include a first sub-pad 401-1 electrically connected to the first fan-out line 402-1 and a second sub-pad 401-2 electrically connected to the second fan-out line 402-2.

[0098] It should be noted that in Figure 11 In the example shown, for ease of illustration, the first conductive layer 501 uses the gate layer identified above, and the second conductive layer 503 uses the source-drain metal layer identified separately, but the present disclosure is not limited to this. The first conductive layer can also be a source-drain metal layer and the second conductive layer can also be a gate layer.

[0099] The array substrate further includes a transfer area 43 disposed between the fan-out area 42 and the first binding area 41. The transfer area 43 includes a plurality of first sub-transfer portions electrically connected to the first sub-pads 401-1 in a one-to-one correspondence and a plurality of second sub-transfer portions electrically connected to the second sub-pads 401-2 in a one-to-one correspondence.

[0100] The first sub-transfer portion 403-1 is arranged on the first conductive layer 501, and the second sub-transfer portion includes a first sub-portion 413-2 arranged on the first conductive layer 501 and a second sub-portion 423-2 arranged on the second conductive layer 503. The first end of the first sub-transfer portion 403-1 is electrically connected to the first sub-pad 401-1, and the other end is electrically connected to the first fan-out line 402-1. The first end of the first sub-portion 413-2 is electrically connected to the second sub-pad 402-2, and the second end is electrically connected to the first end of the second sub-portion 423-2 via a via TK3 passing through the second conductive layer 503. The second end of the second sub-portion 423-2 is electrically connected to the second fan-out line 402-2.

[0101] Through this setting, the connection area set between the binding area and the fan-out area is used as an intermediate transfer structure, and all the first pads are set to be located on the same conductive layer, and the film layer transfer is performed using the connection area, so as to ensure that the contact surface height of all the first pads and the pads to be bound are consistent, thereby ensuring that the force on all pads is consistent, thereby improving the binding yield while designing a narrow frame.

[0102] Optionally, refer to Figure 12 As stated, Figure 12 Another possible implementation of the connection region 43 is shown. In this example, the first sub-transition portion includes a first sub-portion 413-1 disposed on the second conductive layer 503 and two second sub-portions 423-1 disposed on the first conductive layer 501, and the second sub-transition portion includes a first sub-portion 413-2 disposed on the second conductive layer 503 and one second sub-portion 423-2 disposed on the first conductive layer 503.

[0103] Among them, the two ends of the first sub-part 413-1 of the first sub-transfer part are electrically connected to the two second sub-parts 423-1 via the via TK3 penetrating the second conductive layer 503, and the other ends of the two second sub-parts 423-1 are electrically connected to the first sub-pad 401-1 and the first fan-out line 402-1 respectively; the first end of the first sub-part 413-2 of the second sub-transfer part is electrically connected to one end of its second sub-part 423-2 via the via TK3 penetrating the second conductive layer 503, and the second end is electrically connected to the second fan-out line 402-2, and the other end of the second sub-part 423-2 is electrically connected to the second sub-pad 401-2.

[0104] Through this setting, the connection area set between the binding area and the fan-out area is used as an intermediate transfer structure, and all the first pads are set to be located on the same conductive layer, and the film layer transfer is performed using the connection area, so as to ensure that the contact surface height of all the first pads and the pads to be bound are consistent, thereby ensuring that the force on all pads is consistent, thereby improving the binding yield while designing a narrow frame.

[0105] Based on the same inventive concept, another embodiment of the present disclosure provides a display panel including the array substrate described above.

[0106] Since the array substrate included in the display panel provided in the embodiment of the present disclosure corresponds to the array substrates provided in the above-mentioned embodiments, the previous implementation is also applicable to the use method provided in this embodiment and will not be described in detail in this embodiment.

[0107] The display panel disclosed herein provides a first binding area having multiple pad areas, wherein the multiple pad areas include a first area and a second area. The pads arranged in the first area and the pads arranged in the second area are located in different conductive layers, and the surface heights of the first area and the second area are the same, thereby ensuring good contact between the pads bound to the pad area, thereby improving the binding yield while performing a narrow frame design and improving the yield of the display product.

[0108] Based on the same inventive concept, another embodiment of the present disclosure provides a display module, referring to Figure 13 As shown, it includes the display panel and the flexible circuit board 60 described above. The flexible circuit board 60 includes a second pad area 61. The second pad area 61 includes a plurality of second pads 601. The second pads 601 are electrically connected to the first pads 401 in a one-to-one correspondence.

[0109] Since the array substrate included in the display module provided in the embodiment of the present disclosure corresponds to the array substrates provided in the above-mentioned embodiments, the previous implementation is also applicable to the use method provided in this embodiment and will not be described in detail in this embodiment.

[0110] The display module disclosed herein can improve the uniformity of contact force between the first pad in the display panel and the corresponding second pad in the flexible circuit board, thereby improving the binding yield of the first pad and the second pad, and further improving the yield of the display product.

[0111] Based on the same inventive concept, another embodiment of the present disclosure provides a display device, including the display panel described above.

[0112] Since the display panel included in the display device provided in the embodiment of the present disclosure corresponds to the display panels provided in the above-mentioned embodiments, the previous implementation manner is also applicable to the use method provided in this embodiment and will not be described in detail in this embodiment.

[0113] In this embodiment, the display device can be any product or component with a display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, car display, digital photo frame or navigation system. By loading the above display panel, the display device can avoid poor display and improve product stability and life.

[0114] Obviously, the above embodiments of the present disclosure are merely examples for clearly illustrating the present disclosure, and are not intended to limit the implementation methods of the present disclosure. For ordinary technicians in the relevant field, other different forms of changes or modifications can be made based on the above description. It is impossible to list all the implementation methods here. All obvious changes or modifications derived from the technical solutions of the present disclosure are still within the scope of protection of the present disclosure.

Claims

1. An array substrate, characterized in that: include: A display area and a non-display area surrounding the display area are provided on a base substrate, wherein the non-display area includes a first binding area provided on a first side of the display area and a fan-out area provided between the first binding area and the display area. The first bonding area includes: a plurality of pad areas arranged in sequence along a direction, each pad area includes a first pad, The fan-out region includes: a plurality of fan-out lines electrically connected to the plurality of first pads in a one-to-one correspondence, The plurality of fan-out lines include a first fan-out line and a second fan-out line, wherein a portion of the first fan-out line close to the first pad electrically connected thereto is located in a first conductive layer, and a portion of the second fan-out line close to the first pad electrically connected thereto is located in a second conductive layer, and the first conductive layer and the second conductive layer are different. The plurality of pad regions include a first region in which a first pad is electrically connected to the first fan-out line and a second region in which a first pad is electrically connected to the second fan-out line, The distance between the first region and the substrate surface away from the substrate is equal to the distance between the second region and the substrate surface away from the substrate.

2. The array substrate according to claim 1, wherein: The first binding region includes: the first conductive layer, the first insulating layer, the second conductive layer, the passivation layer and the planarization layer stacked on the base substrate, The first region includes the base substrate, the first conductive layer, the first insulating layer, the passivation layer, and the planarization layer stacked in sequence. The second region includes: the base substrate, the first insulating layer, the second conductive layer, the passivation layer, and the planarization layer stacked in sequence. The plurality of first pads include a first sub-pad electrically connected to the first fan-out line and a second sub-pad electrically connected to the second fan-out line, The first sub-pad is disposed in the first conductive layer of the first region, and the second sub-pad is disposed in the second conductive layer of the second region.

3. The array substrate according to claim 1, wherein: The film layer included in the first area is the same as the film layer included in the second area, Each of the first region and the second region includes: the base substrate, the first conductive layer, the first insulating layer, the second conductive layer, and the passivation layer stacked in sequence. The plurality of first pads include a first sub-pad electrically connected to the first fan-out line and a second sub-pad electrically connected to the second fan-out line, The first sub-pad is disposed in the first conductive layer of the first region, and the second sub-pad is disposed in the second conductive layer of the second region.

4. The array substrate according to claim 1, wherein: The first pad is provided on the first conductive layer. The plurality of first pads include a first sub-pad electrically connected to the first fan-out line and a second sub-pad electrically connected to the second fan-out line, The array substrate further includes a transfer area disposed between the fan-out area and the first binding area. The transfer area includes a plurality of first sub-transfer portions electrically connected to the first sub-pads in a one-to-one correspondence and a plurality of second sub-transfer portions electrically connected to the second sub-pads in a one-to-one correspondence. The first sub-transfer portion is provided on a first conductive layer, the second sub-transfer portion includes a first sub-portion provided on the first conductive layer and a second sub-portion provided on the second conductive layer, a first end of the first sub-transfer portion is electrically connected to the first sub-pad, and the other end is electrically connected to the first fan-out line, a first end of the first sub-portion is electrically connected to the second sub-pad, and a second end is electrically connected to the first end of the second sub-portion via a via penetrating the second conductive layer, and a second end of the second sub-portion is electrically connected to the second fan-out line; or The first sub-transfer portion includes a first sub-portion arranged on the second conductive layer and two second sub-portions arranged on the first conductive layer, the second sub-transfer portion includes a first sub-portion arranged on the second conductive layer and a second sub-portion arranged on the first conductive layer, the two ends of the first sub-portion of the first sub-transfer portion are respectively electrically connected to the two second sub-portions via vias passing through the second conductive layer, and the other ends of the two second sub-portions are respectively electrically connected to the first sub-pad and the first fan-out line, the first end of the first sub-portion of the second sub-transfer portion is electrically connected to one end of its second sub-portion via a via passing through the second conductive layer, the second end is electrically connected to the second fan-out line, and the other end of the second sub-portion is electrically connected to the second sub-pad.

5. The array substrate according to claim 4, wherein: The first conductive layer is a gate layer, the second conductive layer is a source / drain metal layer, or, The first conductive layer is a source-drain metal layer, and the second conductive layer is a gate layer.

6. The array substrate according to claim 2, wherein: The second region further includes: an active layer disposed between the first insulating layer and the second conductive layer, The first conductive layer is a gate layer, the second conductive layer is a source / drain metal layer, and the second conductive layer is in direct contact with the active layer.

7. The array substrate according to claim 3, wherein: The first region includes a first via hole penetrating from the passivation layer to the first conductive layer, and the second region includes a second via hole penetrating from the passivation layer to the second conductive layer. An orthographic projection of each of the first via hole and the second via hole on the base substrate is serpentine.

8. A display panel, characterized in that: The invention comprises the array substrate according to any one of claims 1 to 7.

9. A display module, characterized in that: include: The display panel and the flexible circuit board according to claim 8, The flexible circuit board includes a second pad area, and the second pad area includes a plurality of second pads. The second pads are electrically connected to the first pads in a one-to-one correspondence.

10. A display device, characterized in that: The display panel comprises the display panel according to claim 8.

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