Generation circuit of back gate bias voltage

Abstract

The invention discloses a back gate bias voltage generation circuit, relates to the technical field of integrated circuits, and aims to solve the problem of low anti-interference performance of an oscillator in the prior art. The generation circuit of the back gate bias voltage comprises a transistor performance detection circuit, a storage and calculation integrated circuit and a driving circuit, the transistor performance detection circuit is used for detecting integrated circuit performance offset information of N back offset domains on a target integrated circuit; the transistor performance detection circuit comprises N groups of performance detection sub-circuits, and each group of performance detection sub-circuit is used for detecting integrated circuit performance offset information of a back offset domain; n is a positive integer greater than 1; the storage and calculation integrated circuit at least comprises a memory array; the storage and calculation integrated circuit is used for storing and calculating the performance offset information of the integrated circuit; the driving circuit is used for generating a target back gate bias voltage. According to the invention, the signal response speed can be improved, the control structure is simplified, and the local change of chip performance is accurately compensated.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a circuit for generating a back gate bias voltage. Background Art

[0002] As the process nodes of bulk logic devices shrink with each generation, the performance of radio frequency integrated circuits (RFICs), such as those used in 5G applications, has inevitably been subject to analog performance degradation brought on by scaling. Battery-powered 5G devices constantly face a trade-off between power consumption and performance. Process variations introduced during IC manufacturing, as well as fluctuations in voltage and temperature during high-performance operation, constantly threaten the lifespan of electronic devices.

[0003] The thin film structure introduced by FD-SOI (Full Depletion-Silicon On Insulator) technology eliminates the limitations of analog performance caused by deep submicron processes, and can improve short channel effects and subthreshold characteristics. Therefore, integrated circuits designed using this technology can achieve higher bandwidth or lower power consumption at a given bandwidth.

[0004] The buried oxide layer under the FD-SOI transistor channel prevents charge leakage from the S / B junction, which gives the FD-SOI CMOS device a back-gate voltage control range far higher than that of bulk silicon CMOS devices (±3V vs. ±0.3V). Figure 1 As shown, the structure is the existing structure.

[0005] See also Figure 2 , FBB is forward back bias, RBB is reverse back bias, PLVT is low threshold PMOS, NLVT is low threshold NMOS. (This figure shows the corresponding relationship between the back bias voltage (VBB) and the threshold voltage (Vth) of FD-SOIMOSFET (fully depleted silicon metal-oxide-semiconductor field-effect transistor on insulator). Figure 2It can be seen that forward back bias (FBB) and reverse back bias (RBB) have different effects: for low-threshold NMOS (NLVT) and low-threshold PMOS (PLVT), forward back bias (FBB) and reverse back bias (RBB) cause threshold voltage changes in different directions and degrees. Taking the NLVT as an example, the NLVTFBB curve shows that the threshold voltage decreases with increasing forward back bias voltage; while the NLVTRBB curve shows that the threshold voltage increases with increasing reverse back bias voltage. This demonstrates that the threshold voltage of a MOSFET can be adjusted by applying different types of back bias voltage. In summary, applying a voltage to the back gate of an FD-SOI CMOS device can effectively control the device's threshold voltage, thereby regulating circuit power consumption and compensating for on-chip PVT variations. A circuit that can generate the required back gate bias voltage based on circuit operating conditions is called a back bias generation circuit.

[0006] The current back-bias voltage generation circuit is based on the architecture of digital critical paths and digital control circuits, such as the digital circuit, counter, digital control unit, and charge pump unit structure used in U.S. patent application US201816633291A. The control unit, hardware performance monitor, and charge pump unit in this patent are connected in a closed-loop control loop, and the digital control unit is used to process the digital output based on the digital critical path and counter to adjust the working state of the charge pump. However, the architecture based on digital critical paths and digital control circuits in this technology is a highly integrated integrated circuit, which has the following defects: the back-bias voltage generation circuit architecture based on digital control circuits leads to a slow response speed and a complex control structure. The highly integrated control loop is not conducive to the segmentation of back-bias domains in large-area integrated circuits, and it is difficult to meet the needs of compensating for process fluctuations or local changes in voltage and temperature within the chip. Summary of the Invention

[0007] The object of the present invention is to provide a back gate bias voltage generating circuit for solving the problems of slow signal response speed, complex control structure and inability to accurately compensate for local changes in chip performance.

[0008] In order to achieve the above object, the present invention provides the following technical solutions:

[0009] The present invention provides a back gate bias voltage generating circuit, comprising at least:

[0010] Transistor performance detection circuit, storage and calculation integrated circuit and driving circuit;

[0011] The transistor performance detection circuit is used to detect integrated circuit performance offset information of N back-biased domains on a target integrated circuit; the transistor performance detection circuit includes N groups of performance detection sub-circuits, each group of performance detection sub-circuits is used to detect integrated circuit performance offset information of one back-biased domain; N is a positive integer greater than 1;

[0012] The storage and calculation integrated circuit comprises at least a memory array; the storage and calculation integrated circuit is used to store and calculate the integrated circuit performance deviation information;

[0013] The driving circuit is used to generate a target back gate bias voltage.

[0014] Optionally, the back gate bias voltage generating circuit further comprises: a selection input multiplexing circuit and a selection output multiplexing circuit;

[0015] The output end of the transistor performance detection circuit is connected to the input end of the selection input multiplexing circuit, and the output end of the selection input multiplexing circuit is connected to the input end of the storage and calculation integrated circuit; the output end of the storage and calculation integrated circuit is connected to the input end of the selection output multiplexing circuit, and the output end of the selection output multiplexing circuit is connected to the input end of the driving circuit;

[0016] The selection input multiplexing circuit is used to sequentially send the output signal of the transistor performance detection circuit to the storage and calculation integrated circuit;

[0017] The selection output multiplexing circuit is used to send the output signals of the storage and calculation integrated circuit to the driving circuit in sequence.

[0018] Optionally, each group of performance detection sub-circuits includes a PMOS transistor performance detection circuit and an NMOS transistor performance detection circuit;

[0019] The memory array includes a first target memory array and a second target memory array; the first target memory array and the second target memory array each include a plurality of storage bits;

[0020] Each storage bit in the first target memory array is pre-written with weight information corresponding to the PMOS transistor;

[0021] Each storage bit in the second target memory array is pre-written with weight information corresponding to the NMOS transistor;

[0022] The first target memory array includes N signal input ports;

[0023] The second target memory array includes N signal input ports;

[0024] The integrated storage and computing circuit also includes a first current-voltage conversion circuit and a second current-voltage conversion circuit; the first current-voltage conversion circuit is connected to the first target memory array; the second current-voltage conversion circuit is connected to the second target memory array.

[0025] Optionally, the driving circuit includes N driving modules, each driving module includes a pump-up charge pump and a pump-down charge pump;

[0026] Each pump-up charge pump is connected to a PMOS transistor in the back-biased domain;

[0027] Each pump-down charge pump is connected to an NMOS transistor in the back-biased domain.

[0028] Optionally, the first target memory array and the second target memory array each include a word line for transmitting an input signal and a bit line for outputting a convolution operation result;

[0029] When the integrated circuit performance deviation information from the PMOS transistor performance detection circuit is input to a row of bits in the first target memory array, each column of bit lines performs a convolution operation on the bit weight of the column and the input signal, and sends the convolution result in the form of current to the first current-voltage conversion circuit; the first current-voltage conversion circuit converts the corresponding convolution result into a corresponding target control signal to control the corresponding pump-up charge pump;

[0030] When integrated circuit performance deviation information from the NMOS transistor performance detection circuit is input to a row of bits in the second target memory array, each column of bit lines performs a convolution operation on the bit weight of the column with the input signal, and sends the convolution result in the form of current to the second current-voltage conversion circuit. The second current-voltage conversion circuit converts the corresponding convolution result into a corresponding target control signal to control the corresponding pump-down charge pump.

[0031] Optionally, the PMOS transistor performance detection circuit includes a PMOS delay line, a first rising edge counter and a first digital subtractor;

[0032] The NMOS transistor performance detection circuit includes an NMOS delay line, a second rising edge counter and a second digital subtractor;

[0033] The memory array is a memory array based on an SRAM architecture.

[0034] Optionally, the selection input multiplexing circuit and the selection output multiplexing circuit each include N PMOS signal selection circuits and N NMOS signal selection circuits.

[0035] Optionally, the PMOS signal selection circuit and the NMOS signal selection circuit both include: a first NMOS transistor, a second NMOS transistor and a third NMOS transistor;

[0036] The gates of the first NMOS transistor, the second NMOS transistor, and the third NMOS transistor are all connected to corresponding clock signals;

[0037] The drain of the first NMOS transistor is connected to a detection signal; the first NMOS transistor and the second NMOS transistor are connected in series; the source of the second NMOS transistor outputs the detection signal;

[0038] The source of the first NMOS transistor and the drain of the second NMOS transistor are both connected to the drain of the third NMOS transistor.

[0039] Optionally, the pump-up charge pump and the pump-down charge pump each include: a first current array, a second current array, a first inverter, a second inverter, a first capacitor, a second capacitor, and a CMOS cross-coupling pair;

[0040] The power supply ends of the first current array and the second current array are both connected to a power supply;

[0041] The signal input terminals of the first current array and the second current array are both connected to the target control signal;

[0042] The first current array is connected to the first inverter; the signal output terminal of the first inverter is connected to the first terminal of the first capacitor; the input terminal of the first inverter is connected to the first clock signal; the second terminal of the first capacitor is connected to the CMOS cross-coupling pair;

[0043] The second current array is connected to the second inverter; the signal output end of the second inverter is connected to the first end of the second capacitor; the input end of the second inverter is connected to the second clock signal; and the second end of the second capacitor is connected to the CMOS cross-coupling pair.

[0044] Optionally, the first current array and the second current array both include: a third PMOS transistor, a fourth PMOS transistor, and a plurality of MOS transistor branches, each MOS transistor branch including three PMOS transistors connected in series;

[0045] The third PMOS transistor and the fourth PMOS transistor are connected in series to provide a bias voltage for the multiple MOS transistor branches;

[0046] The gate of the third PMOS transistor is connected to the multiple MOS transistor branches;

[0047] The gate of the fourth PMOS transistor is connected to the source of the fourth PMOS transistor;

[0048] The gate of the first PMOS transistor in each MOS transistor branch is connected to the target control signal;

[0049] The gate of the second PMOS tube in each MOS tube branch serves as the bias voltage terminal;

[0050] The gate of the third PMOS transistor in each MOS transistor branch serves as a switch end of the branch and is connected to the branch selection signal.

[0051] The beneficial effects of the present invention are as follows: the present invention provides a back-gate bias voltage generation circuit, and the transistor performance detection circuit directly collects the integrated circuit performance offset information on each back-bias domain and generates a corresponding detection signal. Compared with the digital critical path and digital control circuit architecture based on which the signal must be processed by multiple complex digital units, a large number of intermediate links are reduced here, thereby improving the response speed. The memory array of the storage and calculation integrated circuit performs calculations on the detection signal to ultimately generate the target control signal. The memory array can quickly search and output corresponding control signals based on a preset algorithm structure and data mapping relationship, eliminating the need for complex logical operations and signal conversion required by digital control circuits. Instead of slowly searching and analyzing data from numerous digital cells, as in traditional digital circuits, this accelerates signal processing and further improves overall response speed. The transistor performance detection circuit focuses on collecting back-bias domain performance offset information, while the integrated storage and computation circuit processes the collected signals. The driver circuit generates a back-gate bias voltage based on the processed signals. Each circuit has a distinct task, eliminating the need for a single module to perform multiple complex functions and maintain intricate connections with other modules, as in traditional digital control circuit architectures. This clear division of labor naturally leads to a relatively simple control structure. The transistor performance detection circuit includes N groups of performance detection sub-circuits, each corresponding to a back-bias domain. Essentially, this divides a large integrated circuit chip into multiple independent back-bias domains, each with its own dedicated performance detection sub-circuit for monitoring and management. When process fluctuations or local changes in voltage or temperature occur in a certain back-bias domain, the corresponding performance detection sub-circuit can independently collect and process information without affecting the operation of other back-bias domains. This is conducive to the segmentation of back-bias domains, so as to accurately compensate for local performance changes in the target integrated circuit or chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0052] The drawings described herein are used to provide a further understanding of the present invention and constitute a part of the present invention. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the drawings:

[0053] Figure 1It is a structural diagram of the FD-SOICMOS device in the prior art;

[0054] Figure 2 This is the result of gate voltage test on FD-SOICMOS device;

[0055] Figure 3 One of the circuit structure schematic diagrams of a back gate bias voltage generating circuit provided by one embodiment of the present invention;

[0056] Figure 4 A second circuit structure diagram of a back-gate bias voltage generating circuit provided in one embodiment of the present invention;

[0057] Figure 5 A schematic diagram of a partial circuit structure of a memory array with a back gate bias voltage provided by one embodiment of the present invention;

[0058] Figure 6 A schematic structural diagram of a PMOS transistor performance detection circuit provided by one embodiment of the present invention;

[0059] Figure 7 A schematic structural diagram of an NMOS transistor performance detection circuit provided by one embodiment of the present invention;

[0060] Figure 8 A schematic structural diagram of a signal selection circuit provided by one embodiment of the present invention;

[0061] Figure 9 A schematic diagram of the circuit structure of a pump-on charge pump provided in one embodiment of the present invention;

[0062] Figure 10 A schematic diagram of the circuit structure of a first current array provided in one embodiment of the present invention;

[0063] Figure numerals: 10-transistor performance detection circuit; 11-performance detection sub-circuit; 110-PMOS transistor performance detection circuit; 111-PMOS delay line; 112-first rising edge counter; 113-first digital subtractor; 120-NMOS transistor performance detection circuit; 121-NMOS delay line; 122-second rising edge counter; 123-second digital subtractor; 20-storage and calculation integrated circuit; 21-first target memory array; 22-second target memory array; 23-first current-voltage conversion circuit; 210-storage bit; 30-driving circuit; 40-select input multiplexing circuit; 50-select output multiplexing circuit. DETAILED DESCRIPTION

[0064] To facilitate a clear description of the technical solutions of the embodiments of the present invention, the words "first" and "second" are used in the embodiments of the present invention to distinguish between identical or similar items with substantially the same functions and effects. For example, the first threshold and the second threshold are merely used to distinguish between different thresholds and do not limit their order. Those skilled in the art will understand that the words "first" and "second" do not limit the quantity or execution order, and the words "first" and "second" do not necessarily mean different.

[0065] It should be noted that, in the present invention, words such as "exemplary" or "for example" are used to indicate examples, illustrations, or descriptions. Any embodiment or design described as "exemplary" or "for example" in the present invention should not be construed as being preferred or advantageous over other embodiments or designs. Rather, the use of words such as "exemplary" or "for example" is intended to present the relevant concepts in a concrete manner.

[0066] In the present invention, "at least one" means one or more, "more than one" means two or more, and "and / or" describes the association relationship between associated objects, indicating that three types of relationships can exist.

[0067] See also Figure 3 , an embodiment of the present invention provides a back-gate bias voltage generation circuit, which may include: a transistor performance detection circuit 10, a storage and calculation integrated circuit 20 and a driving circuit 30;

[0068] The transistor performance detection circuit 10 is used to detect integrated circuit performance offset information of N back-biased domains on a target integrated circuit. The transistor performance detection circuit includes N groups of performance detection sub-circuits, each group of performance detection sub-circuits is used to detect integrated circuit performance offset information of a back-biased domain. N is a positive integer greater than 1. The integrated circuit performance offset information may include PMOS performance offset information obtained by detecting PMOS transistors and NMOS performance offset information obtained by detecting NMOS transistors.

[0069] The storage and calculation integrated circuit includes at least a memory array; the storage and calculation integrated circuit is used to store and calculate the integrated circuit performance deviation information;

[0070] The driver circuit is used to generate a target back-gate bias voltage.

[0071] Beneficial effect analysis of this embodiment:

[0072] Conventional technology uses a digital key path and digital control circuit architecture to generate a back gate bias voltage.

[0073] (1) In the traditional architecture, the sensor acquisition signal is converted into a digital circuit signal. In the digital circuit, the signal transmission must pass through multiple logic gates and processing units. Each unit has signal transmission delay and processing time. Moreover, on the digital critical path, the signal must pass through these units in a specific order. Once a delay occurs in a certain link, it will affect the overall response speed. Especially in highly integrated integrated circuits, the various parts are tightly coupled, and factors such as signal interference will further slow down the response.

[0074] The transistor performance detection circuit in this embodiment directly collects integrated circuit performance deviation information on each back-biased domain. Compared to the signal processing required by multiple complex digital units in digital critical path and digital control circuit architectures, this eliminates a large number of intermediate links. For example, if a temperature rise in a certain area of a chip causes performance deviation, the transistor performance detection circuit can immediately sense the change and directly transmit it to the integrated storage and computing circuit, greatly shortening the time from sensing the change to generating the control signal, thereby improving response speed.

[0075] In addition, this embodiment uses a memory array of a storage and calculation integrated circuit to store and calculate the integrated circuit performance offset information, which can quickly search, calculate and generate corresponding control signals based on a preset algorithm structure and data mapping relationship. It does not require complex logical operations and signal conversions like digital control circuits, nor does it require slow search and analysis from a large number of digital units as in traditional digital circuits, thereby speeding up the signal processing speed and further improving the overall response speed.

[0076] (2) A back-bias voltage generation circuit based on a digital critical path and digital control circuit architecture is used to control chip operation. This architecture requires the integration of multiple functional modules such as digital circuits, counters, and digital control units, and the establishment of complex logical relationships and data exchange channels between them. Each sensor, actuator, and control node must exchange data and coordinate with the digital control unit. The digital control unit must process digital signals from various sources, including threshold voltages and currents fed back by sensors, and must perform calculations based on these signals through components such as counters to control the working status of units such as charge pumps. The functions and parameter settings of each module require fine-tuning and coordination. Once the system scale expands or functional requirements increase, the interaction and control logic between modules will grow exponentially, making the control structure extremely complex.

[0077] This embodiment is mainly divided into three main parts: transistor performance detection circuit, storage and calculation integrated circuit and driving circuit. The transistor performance detection circuit focuses on collecting back-gate performance offset information, the storage and calculation integrated circuit is responsible for storing and processing the collected signals, and the driving circuit generates the back-gate bias voltage according to the processed signals. Each circuit has a clear task, and there is no need for a module to undertake multiple complex functions and have intricate connections with other modules as in the traditional digital control circuit architecture. With such a clear division of labor, the control structure is naturally relatively simple, which is easy to manage and maintain.

[0078] Furthermore, in this embodiment, the functional modules of each circuit have clear divisions of labor, and the logical interactions between them are relatively simple. The transistor performance detection circuit transmits integrated circuit performance deviation information to the integrated storage and computing circuit, which then processes the signal and transmits it to the driver circuit. This linear signal transmission and processing flow avoids the complex meshed logic relationships between multiple digital units found in traditional digital control circuits, simplifying the control structure.

[0079] (3) In the traditional architecture, the various circuit modules in the highly integrated control loop are tightly coupled, and the signal transmission and control logic are based on the overall design. When back-bias domain segmentation is to be performed, it is difficult to adjust and control the back-bias voltage of a certain area without affecting the normal operation of other areas due to the close interrelationship between the various parts. Moreover, the wiring and signal transmission paths under this architecture are fixed, which makes it difficult to adapt to the special needs of different back-bias domains, so it is not conducive to back-bias domain segmentation in large-area integrated circuits. Suppose there is an integrated circuit chip (large-area integrated circuit) as large as a football field, and back-bias domain segmentation is required to adapt to the process fluctuations, voltage and temperature changes that may exist in different areas. The back-bias voltage generation circuit based on the digital critical path and digital control circuit architecture is like the rooms (circuit modules) in a large, closed building that are closely connected, making it difficult to perform flexible spatial division (back-bias domain segmentation). If a special back-bias voltage adjustment is to be performed in a certain area to compensate for the process problems in that area, the entire building (control loop) needs to be rebuilt and rewired on a large scale.

[0080] In this embodiment, the transistor performance detection circuit includes N groups of performance detection sub-circuits, and each group of performance detection sub-circuits corresponds to a back-bias domain. In essence, a target integrated circuit (also referred to as a target chip) is divided into multiple independent back-bias domains, and each back-bias domain has its own exclusive performance detection sub-circuit to monitor and manage. When a back-bias domain experiences process fluctuations or local changes in voltage or temperature, the corresponding performance detection sub-circuit can independently collect and process information without affecting the work of other back-bias domains, which is conducive to the division of the back-bias domain so as to accurately compensate for local performance changes in the target integrated circuit or chip.

[0081] The integrated storage and computation circuit calculates the IC performance offset information for each back-bias domain to generate a target control signal. The driver circuit then generates a corresponding target back-gate bias voltage for each back-bias domain based on this information. This means the back-gate bias voltage can be flexibly adjusted based on the actual conditions of different back-bias domains. This allows for precise compensation and control of the back-bias domains without requiring large-scale changes to the control loop. This allows for precise compensation and control of the back-bias domains, facilitating accurate compensation for local performance variations within the target integrated circuit or chip.

[0082] In an optional embodiment, for Figure 1 For FD-SOICMOS devices like the one in [1], the target integrated circuit includes multiple CMOS transistors, and each back-biased domain can correspond to a CMOS transistor, see Figure 4 The transistor performance detection circuit 10 includes, for example, N groups of performance detection sub-circuits 11, and each group of performance detection sub-circuits 11 includes a PMOS transistor performance detection circuit and an NMOS transistor performance detection circuit, so that separate detection and separate performance compensation of PMOS transistors and NMOS transistors in CMOS tubes can be achieved.

[0083] It should be noted that the detection signal is obtained by the transistor performance detection circuit performing conventional signal processing (such as filtering, etc., which can be referred to in related technologies) on the integrated circuit performance offset information of each back-biased domain. Specifically, an NMOS detection signal is obtained by an NMOS transistor performance detection circuit processing the corresponding integrated circuit performance offset information (i.e., NMOS performance offset information), and a PMOS detection signal is obtained by a PMOS transistor performance detection circuit processing the corresponding integrated circuit performance offset information (i.e., PMOS performance offset information).

[0084] Based on the two types of transistors, PMOS transistors and NMOS transistors, when designing memory arrays and driver circuits, further circuit refinement design will be carried out according to the different types of PMOS transistors and NMOS transistors. Figure 4, the memory-computation integrated circuit 20 is divided into a first target memory array 21 corresponding to the PMOS transistor and a second target memory array 22 corresponding to the NMOS transistor; for another example, see Figure 4 The driving circuit includes N driving modules, each driving module includes a pump-up charge pump and a pump-down charge pump, and each driving module corresponds to a back-bias domain. For the driving circuit 30, it always includes a pump-up charge pump 1, a pump-up charge pump 2 to a pump-up charge pump N, and a pump-down charge pump 1, a pump-down charge pump 2 to a pump-down charge pump N; each pump-up charge pump corresponds to a PMOS transistor in the back-bias domain; each pump-down charge pump corresponds to an NMOS transistor in the back-bias domain.

[0085] The integrated storage and computing circuit also includes a first current-to-voltage conversion circuit and a second current-to-voltage conversion circuit. The first current-to-voltage conversion circuit is connected to the first target memory array, while the second current-to-voltage conversion circuit is connected to the second target memory array. The memory array often outputs current signals, which need to be converted into corresponding voltage signals.

[0086] Taking the first target memory array as an example, see Figure 5 , the first target memory array 21 is connected to the first current-voltage conversion circuit 23 .

[0087] The first target memory array includes N signal input ports; a signal output port of each PMOS transistor performance detection circuit (output PMOS detection signal, see Figure 5 ) corresponds to a signal input port of the first target memory array. The second target memory array includes N signal input ports; the signal output port (outputting an NMOS detection signal) of each NMOS transistor performance detection circuit corresponds to a signal input port of the second target memory array.

[0088] The first target memory array and the second target memory array each include a plurality of storage bits; for example, the first target memory array and the second target memory array each include N rows and M columns of storage bits, where M is a positive integer greater than 1.

[0089] For the first target memory array, each storage bit in the first target memory array is pre-written with weight information corresponding to the PMOS transistor. For example, see Figure 5 , the first target memory array 21 is composed of a plurality of storage bits 210 .

[0090] Likewise, for the second target memory array, each storage bit in the second target memory array is pre-written with weight information corresponding to the NMOS transistor.

[0091] In an optional embodiment, in order to further improve the circuit performance, see Figure 4 The back gate bias voltage generating circuit may further include a selection input multiplexing circuit 40 and a selection output multiplexing circuit 50; the output end of the transistor performance detection circuit 10 is connected to the input end of the selection input multiplexing circuit 40, and the output end of the selection input multiplexing circuit 40 is connected to the input end of the storage and computing integrated circuit 20; the output end of the storage and computing integrated circuit 20 is connected to the input end of the selection output multiplexing circuit 50, and the output end of the selection output multiplexing circuit 50 is connected to the input end of the driving circuit 30; the selection input multiplexing circuit is used to send the output signal of the transistor performance detection circuit to the storage and computing integrated circuit in sequence; the selection output multiplexing circuit is used to send the output signal of the storage and computing integrated circuit to the driving circuit in sequence.

[0092] Analysis of the beneficial effects of this embodiment: The transistor performance detection circuit may generate signals of different types and properties. If transmitted simultaneously, these signals may conflict at the input ports of the integrated storage and computing circuit, such as signal level interference and signal timing confusion. Using a selective input multiplexing circuit to transmit detection signals sequentially can avoid this situation, ensuring that each signal is received and processed by the integrated storage and computing circuit at the appropriate time and in the correct state. Furthermore, when a problem occurs in the circuit, transmitting signals sequentially facilitates fault location. If signals are transmitted simultaneously, it is difficult to determine which signal is causing the problem if an error occurs. Transmitting signals sequentially, however, allows for rapid identification of abnormal signals by monitoring the processing of each signal. The beneficial effects of the selective output multiplexing circuit are the same as above and will not be further elaborated here. Furthermore, in the transistor performance detection circuit, the selective input and output multiplexing circuits transmit signals sequentially. In this operating mode, the control unit can be time-division multiplexed: that is, the same control unit can control and schedule different detection signals at different time points, eliminating the need for a separate control unit for each signal. This reduces the number of control units, thereby reducing the area occupied by the control units in the circuit and conserving chip area resources.

[0093] From the above multiple embodiments, it can be seen that the transistor performance detection circuit includes multiple groups of performance detection sub-circuits, each group corresponds to a back-bias domain, and can directly and quickly collect the integrated circuit performance offset information on the back-bias domain. Compared with the prior art where the signal needs to be transmitted and processed through multiple links in a complex digital circuit, the signal transmission delay and intermediate processing steps are reduced here, just like obtaining first-hand information directly at the scene of the incident, and the detection signal can be output at the first time; the input multiplexing circuit is selected to send the integrated circuit performance offset information to the storage and computing circuit in sequence. This sequential sending method avoids the competition for processing resources caused by the simultaneous influx of signals into the storage and computing circuit, so that the storage and computing circuit can receive and process signals in an orderly manner, improves the signal processing efficiency, and thus speeds up the overall response speed; the storage and computing circuit uses a memory array to perform calculations on the detection signal. The memory array can quickly store and calculate integrated circuit performance deviation signals, eliminating the tedious logical operations and signal conversion required by traditional digital control circuits. After calculations are performed in the memory array, corresponding control signals can be quickly generated, significantly reducing signal processing time. The output multiplexing circuit and driver circuit are selected: The output multiplexing circuit sequentially transmits the output signals of the storage and calculation circuit to the driver circuit, ensuring that the driver circuit receives the signals promptly and accurately. Based on this, the driver circuit quickly generates the corresponding target backgate bias voltage. The entire signal processing and voltage generation process is efficient and smooth, effectively solving the problem of slow response speed.

[0094] The transistor performance detection circuit focuses on collecting performance offset information in the back-bias domain, the storage and calculation integrated circuit is responsible for calculating and processing the detection signal, the driving circuit is used to generate the back-gate bias voltage, and the selection input and output multiplexing circuits are respectively responsible for the orderly transmission of signals. The functions of each module are clear, unlike the digital control circuit in the prior art, where one module undertakes multiple complex functions and the logical relationship between modules is intricate. The selection input multiplexing circuit transmits the output signal of the transistor performance detection circuit to the storage and calculation integrated circuit in sequence, and the selection output multiplexing circuit transmits the output signal of the storage and calculation integrated circuit to the driving circuit in sequence. This linear and orderly signal transmission method replaces the complex mesh signal interaction logic in the prior art, making the entire control structure simple and clear, easy to understand, design and maintain.

[0095] Regarding the working principle of the memory array: the first target memory array and the second target memory array both include word lines for transmitting input signals and bit lines for outputting convolution operation results;

[0096] When the integrated circuit performance deviation information from the PMOS transistor performance detection circuit (the PMOS transistor performance detection circuit processes the PMOS performance deviation information to obtain, for example, Figure 5After the PMOS detection signal 1) is sent to a row of bits via a word line in the first target memory array, each column of bit lines performs a convolution operation on the bit weight of the column (i.e., the column) and the input signal, and sends the convolution result in the form of current to the first current-voltage conversion circuit; the first current-voltage conversion circuit converts the corresponding convolution result into a corresponding target control signal to control the corresponding pump-up charge pump;

[0097] When integrated circuit performance deviation information from the NMOS transistor performance detection circuit is fed into a row of bits via a word line in the second target memory array, each column of bit lines performs a convolution operation on the bit weight of its column with the input signal, and transmits the convolution result in the form of current to the second current-voltage conversion circuit. The second current-voltage conversion circuit then converts the corresponding convolution result into a corresponding target control signal to control the corresponding pump-down charge pump.

[0098] In the target memory array of this embodiment, the function of the word line is to select a specific row of bits so that the integrated circuit performance deviation information (hereinafter referred to as the detection signal) can enter the bits in this row. When the bits in this row receive the detection signal, they will generate a corresponding electrical response (such as generating current) according to the weight stored in themselves. The bits in the same column do have the function of storing weights. When the row of bits selected by the word line generates an electrical response, although the bits in other rows in the same column do not directly receive the input signal, the weights they store will still affect this electrical response. Specifically, the bit line is an electrical path that connects the bits in the same column in a vertical direction. When the row of bits selected generates current, this current will flow on the bit line. Due to the existence of other rows of bits in the same column (their weights are reflected in the form of electrical parameters such as resistance, etc.), they will interact with the current on the bit line, so that the total current on the bit line is the result of the combined action of the weights of all bits in the same column (including the bits in the selected row and the bits in other rows). For example, to give a more specific example, assume that the memory array is a 3×3 matrix, A 11 、A 12 、A 13 、A 21 、A 22 、A 23 、A 31 、A 32 、A 33 These 9 bits (A ij When the word line is selected for row 1, the detection signal enters A 11 、A 12 、A 13 These three bits will generate current I according to their own weights. 11 , I 12 , I 13However, for column 1, A 21 and A 31 The stored weight will affect A 11 The resulting current is in the case of the first column bit line, and similarly, the second and third columns. Finally, the total current in the first column bit line is A 11 、A 12 、A 13 As a result of the combined effect of these three bit weights, the total current on the second row bit line is A 21 、A 22 、A 32 As a result of the combined effect of these three bit weights, the total current on the third row of bit lines is A 13 、A 23 、A 33 The weights of all three bits are used in the calculation, but the input signal is selected by the word line, and the weights of the bits in the same column are then added together via the bit line.

[0099] It can be understood that the weight written to each target memory array is also different, which usually means that the weight of each bit in each memory array is different. In actual applications, due to differences in manufacturing processes, the performance of NMOS and PMOS transistors will be different, which will lead to differences in the weights stored in each bit. Moreover, according to different computing requirements, each bit is also required to store different weight values, so as to achieve various complex computing tasks. Although in some specific cases, there may be situations where some bits have the same weight, the weight of each bit in the target memory array can be and usually is different to meet diverse computing needs and adapt to hardware characteristics.

[0100] Although all bits participate in the calculation, ensuring the same output for identical inputs, identical output for identical inputs is still crucial: ensuring deterministic calculation results. Determinism is crucial in circuit systems. Identical inputs produce identical outputs, making the circuits in this embodiment predictable. This helps developers debug, optimize, and verify system correctness.

[0101] Analysis of the beneficial effects of this embodiment: The first target memory array and the second target memory array in this embodiment both implement operations on detection signals based on the in-memory calculation principle. Each target memory array includes the same number of signal input ports as the detection signals, and can directly send the detection signals to the word line, and perform cumulative calculations in a charge sharing manner (corresponding to the output signal of the target memory array being a current). Therefore, the memory array in this embodiment is different from the traditional storage and calculation integrated chip architecture and does not require complex peripheral circuits. Each target memory array is pre-written with weights. Since the performance of NMOS and PMOS transistors is different, the weights written to each memory array are also different. The storage and calculation integrated circuit generates a target control signal for each back-biased domain to control the back-biased domain driver module according to the detection signal input by the selection input multiplexing circuit, and sends the output signal of the storage and calculation integrated circuit to the corresponding back-biased domain driver module one by one through the selection output multiplexing circuit. The pump-up charge pump and the pump-down charge pump in the driver module generate back-gate signals applied to the NMOS transistor body terminal and the PMOS transistor body terminal in the target integrated circuit according to the corresponding control signals. This embodiment encapsulates the complexity of traditional digital control circuit design in the target memory array, thereby achieving a simpler design process for the back-bias voltage generation circuit; by reusing the lookup table module, accurate performance compensation in multi-back-bias domain integrated circuits is achieved.

[0102] In addition, the storage and calculation integrated circuit in this embodiment is also very different from the traditional lookup table. The traditional lookup table includes a decoding circuit, a comparison circuit, a storage module (memory array) and an operation circuit. The decoding circuit decodes the detection signal to obtain a decoding address and sends it to the comparison circuit. The comparison circuit goes to the storage module according to the decoding address to find the corresponding weight information and sends it to the operation circuit. The operation circuit then calculates the detection signal based on the weight information to obtain a control signal to control the driving circuit. The traditional lookup table has the following defects: 1) The various components of the traditional lookup table, such as the decoding circuit, the comparison circuit, the storage module and the operation circuit, have independent functions. The storage module is mainly responsible for storing weight information, while the operation operation is performed by a dedicated operation circuit. This structure requires data to be transferred between different circuit modules and cannot be calculated directly within the storage unit. For example, the comparison circuit needs to read the weight information from the storage module and then send it to the operation circuit for calculation. There is an obvious data transfer process in the middle; 2) Since the storage module and the operation circuit are separated, the transmission of data between them will become a bottleneck. Each time a calculation is performed, the weight information in the storage module needs to be read out and transferred to the operation circuit, and the result is output after the calculation is completed. This process is not only time-consuming but also increases energy consumption, limiting the overall performance of the system. 3) Traditional memory array designs primarily focus on data storage, with the storage cells themselves lacking computational capabilities. They simply store weight information and are unable to perform computational operations simultaneously with storage.

[0103] Compared to traditional lookup tables, which require decoding and comparison circuits to determine the location of weight information, this embodiment, in contrast, includes a signal input port for each target memory array equal to the number of detection signals. This allows detection signals to be directly fed into the corresponding wordline and row of bits, eliminating the decoding and comparison processes and simplifying the circuit structure. This not only reduces hardware costs but also reduces circuit complexity and improves system reliability. This embodiment uses charge sharing to perform cumulative calculations, which can be performed directly within the memory cell, achieving integrated storage and computation. Compared to traditional lookup tables, which require data to be transferred and calculated between different modules, charge sharing reduces data transfer time and energy consumption, significantly improving computational efficiency. For example, when processing a large number of detection signals, this embodiment can more quickly obtain the target control signal. Because this embodiment directly feeds the detection signal into the wordline and performs calculations, it eliminates intermediate steps and can respond more quickly to changes in the detection signal, outputting the target control signal in real time. Traditional lookup tables, on the other hand, require multiple steps such as decoding and comparison, resulting in relatively long response times and poor real-time performance.

[0104] For example, both PMOS and NMOS transistor performance detection circuits can employ a critical path replica architecture that detects clock phase differences. In integrated circuits, the critical path refers to the longest path a signal takes from input to output and determines the circuit's maximum operating frequency. A critical path replica architecture replicates an identical critical path within the circuit and uses this replica to detect changes in IC performance. Its operating principle is as follows: Within a certain timeframe, a rising edge counter counts the number of pulse signals and clock signals passing through the critical path replica. The clock signal is a stable reference signal, while the propagation speed of the pulse signal through the critical path replica is affected by IC performance variations (such as process fluctuations, voltage, and temperature variations). If IC performance degrades, the pulse signal propagates more slowly, resulting in fewer pulses passing through the critical path replica in the same amount of time. A digital subtractor calculates the difference between these two counts to generate a signal reflecting IC performance deviations. Assuming the clock signal frequency is fixed, under normal circumstances, the pulse signal passes through the critical path replica 90 times per 100 clock cycles. When the performance of an integrated circuit degrades due to temperature rise, the number of times a pulse signal passes through the critical path replica may drop to 80 within the same 100 clock cycles. This will cause the difference obtained by the digital subtractor to change, and this difference will reflect the deviation in the performance of the integrated circuit.

[0105] See also Figure 6 , the PMOS transistor performance detection circuit 110 includes a PMOS delay line 111, a first rising edge counter 112 and a first digital subtractor 113; see Figure 7 The NMOS transistor performance detection circuit 120 includes an NMOS delay line 121 , a second rising edge counter 122 and a second digital subtractor 123 .

[0106] Among them, the NMOS delay line and the PMOS delay line are respectively used to delay the corresponding clock signal to form a pulse signal based on the critical path replica; the first rising edge counter and the second rising edge counter respectively count the pulse signals (CLK-PH and CLK-N) after passing through the PMOS delay line and the NMOS delay line and the original clock signal (CLK-P0 and CLK-N0) within a certain period of time; and the first digital subtractor and the second digital subtractor calculate the difference between the pulse signal count value passing through the critical path replica and the clock signal count value. This difference is the detection signal (PMOS detection signal and NMOS detection signal). This difference reflects the phase difference between the pulse signal passing through the critical path replica and the original clock signal. By analyzing this difference, the performance (such as delay characteristics, etc.) of the transistor (NMOS transistor and PMOS transistor) in the critical path can be detected, thereby realizing the detection of transistor performance.

[0107] For example, the PMOS transistor performance detection circuit and the NMOS transistor performance detection circuit can both adopt a circuit architecture based on a critical path copy by detecting a clock phase difference value, and the first target memory array and the second target memory array in the memory array both adopt a memory array based on an SRAM architecture.

[0108] For example, both the PMOS transistor performance detection circuit and the NMOS transistor performance detection circuit can adopt a circuit architecture based on leakage current detection, and calculate the difference of leakage current through a current mirror.

[0109] In an optional embodiment, the selection input multiplexing circuit and the selection output multiplexing circuit each include N PMOS signal selection circuits and N NMOS signal selection circuits.

[0110] A PMOS detection signal enters the first target memory array through a PMOS signal selection circuit and is then output to the drive circuit through a PMOS signal selection circuit;

[0111] An NMOS detection signal enters the second target memory array through an NMOS signal selection circuit, and is then output to the driving circuit through another NMOS signal selection circuit.

[0112] See also Figure 8The PMOS signal selection circuit and the NMOS signal selection circuit both include: a first NMOS transistor, a second NMOS transistor, and a third NMOS transistor; the gates of the first NMOS transistor, the gates of the second NMOS transistor, and the gates of the third NMOS transistor are all connected to corresponding clock signals; the drain of the first NMOS transistor is connected to a detection signal; the first NMOS transistor and the second NMOS transistor are connected in series; the source of the second NMOS transistor outputs the detection signal; the source of the first NMOS transistor and the drain of the second NMOS transistor are both connected to the drain of the third NMOS transistor.

[0113] When the i-th clock signal is 0, N3 is turned off, N1 and MN2 are turned on, and the output signal is selected as the i-th detection signal in the path. i is a positive integer greater than or equal to 0.

[0114] In an alternative embodiment, see Figure 9 The pump-up charge pump and the pump-down charge pump each include: a first current array, a second current array, a first inverter, a second inverter, a first capacitor, a second capacitor, and a CMOS cross-coupling pair; power supply terminals of the first current array and the second current array are both connected to a power supply VDD;

[0115] The signal input ends of the first current array and the second current array are both connected to the target control signal; the first current array is connected to the first inverter INV1; the signal output end of the first inverter INV1 is connected to the first end of the first capacitor C1; the input end of the first inverter INV1 is connected to the first clock signal CLKA; the second end of the first capacitor C1 is connected to the CMOS cross-coupling pair; the second current array is connected to the second inverter INV2; the signal output end of the second inverter INV2 is connected to the first end of the second capacitor C2; the input end of the second inverter INV2 is connected to the second clock signal CLKB; and the second end of the second capacitor C2 is connected to the CMOS cross-coupling pair.

[0116] For a CMOS cross-coupled pair of charge pumps on pumps, see Figure 9 , the CMOS cross-coupling pair includes a first PMOS transistor, a second PMOS transistor, a fourth NMOS transistor and a fifth NMOS transistor;

[0117] The gate of the first PMOS transistor and the gate of the fourth NMOS transistor are both connected to the second capacitor; the gate of the second PMOS transistor and the gate of the fifth NMOS transistor are both connected to the first capacitor;

[0118] The source of the first PMOS transistor and the source of the second PMOS transistor (as signal input terminals) are connected to the input signal In (the input signal In here is the output signal of the signal selection circuit); the source of the first PMOS transistor is connected to the source of the fourth NMOS transistor; the source of the second PMOS transistor is connected to the source of the fifth NMOS transistor; the drain of the fourth NMOS transistor and the drain of the fifth NMOS transistor serve as signal output terminals of the pump-up charge pump.

[0119] The CMOS cross-coupled pair in the under-pump charge pump can be referred to as the CMOS cross-coupled pair in the over-pump charge pump, except that the two NMOS transistors in the CMOS cross-coupled pair are connected to the signal input terminal, and the two PMOS transistors are connected to the signal output terminal. This will not be further described here.

[0120] Taking a pump-on charge pump as an example, the charge pump's operating principle is explained: 1) CLKA and CLKB are two non-overlapping clock signals, which are input to inverters INV1 and INV2, respectively. The inverters invert the input clock signals. In the charge pump circuit, the inverted clock signals output by the inverters are used to control the on and off states of the corresponding switches (P1, P2, N4, and N5). By controlling the states of the switches, they indirectly affect the current flow and the charging and discharging process of the capacitors, thereby affecting the amount of charge flowing into the capacitors to a certain extent. 2) When CLKA is low and CLKB is high: INV1 outputs a high level and INV2 outputs a low level, turning on P1, turning off N4, turning off P2, and turning on N5. The potential of the lower plate of C1 is set to the same level as the input signal. The second current array charges capacitor C2 through INV2. According to the principle of charge conservation, the potential of the lower plate of C2 suddenly changes to the difference between the input signal level and the low level output by INV2. The charge on the lower plate of capacitor C2 is transferred to the output through N5, completing the charge transfer or voltage boost operation. When CLKA is high and CLKB is low, INV1 outputs a low level and INV2 outputs a high level, turning off P1, turning on N4, turning on P2, and turning on N5. According to the principle of charge conservation, the potential of the lower plate of C1 suddenly changes to the difference between the input signal level and the low level output by INV1, and the lower plate of C2 is set to the same level as the input signal. 3) Under the control of the Ctrl signal, the first and second current arrays provide stable current sources. When the switch tube is turned on, it provides current to charge the capacitor, thereby realizing the function of the charge pump, such as increasing the output voltage.

[0121] In an alternative embodiment, see Figure 10 , the first current array and the second current array both include: a third PMOS transistor, a fourth PMOS transistor and a plurality of MOS transistor branches, each MOS transistor branch includes three PMOS transistors connected in series; see Figure 10 , multiple MOS tubes include P4, P5 to P13;

[0122] The third PMOS transistor and the fourth PMOS transistor are connected in series to provide a bias voltage for multiple MOS transistor branches; the gate of the third PMOS transistor is connected to all of the multiple MOS transistor branches; the gate of the fourth PMOS transistor is connected to the source of the fourth PMOS transistor; the gate of the first PMOS transistor in each MOS transistor branch is connected to the target control signal; the gate of the second PMOS transistor in each MOS transistor branch serves as a bias voltage terminal; and the gate of the third PMOS transistor in each MOS transistor branch serves as a switch terminal of the branch and is connected to the branch selection signal.

[0123] P3 and P4 are used to provide bias voltage for each MOS tube branch to achieve the purpose of fixing the corresponding MOS tube source-drain voltage. P6 and P7 are used to provide high output impedance. By changing the ctrl signal, the current flowing through the branch is changed. The current is inversely proportional to the size of the ctrl signal. The width-to-length ratio between P5, P8, and P11 is a multiple of 2, so the maximum current flowing through each branch is also a multiple of 2. Through SEL The signal (also known as the branch selection signal) selects the number of branches connected to the charge pump circuit, ultimately achieving a faster charge transfer speed by changing the amount of charge flowing into the pump capacitor during a clock cycle. i is a positive integer greater than or equal to 0.

[0124] Although the present invention has been described herein with reference to various embodiments, in the process of implementing the claimed invention, those skilled in the art may understand and implement other variations of the disclosed embodiments by examining the drawings, the disclosure, and the appended claims. In the claims, the word "comprising" does not exclude other components or steps, and "a" or "an" does not exclude multiple components. A single processor or other unit may implement several of the functions listed in the claims. The fact that certain measures are recited in different dependent claims does not mean that these measures cannot be combined to produce good results.

[0125] Although the present invention has been described with reference to specific features and embodiments thereof, it will be apparent that various modifications and combinations may be made thereto without departing from the spirit and scope of the invention. Accordingly, this specification and drawings are merely illustrative of the invention as defined by the appended claims and are deemed to cover any and all modifications, variations, combinations or equivalents within the scope of the invention. It will be apparent that various modifications and variations may be made to the present invention by those skilled in the art without departing from the spirit and scope of the invention. Thus, the present invention is intended to include such modifications and variations as fall within the scope of the claims of the present invention and their equivalents.

Claims

1. A back gate bias voltage generating circuit, characterized in that: At least: Transistor performance detection circuit, storage and calculation integrated circuit and driving circuit; The transistor performance detection circuit is used to detect integrated circuit performance offset information of N back-biased domains on a target integrated circuit; the transistor performance detection circuit includes N groups of performance detection sub-circuits, each group of performance detection sub-circuits is used to detect integrated circuit performance offset information of one back-biased domain; N is a positive integer greater than 1; The storage and calculation integrated circuit comprises at least a memory array; the storage and calculation integrated circuit is used to store and calculate the integrated circuit performance deviation information; The driving circuit is used to generate a target back gate bias voltage.

2. The back gate bias voltage generating circuit according to claim 1, wherein: Also includes: selecting an input multiplexing circuit and selecting an output multiplexing circuit; The output end of the transistor performance detection circuit is connected to the input end of the selection input multiplexing circuit, and the output end of the selection input multiplexing circuit is connected to the input end of the storage and calculation integrated circuit; the output end of the storage and calculation integrated circuit is connected to the input end of the selection output multiplexing circuit, and the output end of the selection output multiplexing circuit is connected to the input end of the driving circuit; The selection input multiplexing circuit is used to sequentially send the output signal of the transistor performance detection circuit to the storage and calculation integrated circuit; The selection output multiplexing circuit is used to send the output signals of the storage and calculation integrated circuit to the driving circuit in sequence.

3. The back gate bias voltage generating circuit according to claim 2, wherein: Each group of performance detection sub-circuits includes a PMOS transistor performance detection circuit and an NMOS transistor performance detection circuit; The memory array includes a first target memory array and a second target memory array; The first target memory array and the second target memory array each include a plurality of storage bits; Each storage bit in the first target memory array is pre-written with weight information corresponding to the PMOS transistor; Each storage bit in the second target memory array is pre-written with weight information corresponding to the NMOS transistor; The first target memory array includes N signal input ports; The second target memory array includes N signal input ports; The integrated storage and computing circuit also includes a first current-voltage conversion circuit and a second current-voltage conversion circuit; the first current-voltage conversion circuit is connected to the first target memory array; the second current-voltage conversion circuit is connected to the second target memory array.

4. The back gate bias voltage generating circuit according to claim 3, wherein: The driving circuit includes N driving modules, each of which includes an upper charge pump and a lower charge pump; Each pump-up charge pump is connected to a PMOS transistor in the back-biased domain; Each pump-down charge pump is connected to an NMOS transistor in the back-biased domain.

5. The back gate bias voltage generating circuit according to claim 4, wherein: The first target memory array and the second target memory array each include a word line for transmitting an input signal and a bit line for outputting a convolution operation result; When the integrated circuit performance deviation information from the PMOS transistor performance detection circuit is input to a row of bits in the first target memory array, each column of bit lines performs a convolution operation on the bit weight of the column and the input signal, and sends the convolution result in the form of current to the first current-voltage conversion circuit; the first current-voltage conversion circuit converts the corresponding convolution result into a corresponding target control signal to control the corresponding pump-up charge pump; When integrated circuit performance deviation information from the NMOS transistor performance detection circuit is input to a row of bits in the second target memory array, each column of bit lines performs a convolution operation on the bit weight of the column with the input signal, and sends the convolution result in the form of current to the second current-voltage conversion circuit. The second current-voltage conversion circuit converts the corresponding convolution result into a corresponding target control signal to control the corresponding pump-down charge pump.

6. The back gate bias voltage generating circuit according to claim 3, wherein: The PMOS transistor performance detection circuit includes a PMOS delay line, a first rising edge counter and a first digital subtractor; The NMOS transistor performance detection circuit includes an NMOS delay line, a second rising edge counter and a second digital subtractor; The memory array is a memory array based on an SRAM architecture.

7. The back gate bias voltage generating circuit according to claim 3, wherein: The selection input multiplexing circuit and the selection output multiplexing circuit each include N PMOS signal selection circuits and N NMOS signal selection circuits.

8. The back gate bias voltage generating circuit according to claim 7, wherein: The PMOS signal selection circuit and the NMOS signal selection circuit both include: a first NMOS transistor, a second NMOS transistor and a third NMOS transistor; The gates of the first NMOS transistor, the second NMOS transistor, and the third NMOS transistor are all connected to corresponding clock signals; The drain of the first NMOS transistor is connected to a detection signal; the first NMOS transistor and the second NMOS transistor are connected in series; the source of the second NMOS transistor outputs the detection signal; The source of the first NMOS transistor and the drain of the second NMOS transistor are both connected to the drain of the third NMOS transistor.

9. The back gate bias voltage generating circuit according to claim 4, wherein: The pump-up charge pump and the pump-down charge pump each include: a first current array, a second current array, a first inverter, a second inverter, a first capacitor, a second capacitor, and a CMOS cross-coupling pair; The power supply ends of the first current array and the second current array are both connected to a power supply; The signal input terminals of the first current array and the second current array are both connected to the target control signal; The first current array is connected to the first inverter; the signal output terminal of the first inverter is connected to the first terminal of the first capacitor; the input terminal of the first inverter is connected to the first clock signal; the second terminal of the first capacitor is connected to the CMOS cross-coupling pair; The second current array is connected to the second inverter; the signal output end of the second inverter is connected to the first end of the second capacitor; the input end of the second inverter is connected to the second clock signal; and the second end of the second capacitor is connected to the CMOS cross-coupling pair.

10. The back gate bias voltage generating circuit according to claim 9, wherein: The first current array and the second current array both include: a third PMOS transistor, a fourth PMOS transistor, and a plurality of MOS transistor branches, each MOS transistor branch including three PMOS transistors connected in series; The third PMOS transistor and the fourth PMOS transistor are connected in series to provide a bias voltage for the multiple MOS transistor branches; The gate of the third PMOS transistor is connected to the multiple MOS transistor branches; The gate of the fourth PMOS transistor is connected to the source of the fourth PMOS transistor; The gate of the first PMOS transistor in each MOS transistor branch is connected to the target control signal; The gate of the second PMOS tube in each MOS tube branch serves as the bias voltage terminal; The gate of the third PMOS transistor in each MOS transistor branch serves as a switch end of the branch and is connected to the branch selection signal.

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