A current adaptive control fast response low dropout linear regulator

Abstract

This invention provides a fast-response low-dropout linear regulator with current adaptive control, comprising: a first-stage circuit, a second-stage circuit, and an output stage circuit connected in sequence. The first-stage circuit compares a reference voltage VREF1 with a feedback voltage and amplifies the resulting error signal to provide control signals for the subsequent second-stage and output stage circuits. The second-stage circuit adjusts the output current according to load changes through a current adaptive control circuit to shorten the loop response time and reduce output voltage fluctuations during load switching. The output stage circuit outputs a stable voltage and provides the required current to the load, enabling direct drive of the load. This invention, through a three-stage linkage of "precise error amplification → adaptive current adjustment → fast power transistor response," reduces voltage fluctuation amplitude and shortens recovery time at load transition edges, achieving a high-speed transient response level.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit design, and in particular relates to a fast-response low-dropout linear regulator with current adaptive control. Background Technology

[0002] With the rapid development of technology, portable electronic devices are becoming increasingly important in daily life and work, driving the diversification of power solutions. Low dropout linear regulators (LDOs), as a common step-down chip, are widely used in small electronic devices, especially in System-on-Chips (SoCs), where LDOs are favored for their excellent noise performance and ease of integration.

[0003] A typical LDO structure is as follows Figure 1 As shown, the circuit consists of a first stage, a second stage, and an output stage. IB1, IB2, and IB3 are current sources, and VREF and VB are reference voltages. MP is a power transistor used to provide current to the output (load). When the load current changes, the entire LDO loop controls the output current of the power transistor by adjusting the gate (A) voltage of MP.

[0004] When the output transitions from a heavy load (larger output current) to a light load (smaller output current), the loop response consisting of M11-M15-M21-M22-M23-MP requires a certain amount of time, causing the output voltage VOUT to overshoot. Specifically, as follows... Figure 2 As shown.

[0005] The magnitude of the output voltage overshoot is related to the loop response time. The loop response time is related to the parasitic capacitance at point A and the charging / discharging current at point A. To reduce the output VOUT overshoot voltage, the current value of IB3 needs to be increased, which will increase the overall quiescent power dissipation of the LDO and reduce the power conversion efficiency. Summary of the Invention

[0006] To address the problems existing in the background technology, the present invention provides a fast-response low-dropout linear regulator with current adaptive control, comprising: a first-stage circuit, a second-stage circuit, and an output stage circuit connected in sequence; the first-stage circuit is used to compare a reference voltage VREF1 with a feedback voltage and amplify the generated error signal to provide control signals for the subsequent second-stage and output stage circuits; the second-stage circuit is used to adjust the output current according to load changes through a current adaptive control circuit to shorten the loop response time and reduce output voltage fluctuations during load switching; the output stage circuit is used to output a stable voltage and provide the required current to the load, realizing direct drive of the load.

[0007] The present invention has at least the following beneficial effects

[0008] This invention, through a three-stage linkage of "precise error amplification → adaptive current adjustment → fast power transistor response," reduces voltage fluctuation amplitude and shortens recovery time under load transition edges, achieving a rapid transient response level. Attached Figure Description

[0009] Figure 1 This is a schematic diagram of the circuit structure of a traditional LDO;

[0010] Figure 2 This is a schematic diagram of a traditional LDO experiencing overshoot.

[0011] Figure 3 This is a schematic diagram of the circuit structure of the present invention;

[0012] Figure 4 This is a simulation diagram of the present invention. Detailed Implementation

[0013] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that the illustrations provided in the following embodiments are only schematic representations of the basic concept of the present invention. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0014] Please see Figure 3 This invention provides a fast-response low-dropout linear regulator with current adaptive control, comprising a first-stage circuit, a second-stage circuit, and an output stage circuit connected in sequence. The first-stage circuit compares a reference voltage VREF1 with a feedback voltage and amplifies the resulting error signal to provide control signals for the subsequent second-stage and output stage circuits. The second-stage circuit adjusts the output current according to load changes through a current adaptive control circuit to shorten the loop response time and reduce output voltage fluctuations during load switching. The output stage circuit outputs a stable voltage and provides the required current to the load, enabling direct drive of the load.

[0015] Preferably, the first stage circuit includes: a current source IB2 and an N-channel MOS transistor M15; the positive terminal of the current source IB2 is connected to the VIN terminal; the negative terminal of the current source IB2, the control signal input terminal of the second stage circuit, and the drain of M15 are connected to the feedback voltage terminal; a capacitor Cm is connected between the feedback voltage terminal and the output voltage terminal VOUT; the gate of the M15 is connected to the reference voltage VREF1; and the source of the M15 is connected to the control signal input terminal of the output stage circuit.

[0016] Preferably, the second-stage circuit includes: a P-channel MOS transistor M21, a resistor R1, and N-channel MOS transistors M22, M23, M24, and M25; the gate of M21 is connected to the control signal input terminal of the second-stage circuit; the source of M21 is connected to the VIN terminal; the drains of M21, M22, M22, M23, and M24 are connected; the sources of M22, M23, and M24 are grounded to GND; the drain of M23, one end of resistor R1, and the gate of M25 are connected; the other end of resistor R1 and the drain of M25 are connected to the VIN terminal; the source of M25 and the drain of M24 are connected to the adjustment control terminal of the output stage circuit.

[0017] Preferably, the output stage circuit includes: a current source IB1, and P-channel MOS transistors MP and M11; the negative terminal of the current source IB1 is connected to GND; the positive terminal of the current source IB1 and the drain of M11 are connected to the control signal input terminal of the output stage circuit; the gate of M11 is connected to the reference voltage VREF2; the source of M11 and the drain of MP are connected to the output voltage terminal VOUT; the gate of MP is connected to the adjustment control terminal of the output stage circuit; and the source of MP is connected to the VIN terminal.

[0018] Preferably, when the output of the fast-response low-dropout linear regulator transitions from heavy load to light load, the gate charging current of the transistor MP satisfies the formula:

[0019]

[0020] Where, μ N For the migration velocity of N-type carriers, C OX V represents the gate oxide thickness of transistor M25. TH V is the threshold voltage of transistor M25; W and L are the channel width and length of transistor M25, respectively; A i is the gate voltage of transistor MP before switching; charge This represents the gate current of transistor MP;

[0021] By properly designing the dimensions of M25, a larger gate current i of transistor MP can be obtained. charge This improves the charging capability of the gate capacitor, reduces the loop response time, and decreases output voltage fluctuations during load switching.

[0022] Preferably, the static current I of resistor R1 in the static current adaptive control circuit is... Q for:

[0023]

[0024] Among them, V GS,MPV is the gate-source voltage of the power transistor MP; GS,25 The gate-source voltage of transistor M25 is given; the quiescent current is reduced by designing the value of resistor R1.

[0025] In this embodiment, a fast-response low-dropout linear regulator with adaptive current control is as follows: Figure 3 As shown, when the output transitions from heavy load (larger output current) to light load (smaller output current), the gate charging current i of MP... charge It can be calculated as:

[0026]

[0027] Where, μ N For the migration velocity of N-type carriers, C OX V represents the gate oxide thickness of transistor M25. TH V is the threshold voltage of transistor M25; W and L are the channel width and length of transistor M25, respectively; A i is the gate voltage (point A voltage) of transistor MP before switching; charge This represents the gate current of transistor MP (the charging current i at the gate of transistor MP). charge By properly designing the dimensions of M25, a larger gate current i of transistor MP can be obtained. charge This improves the charging capability of the gate capacitor, reduces the loop response time, and decreases output voltage fluctuations during load switching.

[0028] The static current I of resistor R1 in the static current adaptive control circuit Q for:

[0029]

[0030] Among them, V GS,MP V is the gate-source voltage of the power transistor MP; GS,25 This refers to the gate-source voltage of transistor M25; the quiescent current can be reduced by designing the value of resistor R1; the quiescent current can be reduced by designing the value of R1, since V GS,MP Since it is related to the output current, the quiescent current of the current adaptive control circuit can also adapt to changes in the load current.

[0031] In summary, the current adaptive control circuit achieves high transient charge and discharge capability while maintaining low quiescent current, reducing loop response time and minimizing output voltage fluctuations during load switching.

[0032] To verify the effectiveness of the present invention, Figure 3 The circuit shown was simulated and verified using a 0.18μm CMOS process. Figure 4The response of an LDO with and without current adaptive control circuitry under transient load changes is demonstrated. When the load current jumps from 1mA to 50mA in a 300ns edge time, the undershoot voltage of the LDO with current adaptive control circuitry drops from 158mV to 26.2mV, with a recovery time of less than 1μs. Conversely, when the load current jumps from 50mA to 1mA, the overshoot voltage of the LDO with current adaptive control circuitry drops from 223.8mV to 34.6mV, also with a recovery time of less than 1μs. In summary, the LDO of this invention achieves high transient charge and discharge capability while maintaining low quiescent current, reducing loop response time and minimizing output voltage fluctuations during load switching.

[0033] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit it. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the spirit and scope of the present invention, and all such modifications or substitutions should be covered within the scope of the claims of the present invention.

Claims

1. A fast-response low-dropout linear regulator with current adaptive control, characterized in that, The circuit includes a first-stage circuit, a second-stage circuit, and an output stage circuit connected in sequence. The first-stage circuit compares the reference voltage VREF1 with the feedback voltage and amplifies the resulting error signal to provide control signals for the subsequent second-stage and output stage circuits. The second-stage circuit adjusts the output current according to load changes through a current adaptive control circuit to shorten the loop response time and reduce output voltage fluctuations during load switching. The output stage circuit outputs a stable voltage and provides the required current to the load, enabling direct drive of the load. The second-stage circuit includes: a P-channel MOS transistor M21, a resistor R1, and N-channel MOS transistors M22, M23, M24, and M25; the gate of M21 is connected to the control signal input terminal of the second-stage circuit; the source of M21 is connected to the VIN terminal; the drains of M21, M22, M22, M23, and M24 are connected; the sources of M22, M23, and M24 are grounded to GND; the drain of M23, one end of resistor R1, and the gate of M25 are connected; the other end of resistor R1 and the drain of M25 are connected to the VIN terminal; the source of M25 and the drain of M24 are connected to the adjustment control terminal of the output stage circuit.

2. The fast-response low-dropout linear regulator with current adaptive control according to claim 1, characterized in that, The first stage circuit includes: a current source IB2 and an N-channel MOS transistor M15; the positive terminal of the current source IB2 is connected to the VIN terminal; the negative terminal of the current source IB2, the control signal input terminal of the second stage circuit, and the drain of M15 are connected to the feedback voltage terminal; a capacitor Cm is connected between the feedback voltage terminal and the output voltage terminal VOUT; the gate of the M15 is connected to the reference voltage VREF1; and the source of the M15 is connected to the control signal input terminal of the output stage circuit.

3. The fast-response low-dropout linear regulator with current adaptive control according to claim 1, characterized in that, The output stage circuit includes: a current source IB1, and P-channel MOS transistors MP and M11; the negative terminal of the current source IB1 is connected to GND; the positive terminal of the current source IB1 and the drain of M11 are connected to the control signal input terminal of the output stage circuit; the gate of M11 is connected to the reference voltage VREF2; the source of M11 and the drain of MP are connected to the output voltage terminal VOUT; the gate of MP is connected to the adjustment control terminal of the output stage circuit; and the source of MP is connected to the VIN terminal.

4. The fast-response low-dropout linear regulator with current adaptive control according to claim 3, characterized in that, When the output of the fast-response low-dropout linear regulator transitions from heavy load to light load, the gate charging current of transistor MP is: in, For the migration velocity of N-type carriers, C OX V represents the gate oxide thickness of transistor M25. TH The threshold voltage of transistor M25; W and L are the channel width and length of transistor M25, respectively; i charge V represents the gate charging current of transistor MP; A The gate voltage of transistor MP before switching; By properly designing the dimensions of M25, a larger gate charging current i can be obtained. charge This improves the charging capability of the gate capacitor, reduces the loop response time, and decreases output voltage fluctuations during load switching.

5. A fast-response low-dropout linear regulator with current adaptive control according to claim 3, characterized in that, The static current I of resistor R1 in the static current adaptive control circuit Q for: in, This is the gate-source voltage of the power transistor MP; The gate-source voltage of transistor M25 is given; the quiescent current is reduced by designing the value of resistor R1.

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