Ultra-low step time symmetric current generation circuit

Abstract

The invention discloses an extremely low step time symmetric current generation circuit, and relates to the technical field of any power management unit test, and the circuit mainly comprises a power supply unit, a pulse generator, a time constant adjustment network, an MOSFET switch, and a load adjustment resistor. The power supply unit, the pulse generator, the time constant adjusting network, the MOSFET switch and the load adjusting resistor are electrically connected in sequence. By implementing the extremely low step time symmetric current generation circuit provided by the invention, the current step time as low as 10ns can be realized, and the transient and stability test of any power supply management unit is supported.

Description

Technical Field

[0001] The present invention relates to the technical field of testing arbitrary power management units, and more particularly to an extremely low step time symmetrical current generating circuit. Background Art

[0002] In power management unit testing, load transient testing is an important means to evaluate the transient and loop stability of the power management unit under test. Load transient includes the maximum allowable output voltage change and recovery time when the load current changes stepwise. The rapidly changing pulse load current poses a challenge to the power management unit. Faced with this current load, the system requires sufficient bandwidth to maintain output voltage stability.

[0003] Current load transient testing solutions primarily include manual testing, electronic load meters, and commercial load transient test tools. Manual testing involves manually connecting and disconnecting a load resistor at the output of a power management unit (PMU) and using a storage oscilloscope with a sweep function to capture changes in the PMU's output voltage. However, this method cannot adjust the load current step time; the di / dt rate of the current step is primarily determined by parasitic parameters such as the lead inductance in series with the load resistor. Electronic load meters can directly generate step load currents, but due to the long leads between the electronic load meter and the actual circuit, the parasitic inductance of these long leads also limits the generated current step change rate (di / dt). Commercial load transient test tools generally offer advantages in accuracy and conversion rate, but they are subject to maximum current and conversion rate limitations depending on the PMU being tested, resulting in limited versatility and flexibility.

[0004] The above content is only used to assist in understanding the technical solution of the present invention and does not constitute an admission that the above content is prior art. Summary of the Invention

[0005] The purpose of the present invention is to provide a symmetrical current generating circuit with extremely low step time, which can achieve current step time as low as 10ns and support transient and stability testing of any power management unit.

[0006] The present invention provides an extremely low step time symmetrical current generating circuit, comprising a power supply unit, a pulse generator, a time constant adjustment network, a MOSFET switch and a load adjustment resistor; the power supply unit is used to supply power to the pulse generator, and the pulse generator is used to generate a pulse width modulation signal to control the periodic on and off of the MOSFET switch; the time constant adjustment network is used to adjust the switching speed of the MOSFET switch; during the on-state of the MOSFET switch, the load adjustment resistor draws a maximum load current from a power management unit, and during the off-state of the MOSFET switch, the load adjustment resistor maintains a minimum load current from the power management unit; the power supply unit, the pulse generator, the time constant adjustment network, the MOSFET switch and the load adjustment resistor are electrically connected in sequence.

[0007] Furthermore, the power supply unit includes a battery, a switch, a first resistor, a first capacitor, and a second capacitor, one end of the switch is connected to the positive electrode of the battery, the other end of the switch is connected to one end of the first resistor, the other end of the first resistor is connected to one end of the first capacitor and one end of the second capacitor, and the other end of the first capacitor, the other end of the second capacitor, and the negative electrode of the battery are grounded.

[0008] Furthermore, the first capacitor is an electrolytic capacitor, the second capacitor is a ceramic capacitor, and the first resistor is used to limit the input current.

[0009] Furthermore, the above-mentioned pulse generator includes a voltage-controlled oscillator, a first frequency-modulating resistor and a second frequency-modulating resistor, a first duty cycle adjustment resistor and a second duty cycle adjustment resistor, and the voltage-controlled oscillator includes a PWM signal output terminal, a power supply input terminal, a frequency division control input terminal, a ground terminal, a frequency setting input terminal, and an analog voltage control input terminal; the power supply input terminal is connected to one end of the first frequency-modulating resistor, and the other end of the first frequency-modulating resistor is connected to the frequency division control input terminal and one end of the second frequency-modulating resistor; the frequency setting input terminal is connected to one end of the first duty cycle adjustment resistor, and the other end of the first duty cycle adjustment resistor is connected to the analog voltage control input terminal and one end of the second duty cycle adjustment resistor; the ground terminal, the other end of the second frequency-modulating resistor, and the other end of the second duty cycle adjustment resistor are grounded.

[0010] Furthermore, the voltage-controlled oscillator is an LTC6992 chip.

[0011] Furthermore, the above-mentioned time constant adjustment network includes a first Schottky diode D1 and a second Schottky diode, a first time constant adjustment resistor, a second time constant adjustment resistor and a third capacitor; the anode of the first Schottky diode and the cathode of the second Schottky diode are connected, serving as the input end of the time constant adjustment network; the cathode of the first Schottky diode is connected to one end of the first time constant adjustment resistor, the cathode of the second Schottky diode is connected to one end of the second time constant adjustment resistor, one end of the third capacitor is connected to the other end of the first time constant adjustment resistor and the other end of the second time constant adjustment resistor, serving as the output end of the time constant adjustment network; the other end of the third capacitor is grounded.

[0012] Furthermore, the gate of the MOSFET switch is connected to the output end of the time constant adjustment network, the drain of the MOSFET switch is connected to the load adjustment resistor, and the source of the MOSFET switch is grounded.

[0013] Furthermore, the above-mentioned load adjustment resistor includes a dynamic resistor and a static resistor, one end of the dynamic resistor is connected to the drain of the MOSFET switch; the other end of the dynamic resistor is connected to one end of the static resistor, for connecting to the output end of the power management unit; the other end of the static resistor is connected to the source of the MOSFET switch.

[0014] The present invention also provides a load current control method applied to the above-mentioned extremely low step time symmetrical current generating circuit, comprising: utilizing the extremely low step time symmetrical current generating circuit to adjust the load current and step time of the power management unit.

[0015] The implementation of the extremely low step time symmetrical current generating circuit and load current control method provided by the present invention has the following beneficial effects: To address the shortcomings of existing load transient testing solutions, the present invention provides an extremely low-step-time symmetrical current generation circuit for measuring the transient response of a power management unit (PMU) under extreme conditions. The extremely low-step-time symmetrical current generation circuit includes a power supply unit, a pulse generator, a time constant adjustment network, a MOSFET switch, and a load adjustment resistor. The power supply unit supplies power to the pulse generator, which generates a pulse-width modulated signal that periodically controls the on and off state of the MOSFET switch. The time constant adjustment network is used to adjust the switching speed of the MOSFET switch. During the MOSFET on-time, the load adjustment resistor draws the maximum load current from the PMU. During the MOSFET off-time, the load adjustment resistor maintains a minimum load current of 1 mA from the PMU.

[0016] The present invention can achieve load current and step time control in a wide range by adjusting the resistance and capacitance in the circuit, and can provide symmetrical step load current for any power management unit. The load current step time can be adjusted in a wide range by adjusting the resistance and capacitance in the time constant adjustment network, with the minimum step time as low as 10ns. The load adjustment resistor supports a wide range of load current, has good scalability, can support transient and stability testing of any power management unit, and has a simple structure and low cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The present invention will be further described below with reference to the accompanying drawings and embodiments, in which: Figure 1 This is a structural block diagram of a very low step time symmetrical current generating circuit provided by the present invention; Figure 2 This is a schematic diagram of a very low step time symmetrical current generating circuit provided by the present invention; Figure 3 This is a schematic diagram of the MOSFET conduction process provided by the present invention; Figure 4 This is the equivalent circuit and small signal model diagram of the extremely low step time symmetrical current generating circuit provided by the present invention; Figure 5 This is a simulation diagram of a very low step time symmetrical current generating circuit provided by the present invention; Figure 6 This is a simulation diagram of the rise time and fall time of the drain-source voltage VDS of the MOSFET regulated by the time constant adjustment network provided by the present invention; Figure 7 This is a 10ns step time simulation diagram of the circuit provided by the present invention. DETAILED DESCRIPTION

[0018] In order to have a clearer understanding of the technical features, purposes and effects of the present invention, specific embodiments of the present invention are now described in detail with reference to the accompanying drawings.

[0019] Figure 1A schematic diagram of an extremely low-step time-symmetric current generation circuit according to this embodiment is shown. In this embodiment, the extremely low-step time-symmetric current generation circuit includes a power supply unit, a pulse generator, a time constant adjustment network, a MOSFET switch, and a load adjustment resistor. The power supply unit is used to power the pulse generator, which is used to generate a pulse-width modulation signal to control the periodic on and off of the MOSFET switch. The time constant adjustment network is used to adjust the switching speed of the MOSFET switch. During the on-time period of the MOSFET switch, the load adjustment resistor draws the maximum load current from the power management unit, and during the off-time period of the MOSFET switch, the load adjustment resistor maintains the minimum load current from the power management unit. The power supply unit, pulse generator, time constant adjustment network, MOSFET switch, and load adjustment resistor are electrically connected in sequence.

[0020] In an exemplary embodiment, the power supply unit includes a battery, a switch, a first resistor R1, a first capacitor C1, and a second capacitor C2, one end of the switch is connected to the positive electrode of the battery, the other end of the switch is connected to one end of the first resistor R1, the other end of the first resistor R1 is connected to one end of the first capacitor C1 and one end of the second capacitor C2, and the other end of the first capacitor C1, the other end of the second capacitor C2, and the negative electrode of the battery are grounded.

[0021] In an exemplary embodiment, the first capacitor C1 is an electrolytic capacitor, the second capacitor C2 is a ceramic capacitor; and the first resistor R1 is used to limit input current.

[0022] In an exemplary embodiment, the pulse generator includes a voltage-controlled oscillator, a first frequency-modulating resistor R2, a second frequency-modulating resistor R3, a first duty cycle adjustment resistor R8, and a second duty cycle adjustment resistor R9. The voltage-controlled oscillator includes a PWM signal output terminal, a power input terminal, a frequency division control input terminal, a ground terminal, a frequency setting input terminal, and an analog voltage control input terminal; the power input terminal is connected to one end of the first frequency-modulating resistor R2, and the other end of the first frequency-modulating resistor R2 is connected to the frequency division control input terminal and one end of the second frequency-modulating resistor R3; the frequency setting input terminal is connected to one end of the first duty cycle adjustment resistor R8, and the other end of the first duty cycle adjustment resistor R8 is connected to the analog voltage control input terminal and one end of the second duty cycle adjustment resistor R9; the ground terminal, the other end of the second frequency-modulating resistor R3, and the other end of the second duty cycle adjustment resistor R9 are grounded.

[0023] In an exemplary embodiment, the voltage controlled oscillator is an LTC6992 chip.

[0024] In an exemplary embodiment, the time constant adjustment network includes a first Schottky diode D1 and a second Schottky diode D2, a first time constant adjustment resistor R4, a second time constant adjustment resistor R5 and a third capacitor C3; the anode of the first Schottky diode D1 and the cathode of the second Schottky diode D2 are connected, serving as an input end of the time constant adjustment network; the cathode of the first Schottky diode D1 is connected to one end of the first time constant adjustment resistor R4, the cathode of the second Schottky diode D2 is connected to one end of the second time constant adjustment resistor R5, one end of the third capacitor C3 is connected to the other end of the first time constant adjustment resistor R4 and the other end of the second time constant adjustment resistor R5, serving as an output end of the time constant adjustment network; the other end of the third capacitor C3 is grounded.

[0025] In an exemplary embodiment, the gate of the MOSFET switch is connected to the output end of the time constant adjustment network, the drain of the MOSFET switch is connected to the load adjustment resistor, and the source of the MOSFET switch is grounded.

[0026] In an exemplary embodiment, the load adjustment resistor includes a dynamic resistor R6 and a static resistor R7, one end of the dynamic resistor R6 is connected to the drain of the MOSFET switch; the other end of the dynamic resistor R6 is connected to one end of the static resistor R7, for connecting to the output end of the power management unit; the other end of the static resistor R7 is connected to the source of the MOSFET switch.

[0027] This embodiment provides a load current control method applied to the extremely low step time symmetrical current generating circuit, comprising: utilizing the extremely low step time symmetrical current generating circuit to adjust the load current and step time of a power management unit.

[0028] In some embodiments, the extremely low step time symmetrical current generating circuit described above may also be implemented in the following manner.

[0029] In this embodiment, the ultra-low step-time symmetrical current generation circuit includes a power supply unit, a pulse generator, a time constant adjustment network, a MOSFET switch, and a load adjustment resistor. The power supply unit supplies power to the pulse generator, which generates a pulse-width modulated signal V1 to periodically turn the MOSFET switch on and off. The time constant adjustment network is used to adjust the switching speed of the MOSFET switch. During the MOSFET on-time, the load adjustment resistor draws the maximum load current from the power management unit. During the MOSFET off-time, the load adjustment resistor maintains a minimum load current of 1 mA from the power management unit.

[0030] Specifically, the power supply unit includes a battery, a switch, a current-limiting resistor R1, an electrolytic capacitor C1 and a ceramic capacitor C2. One end of the switch is connected to the positive pole of the battery, and the other end is connected to the current-limiting resistor R1 to limit the input current. R1 is connected in series with the electrolytic capacitor C1 and the ceramic capacitor C2 to provide a larger time constant when the circuit starts and the load changes in step, thereby suppressing transient changes in the current.

[0031] Specifically, the pulse generator includes an LTC6992 chip, frequency-modulating resistors R2 and R3, and duty-cycle adjustment resistors R8 and R9. The LTC6992 is a voltage-controlled oscillator with adjustable duty cycle and frequency, outputting a pulse-width modulated signal V1 with a maximum frequency of 1 MHz. R2 is connected in series between the LTC6992's V+ and DIV terminals, and R3 is connected in series between the DIV terminal and GND. The voltage divider R2 and R3 controls the internal frequency divider to divide the 1 MHz signal to generate the target frequency signal. R8 and R9 are connected in series to the SET terminal and GND, respectively. The MOD terminal is connected between R8 and R9, and the duty cycle of the output pulse signal is controlled by the voltage divider ratio.

[0032] Specifically, the pulse generator includes an LTC6992 chip, frequency-modulating resistors R2 and R3, and duty-cycle adjustment resistors R8 and R9. The LTC6992 is a voltage-controlled oscillator with adjustable duty cycle and frequency, outputting a pulse-width modulated signal V1 with a maximum frequency of 1 MHz. R2 is connected in series between the LTC6992's V+ terminal (power input) and DIV terminal (frequency division control input), and R3 is connected in series between DIV terminal and GND (ground). The voltage divider between R2 and R3 controls the internal frequency divider to divide the 1 MHz frequency, generating the target frequency signal. R8 and R9 are connected in series and connected to the SET terminal (frequency setting input) and GND, respectively. The MOD terminal (analog voltage control input) is connected between R8 and R9, and the duty cycle of the output pulse signal is controlled by the voltage divider ratio.

[0033] Specifically, the discrete MOSFET switch is manufactured based on a vertical process, and its gate-source parasitic capacitance C GS Much larger than the Miller capacitance C GD , which makes the MOSFET have a stronger gate drive capability when it is turned on than when it is turned off, resulting in the MOSFET's on time being shorter than its off time. And due to the Miller effect, the gate-source voltage V GS The Miller plateau appears, extending the MOSFET's turn-on and turn-off times. The two aforementioned factors lead to inconsistent MOSFET drain time constants. The time constant adjustment network, through D1, D2, R4, R5, and C3, forms an asymmetric charge and discharge path to compensate for the inconsistent MOSFET drain time constants, thereby achieving symmetrical step load currents.

[0034] Specifically, the load adjustment resistor includes a dynamic resistor R6 and a static resistor R7. The dynamic resistor R6 is connected in series between the drain of the MOSFET and the output of the power management unit. One end of the static resistor R7 is connected between R6 and the output of the power management unit, and the other end is connected to the source of the MOSFET. When the MOSFET is turned on, R6 draws the maximum load current from the power management unit. When the MOSFET is turned off, R7 maintains a minimum load current of 1mA from the power management unit.

[0035] In some embodiments, the extremely low step time symmetrical current generating circuit described above may also be implemented in the following manner.

[0036] like Figure 1 and Figure 2 As shown, in this embodiment, the extremely low step time symmetrical current generating circuit includes a power supply unit 1, a pulse generator 2, a time constant adjustment network 3, a MOSFET switch 4, and a load adjustment resistor 5; the power supply unit 1 supplies power to the pulse generator 2; the pulse generator 2 generates a pulse width modulation signal to control the periodic on and off of the MOSFET switch 4; the time constant adjustment network 3 adjusts the switching speed of the MOSFET switch 4 to achieve a symmetrical step of the load current; during the on-time of the MOSFET switch 4, the maximum load current is extracted from the power management unit through the load adjustment resistor 5, and during the off-time, the power management unit maintains a minimum load current of 1 mA through the load adjustment resistor 5.

[0037] Specifically, if Figure 2 As shown, the circuit of power supply unit 1 includes a battery, a switch, a current-limiting resistor R1, and capacitors C1 and C2. The battery powers the circuit and is connected to the circuit through the switch. The current-limiting resistor R1 and capacitors C1 and C2 provide a large time constant during circuit startup and load step changes, limiting transient current changes.

[0038] Specifically, in the pulse generator 2, the pulse signal is generated by LTC6992, the maximum frequency of LTC6992 can reach 1MHz, and the oscillation frequency f M The voltage V SET and current I SET To control, since the internal feedback loop of LTC6992 will V SET Maintained at 1V, so f M Mainly through I SET To control. And I SET By connecting a resistor R in series between the SET terminal and GND SET Get, f M It is given by formula (1).

[0039] (1) The LTC6992 contains a programmable frequency divider that can be used to divide f by 1, 4, 16, 64, 256, 1024, 16384. M After frequency division, the output is output, the frequency division ratio is N DIV According to the setting of the voltage divider resistors R2 and R3 at the DIV terminal, the frequency f of the output pulse width modulation signal is OUT As shown in formula (2).

[0040] (2) MOD is the output pulse width modulation duty cycle control port. By setting the MOD terminal voltage to 0.1V SET ~0.9V SET Given a duty cycle D of 0%~100%, it is given by formula (3).

[0041] (3) Specifically, if Figure 2 As shown, the circuit of the time constant adjustment network 3 includes: Schottky diodes D1 and D2, resistors R4 and R5, and capacitor C3; D1 and D2 are connected in reverse, with the OUT terminal of the LTC6992 connected to the cathode of D1 and the anode of D2, respectively. The anode of D1 is connected to R4, and the cathode of D2 is connected to R5. R4, R5, and C3 are connected in series. D1 and R4 form a low-impedance discharge path, while D2 and R5 form the MOSFET gate drive path. D1, D2, R4, and R5 together form an asymmetric charge and discharge path to regulate the switching speed of MOSFET switch 4, achieving symmetrical step-time load current.

[0042] Specifically, if Figure 3 As shown in (a), the parasitic capacitance of MOSFET switch 4 includes C GS 、C GD and C DS The conduction process of MOSFET switch 4 can be divided into four stages, t0~t1 stage, t1~t2 stage, t2~t3 stage and t3~t4 stage, as shown in Figure 3 As shown in (b). During the t0~t1 period, V GS Start applying voltage V IN , and give the input parasitic capacitance C GD and C GS Charging, thus generating an input current I G As shown in formula (4), where C GD < <C GS , at this time V GS Less than the threshold voltage V TH , so Q1 is in the cutoff region.

[0043] (4) During the t1~t2 phase, V GS >V TH MOSFET switch 4 starts to conduct, because V DS >V GS -V TH , so the MOSFET switch 4 is in the saturation region, and a current I is generated between the drain and the source D , I D As shown in formula (5), where μ n is the electron mobility, C OX is the gate oxide capacitance per unit area, and (W / L) is the width-to-length ratio of the MOSFET switch 4. Since the MOSFET switch 4 is in the saturation region, the Miller capacitance C GD Under the effect of inverting amplification, C GD The equivalent capacitance C eq =(1+A V )C GD is amplified, which is called the "Miller effect". G As shown in formula (7), where A V is the intrinsic gain of MOSFET switch 4 when it is in the saturation region. m and A V As shown in formula (8) and formula (9), as I D Increase, the transconductance g of MOSFET switch 4 m and A V Also began to grow, but at this stage C eq Still smaller than C GS , so I G Continue to give C GS Charging, V GS Continue to grow.

[0044] (5) (6) (7) (8) (9) t2~t3 stage, I D Reaching the maximum value, C eq >>C GS , so that I G Priority given to C eq Charging, V GS It is almost unchanged and presents a flat area, which is called the "Miller Platform". G Given by formula (10), I G By C eqExtracting drain charge forces V DS Rapidly lower.

[0045] (10) During the t3~t4 phase, V DS Start to drop, V DS <V GS -V TH MOSFET switch 4 is in the linear region, the Miller platform ends, and I G Continue to give C GS Charge until V GS =V IN , MOSFET switch 4 enters the fully on state.

[0046] The turn-off process of MOSFET switch 4 is opposite to the turn-on process. The Miller platform effect will prolong the switching time of MOSFET switch 4 and generate additional switching loss. Under the condition of ignoring the influence of switching loss, the time constant adjustment network is used to provide charging and discharging paths for the input capacitance of MOSFET switch 4 respectively. The time constants of the turn-on stage and the turn-off stage of MOSFET switch 4 are compensated by using the difference in values of R4 and R5, thereby achieving I D The rise time and fall time are symmetrical.

[0047] Specifically, the load regulating resistor 5 includes a dynamic resistor R6 and a static resistor R7. When the MOSFET switch 4 is on, the maximum load current is drawn from the power management unit through R6. When the MOSFET switch 4 is off, the power management unit maintains a minimum load current of 1 mA through R7.

[0048] Specifically, if Figure 4 As shown in (a), when the MOSFET switch 4 is turned on, D2 in the time constant adjustment network 3 is turned on, R5 is connected to the gate of the MOSFET switch 4, and the drain of the MOSFET switch 4 is connected to the dynamic resistor R6 of the load adjustment resistor 5.

[0049] MOSFET switch 4 drain V DD Provided by the power management unit, C OUT is the output capacitance of the power management unit. After the MOSFET switch 4 is turned on, it directly enters the saturation region. At this time, R6 is the equivalent load resistance of the power management unit. The load current I L Given by Equation (11). Due to the channel modulation effect, once V DS Descend, I L It starts to change in reverse.

[0050] (11) right Figure 4 The sum of the branch currents at each node of the small signal model shown in (b) is shown in Equations (12) and (13).

[0051] (12) (13) From formula (13), we can get formula (14): (14) Substitute equation (14) into equation (12) and simplify to obtain: (15) Where ξ=C OUT (C3+C GS )+C OUT C GD +C GD (C3+C GS ), it can be seen from formula (15) that the circuit has a zero point ω z1 and two extreme points ω p1 、ω p2 ,ω z1 As shown in formula (16).

[0052] (16) Formula (15) can be simplified as: (17) Assume |ω p1 |<<|ω p2 |, from formula (17) we can get: (18) Since R5>>R6, ω p1 It can be approximated as: (19) Assumption C GS >>(1+g m R D )C GD +R D (C GD +C OUT ) / R S , then ω p2 It can be approximated as: (20) Therefore, the transfer function can be expressed as Equation (21).

[0053] (twenty one) Combining equations (11) and (21) we can get V1 and I L The conversion relationship is shown in formula (4.19).

[0054] (twenty two) Performing an inverse Laplace transform on the transfer function of Equation (21) can yield the unit step response of the system, as shown in Equation (23).

[0055] (twenty three) It can be seen from formula (23) that the transient process consists of two exponential terms, and the time constants are τ1=R5((1+g m R5)C GD +C3+C GS ) and τ2=R6(C OUT +C GD ), C OUT >>C GD , so τ2 can be simplified to R6C OUT Since τ1>>(C GD / g m ) and τ2>>(C GD / g m ), formula (23) can be simplified to formula (24).

[0056] (twenty four) From the conduction process of MOSFET switch 4, we know that τ1>>τ2, so V DS The transient process is determined by τ1.

[0057] In this embodiment, a current step time as low as 10ns can be achieved, and the parameters of the relevant circuit components are shown in Table 1; Table 1: Component parameters of the 10ns step-time symmetrical current generation circuit

[0058] The beneficial effects of the present invention can be further illustrated by the following simulation experiments: Experiment 1: Using simulation software LTspice to Figure 4 The simulation of the extremely low step time symmetrical current generation circuit shown in the figure, V IN It is a pulse width modulation signal with a frequency of 500HZ, a duty cycle of 50%, and an amplitude of 5V. DD is 2.5V, the parasitic capacitance of the MOSFET switch C GS 、C GD and C DS They are 71.3pF, 7.6pF and 11.9pF respectively.

[0059] like Figure 5 (a) and Figure 5 As shown in (b), the horizontal axis represents time in ns, and the vertical axis on the left represents V DS , the unit is V, the vertical axis on the right represents the drain current I L , the unit is mA. Figure 5 (a) and Figure 5 In (b), we can see that V DS and I L Change curve, due to the channel modulation effect, once V DS Start to descend, I L It starts to change in reverse.

[0060] Experiment 2: Use the simulation software Matlab 2019 to draw the transfer function graph shown in formula (21) using the single variable method.

[0061] like Figure 6 As shown, the horizontal axis represents time in ns, and the vertical axis on the left represents the drain-source voltage V DS , the unit is V. Figure 6 As can be seen in (a), under the condition of C3 = 10pF, R5 is swept from 10Ω to 700Ω to achieve a V of 2ns to 110ns. DS Rise time; Figure 6 As can be seen in (b), under the condition of R5=50Ω, sweeping C3 from 10pF to 1nF achieves a V of 10ns to 120ns. DS Rise time.

[0062] Experiment 3: Use the simulation software LTSPICE to simulate the circuit for generating very low step time symmetrical current. The LTC6992 outputs a pulse width modulation signal with an amplitude of 5V, a frequency of 500Hz, and a duty cycle of 10%. Its rise time and fall time are both 1ns. The power management unit outputs 2.5V, and the load current I L From 1mA to 150mA steps.

[0063] The simulation waveform of the 10ns symmetrical step load current generation circuit is as follows Figure 7 As shown. Figure 7 As shown in (a), the horizontal axis represents time in ms, and the vertical axis on the left represents the gate voltage V of MOSFET switch 4 G , the unit is V. Figure 7 As shown in (c), the horizontal axis represents time in ms, and the vertical axis on the left represents the gate voltage V of MOSFET switch 4 G , the unit is V. Figure 7 (b) and Figure 7As shown in (d), the horizontal axis represents time in ns, and the vertical axis on the left represents V G , the unit is V, the vertical axis on the right represents I L , the unit is mA. Figure 7 It can be seen that after the time constant adjustment network is controlled, the gate voltage V G Rise time t G_r is 200ns, the fall time t G_f is 60ns, the load current I L During the 1mA to 150mA step, the rise time t L_r and fall time t L_f Both are 10ns.

[0064] The embodiments of the present invention are described above in conjunction with the accompanying drawings, but the present invention is not limited to the above-mentioned specific implementation methods. The above-mentioned specific implementation methods are merely illustrative and not restrictive. Under the guidance of the present invention, ordinary technicians in this field can also make many forms without departing from the scope of protection of the present invention and the claims, all of which are protected by the present invention.

Claims

1. A very low step time symmetrical current generating circuit, characterized in that: The invention comprises a power supply unit, a pulse generator, a time constant adjustment network, a MOSFET switch and a load adjustment resistor; the power supply unit is used to supply power to the pulse generator, the pulse generator is used to generate a pulse width modulation signal to control the periodic on and off of the MOSFET switch; the time constant adjustment network is used to adjust the switching speed of the MOSFET switch; when the MOSFET switch is on, the load adjustment resistor draws the maximum load current from the power management unit, and when the MOSFET switch is off, the load adjustment resistor maintains the minimum load current from the power management unit; the power supply unit, the pulse generator, the time constant adjustment network, the MOSFET switch and the load adjustment resistor are electrically connected in sequence.

2. The extremely low step time symmetrical current generating circuit according to claim 1, characterized in that: The power supply unit includes a battery, a switch, a first resistor, a first capacitor, and a second capacitor. One end of the switch is connected to the positive electrode of the battery, the other end of the switch is connected to one end of the first resistor, the other end of the first resistor is connected to one end of the first capacitor and one end of the second capacitor, and the other end of the first capacitor, the other end of the second capacitor, and the negative electrode of the battery are grounded.

3. The extremely low step time symmetrical current generating circuit according to claim 2, characterized in that: The first capacitor is an electrolytic capacitor, the second capacitor is a ceramic capacitor; and the first resistor is used to limit input current.

4. The extremely low step time symmetrical current generating circuit according to claim 1, characterized in that: The pulse generator includes a voltage-controlled oscillator, a first frequency-modulating resistor and a second frequency-modulating resistor, a first duty cycle adjustment resistor and a second duty cycle adjustment resistor. The voltage-controlled oscillator includes a PWM signal output terminal, a power input terminal, a frequency division control input terminal, a ground terminal, a frequency setting input terminal, and an analog voltage control input terminal; the power input terminal is connected to one end of the first frequency-modulating resistor, and the other end of the first frequency-modulating resistor is connected to the frequency division control input terminal and one end of the second frequency-modulating resistor; the frequency setting input terminal is connected to one end of the first duty cycle adjustment resistor, and the other end of the first duty cycle adjustment resistor is connected to the analog voltage control input terminal and one end of the second duty cycle adjustment resistor; the ground terminal, the other end of the second frequency-modulating resistor, and the other end of the second duty cycle adjustment resistor are grounded.

5. The extremely low step time symmetrical current generating circuit according to claim 4, characterized in that: The voltage controlled oscillator is an LTC6992 chip.

6. The extremely low step time symmetrical current generating circuit according to claim 1, characterized in that: The time constant adjustment network includes a first Schottky diode and a second Schottky diode, a first time constant adjustment resistor, a second time constant adjustment resistor and a third capacitor; the anode of the first Schottky diode and the cathode of the second Schottky diode are connected, serving as the input end of the time constant adjustment network; the cathode of the first Schottky diode is connected to one end of the first time constant adjustment resistor, the cathode of the second Schottky diode is connected to one end of the second time constant adjustment resistor, one end of the third capacitor is connected to the other end of the first time constant adjustment resistor and the other end of the second time constant adjustment resistor, serving as the output end of the time constant adjustment network; the other end of the third capacitor is grounded.

7. The extremely low step time symmetrical current generating circuit according to claim 1, characterized in that: The gate of the MOSFET switch is connected to the output end of the time constant adjustment network, the drain of the MOSFET switch is connected to the load adjustment resistor, and the source of the MOSFET switch is grounded.

8. The extremely low step time symmetrical current generating circuit according to claim 1, characterized in that: The load regulating resistor includes a dynamic resistor and a static resistor, one end of the dynamic resistor is connected to the drain of the MOSFET switch; the other end of the dynamic resistor is connected to one end of the static resistor and is used to be connected to the output end of the power management unit; the other end of the static resistor is connected to the source of the MOSFET switch.

9. A load current control method applied to the extremely low step time symmetrical current generating circuit according to any one of claims 1 to 8, characterized in that: include: The extremely low step time symmetrical current generating circuit is utilized to adjust the load current and step time of the power management unit.

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