Online deduplication of volatile memory

Abstract

The invention relates to online deduplication of volatile memory. Embodiments described herein relate to a system including a volatile memory and a controller. The controller may receive a command to write data to the volatile memory, wherein the command indicates a logical address associated with the data. The controller may compare the data to one or more duplicated data patterns to identify whether the data matches the duplicated data patterns. The controller may, in response to the data matching the duplicate data pattern, map a physical address associated with the duplicate data pattern to the logical address without writing the data to the volatile memory.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This patent application claims priority to U.S. Provisional Patent Application No. 63 / 552,752, filed on February 13, 2024, and entitled “ONLINE DEDUPLICATION FOR VOLATILE MEMORY.” The disclosure of that prior application is considered part of and incorporated by reference into this patent application. Technical Field

[0003] The present disclosure relates generally to memory devices, memory device operations, and, for example, to inline deduplication of volatile memory. Background Art

[0004] Memory devices are widely used to store information in various electronic devices. Memory devices include memory cells. A memory cell is an electronic circuit that can be programmed to a data state among two or more data states. For example, a memory cell can be programmed to a data state representing a single binary value, typically represented by a binary "1" or a binary "0." As another example, a memory cell can be programmed to a data state representing a fractional value (e.g., 0.5, 1.5, or the like). To store information, an electronic device can write to or program a group of memory cells. To access the stored information, the electronic device can read or sense the stored state from the group of memory cells.

[0005] There are various types of memory devices, including random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), static RAM (SRAM), synchronous dynamic RAM (SDRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), holographic RAM (HRAM), flash memory (e.g., NAND memory and NOR memory), and the like. Memory devices can be volatile or non-volatile. Non-volatile memory (e.g., flash memory) can store data for extended periods of time, even in the absence of an external power source. Volatile memory (e.g., DRAM) can lose stored data over time unless it is refreshed by a power source. In some examples, a memory device may be associated with Compute Express Link (CXL). For example, the memory device may be a CXL-compatible memory device and / or may include a CXL interface. Summary of the Invention

[0006] In one aspect, the present disclosure provides a system comprising: a volatile memory; and a controller configured to: receive a command to write data to the volatile memory, wherein the command indicates a logical address associated with the data; compare the data with one or more repeating data patterns to identify whether the data matches a repeating data pattern in the one or more repeating data patterns; and in response to the data matching the repeating data pattern, map a physical address associated with the repeating data pattern to the logical address without writing the data to the volatile memory.

[0007] On the other hand, the present disclosure further provides a method, comprising: receiving, by a controller of a memory system, a command to write data to a volatile memory of the memory system, wherein the command indicates a logical address associated with the data; retrieving, by the controller, a repeating data pattern using information in a local memory of the controller; comparing, by the controller, the data with the repeating data pattern to identify whether the data matches the repeating data pattern; and mapping, by the controller and in response to the data matching the repeating data pattern, a physical address associated with the repeating data pattern to the logical address without writing the data to the volatile memory.

[0008] In yet another aspect, the present disclosure further provides a system comprising a volatile memory; and a Compute Express Link (CXL) controller, comprising: a CXL interface; and a controller configured to: receive a command to write data to the volatile memory, wherein the command indicates a logical address associated with the data; compare the data with one or more repeating data patterns to identify whether the data matches a repeating data pattern in the one or more repeating data patterns; and in response to the data matching the repeating data pattern, map a physical address associated with the repeating data pattern to the logical address without writing the data to the volatile memory. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 is a diagram illustrating an example system.

[0010] Figure 2 is a diagram illustrating an example system.

[0011] Figure 3 This is a diagram illustrating the central controller and memory device of the system.

[0012] Figures 4A to 4C is a diagram of an example of online deduplication of volatile memory.

[0013] Figures 5A to 5Eis a diagram of an example of online deduplication of volatile memory.

[0014] Figures 6A to 6C is a diagram of an example of online deduplication of volatile memory.

[0015] Figures 7A to 7C is a graph of instances of block allocation.

[0016] Figure 8 is a flow chart of an example method associated with online deduplication of volatile memory. DETAILED DESCRIPTION

[0017] Memory blocks are typically replicated in the system's memory. For example, a block may be a duplicate when the corresponding data stored in the two blocks is identical (e.g., the two blocks may each store the same sequence of bit values). This may occur when a block is initialized but not used, when identical structures exist across multiple files of the same format loaded into memory, and / or when multiple identical files (e.g., the same library or kernel binary) are loaded into memory across different virtual machines hosted on the same system, among other instances.

[0018] Deduplication is a technique used to reduce the number of duplicate blocks in memory. Deduplication techniques can be categorized as online (also known as in-band) or offline (also known as out-of-band). In online deduplication, deduplication is performed while the data is being written to the memory. In offline deduplication, deduplication is performed by retrospectively analyzing the written data to identify duplicate blocks. Typically, deduplication techniques are implemented in software, with an emphasis on storage deduplication. However, due to the high performance requirements of volatile memories, these software-based deduplication techniques are not suitable for volatile memories. In volatile memories, the duplication of blocks consumes excessive memory resources and reduces memory capacity.

[0019] Some embodiments described herein implement online deduplication of volatile memory. In some embodiments, a memory controller (e.g., a CXL controller) may perform deduplication operations when executing a command to write data to volatile memory. The memory controller may implement one or more data structures for tracking data previously written to volatile memory. When a command is received to write new data to volatile memory, the new data may be compared with the data structure(s) to identify whether the new data is a duplicate of data previously written to volatile memory. If so, the logical address of the new data may be mapped to the physical address of the previously written data in volatile memory without writing the new data to the volatile memory. In this way, although the new data of the write command is not actually written to the volatile memory, a subsequent read command for the logical address will return the correct data (e.g., return the previously written data that is a duplicate of the new data requested to be written to the logical address).

[0020] Thus, the number of times duplicate data blocks can be written to volatile memory is reduced (e.g., only once). In some embodiments, data that may be associated with frequent replication can be written to and read from local memory (non-volatile memory) of the memory controller (e.g., only once). In this way, such frequently replicated data can be identified and read with improved speed and performance.

[0021] The online deduplication of volatile memory described herein saves significant memory resources and increases memory capacity. The increased memory capacity can be used for additional user data and / or for storing management data (e.g., to reduce the number of required memory dies). Furthermore, the online deduplication of volatile memory described herein significantly reduces the cost per byte of volatile memory and is implemented using few additional resources of the memory controller while incurring minimal performance impact on the memory controller.

[0022] Figure 1 1 is a diagram illustrating an example system 100. System 100 may include one or more devices, apparatuses, and / or components for performing the operations described herein. For example, system 100 may include a host system 105 and a memory system 110. Memory system 110 may include a memory system controller 115 and one or more memory devices 120 (shown as memory devices 120-1 through 120-N (where N ≥ 1)). A memory device may include a local controller 125 and one or more memory arrays 130. Host system 105 may communicate with memory system 110 (e.g., memory system controller 115 of memory system 110) via a host interface 140. Memory system controller 115 and memory devices 120 may communicate via respective memory interfaces 145 (shown as memory interfaces 145-1 through 145-N (where N ≥ 1)).

[0023] System 100 can be any electronic device configured to store data in memory. For example, system 100 can be a computer, a mobile phone, a wired or wireless communication device, a network device, a server, a device in a data center, a device in a cloud computing environment, a vehicle (e.g., a car or airplane), and / or an Internet of Things (IoT) device. Host system 105 can include host processor 150. Host processor 150 can include one or more processors configured to execute instructions and store data in memory system 110. For example, host processor 150 can include a central processing unit (CPU), a graphics processing unit (GPU), a field programmable gate array (FPGA), an application-specific integrated circuit (ASIC), and / or another type of processing component.

[0024] The memory system 110 may be any electronic device or apparatus configured to store data in memory. For example, the memory system 110 may be a hard disk drive, a solid-state drive (SSD), a flash memory system (e.g., a NAND flash memory system or a NOR flash memory system), a universal serial bus (USB) drive, a memory card (e.g., a secure digital (SD) card), an auxiliary storage device, a non-volatile memory express (NVMe) device, an embedded multimedia card (eMMC) device, a dual in-line memory module (DIMM), and / or a random access memory (RAM) device, such as a dynamic RAM (DRAM) device or a static RAM (SRAM) device.

[0025] The memory system controller 115 can be any device configured to control the operation of the memory system 110 and / or the operation of the memory devices 120. For example, the memory system controller 115 can include control logic, a memory controller, a system controller, an ASIC, an FPGA, a processor, a microcontroller, and / or one or more processing components. In some implementations, the memory system controller 115 can communicate with the host system 105 and can instruct one or more memory devices 120 regarding memory operations to be performed by the one or more memory devices 120 based on one or more instructions from the host system 105. For example, the memory system controller 115 can provide instructions to the local controllers 125 regarding memory operations to be performed by the local controllers 125 in conjunction with the corresponding memory devices 120.

[0026] The memory device 120 may include a local controller 125 and one or more memory arrays 130. In some implementations, the memory device 120 includes a single memory array 130. In some implementations, each memory device 120 of the memory system 110 may be implemented in a separate semiconductor package or on a separate die that includes a respective local controller 125 and respective memory array 130 for that memory device 120. The memory system 110 may include multiple memory devices 120.

[0027] The local controller 125 can be any device configured to control the memory operations of the memory device 120 in which the local controller 125 is contained (e.g., and not control the memory operations of other memory devices 120). For example, the local controller 125 can include control logic, a memory controller, a system controller, an ASIC, an FPGA, a processor, a microcontroller, and / or one or more processing components. In some implementations, the local controller 125 can communicate with the memory system controller 115 and can control operations performed on the memory array 130 coupled to the local controller 125 based on one or more instructions from the memory system controller 115. As an example, the memory system controller 115 can be an SSD controller, and the local controller 125 can be a NAND controller.

[0028] The memory array 130 may include an array of memory cells configured to store data. For example, the memory array 130 may include a non-volatile memory array (e.g., a NAND memory array or a NOR memory array) or a volatile memory array (e.g., an SRAM array or a DRAM array). In some embodiments, the memory system 110 may include one or more volatile memory arrays 135. The volatile memory array 135 may include an SRAM array and / or a DRAM array, among other examples. The one or more volatile memory arrays 135 may be included in the memory system controller 115, in one or more memory devices 120, and / or in both the memory system controller 115 and the one or more memory devices 120. In some embodiments, the memory system 110 may include both non-volatile memory that is capable of maintaining stored data after the memory system 110 is powered off, and volatile memory (e.g., the volatile memory array 135) that requires power to maintain stored data and loses stored data after the memory system 110 is powered off. For example, the volatile memory array 135 may cache data read from or to be written to non-volatile memory and / or may cache instructions to be executed by a controller of the memory system 110 .

[0029] The host interface 140 enables communication between the host system 105 (e.g., the host processor 150) and the memory system 110 (e.g., the memory system controller 115). The host interface 140 may include, for example, a small computer system interface (SCSI), a serial attached SCSI (SAS), a serial advanced technology attachment (SATA) interface, a peripheral component interconnect express (PCIe) interface, an NVMe interface, a USB interface, a universal flash storage (UFS) interface, an eMMC interface, a double data rate (DDR) interface, and / or a DIMM interface.

[0030] In some examples, memory device 120 may be a Compute Express Link (CXL)-compatible memory device 120. For example, memory device 120 may include a PCIe / CXL interface (e.g., host interface 140 may be associated with a PCIe / CXL interface). CXL is a high-speed CPU-to-device and CPU-to-memory interconnect designed to accelerate next-generation performance. CXL technology maintains memory coherency between the CPU memory space and the memory on the attached device, which allows resource sharing to achieve higher performance, reduced software stack complexity, and lower overall system cost. CXL is designed as an industry-standard open interface for high-speed communication. CXL technology is built on the PCIe infrastructure, leveraging the PCIe physical and electrical interfaces to provide advanced protocols in areas such as input / output (I / O) protocols, memory protocols, and coherent interfaces.

[0031] The memory interface 145 enables communication between the memory system 110 and the memory device 120. The memory interface 145 may include a non-volatile memory interface (e.g., for communicating with non-volatile memory), such as a NAND interface or a NOR interface. Additionally or alternatively, the memory interface 145 may include a volatile memory interface (e.g., for communicating with volatile memory), such as a DDR interface.

[0032] While the example memory system 110 described above includes a memory system controller 115, in some embodiments, the memory system 110 does not include a memory system controller 115. For example, an external controller (e.g., included in the host system 105) and / or one or more local controllers 125 included in one or more corresponding memory devices 120 may perform the operations described herein as being performed by the memory system controller 115. Furthermore, as used herein, "controller" may refer to the memory system controller 115, the local controller 125, or an external controller. In some embodiments, a set of operations described herein as being performed by a controller may be performed by a single controller. For example, the entire set of operations may be performed by a single memory system controller 115, a single local controller 125, or a single external controller. Alternatively, a set of operations described herein as being performed by a controller may be performed by more than one controller. For example, a first subset of the operations may be performed by the memory system controller 115 and a second subset of the operations may be performed by the local controller 125. Furthermore, depending on the context, the term "memory device" may refer to either the memory system 110 or the memory device 120.

[0033] A controller (e.g., memory system controller 115, local controller 125, or external controller) can control operations performed on a memory (e.g., memory array 130), for example, by executing one or more instructions. For example, memory system 110 and / or memory device 120 can store one or more instructions as firmware in memory, and the controller can execute those one or more instructions. Additionally or alternatively, the controller can receive one or more instructions from host system 105 and / or from memory system controller 115 and can execute those one or more instructions. In some embodiments, a non-transitory computer-readable medium (e.g., volatile memory and / or non-volatile memory) can store a set of instructions (e.g., one or more instructions or code) for execution by the controller. The controller can execute the set of instructions to perform one or more operations or methods described herein. In some embodiments, execution of the set of instructions by the controller causes the controller, memory system 110, and / or memory device 120 to perform one or more operations or methods described herein. In some embodiments, hardwired circuitry is used instead of or in combination with one or more instructions to perform one or more operations or methods described herein. Additionally or alternatively, a controller may be configured to perform one or more operations or methods described herein. Instructions are sometimes referred to as "commands."

[0034] For example, a controller (e.g., memory system controller 115, local controller 125, or external controller) may transmit signals to and / or receive signals from memory (e.g., one or more memory arrays 130) based on one or more instructions, such as to transfer data (e.g., write or program) to the memory, transfer data (e.g., read) from the memory, erase, and / or refresh all or a portion of the memory (e.g., one or more memory cells, pages, sub-blocks, blocks, or planes of the memory). Additionally or alternatively, the controller may be configured to control access to the memory and / or provide a translation layer between the host system 105 and the memory (e.g., for mapping logical addresses to physical addresses of the memory array 130). In some embodiments, the controller may translate host interface commands (e.g., commands received from the host system 105) into memory interface commands (e.g., commands for performing operations on the memory array 130).

[0035] Figure 1 The number and arrangement of components shown in FIG are provided as examples. In practice, compared to Figure 1 There may be additional components, fewer components, different components, or components arranged in a different manner than those shown in FIG. Figure 1 Two or more components shown in may be implemented in a single component, or Figure 1 The single component shown in may be implemented as multiple distributed components. Additionally or alternatively, Figure 1 A set of components (e.g., one or more components) shown in Figure 1 One or more operations performed by another set of components shown in .

[0036] Figure 2 is a diagram illustrating an example system 200. System 200 may include one or more devices, apparatuses, and / or components for performing the operations described herein. In some implementations, system 200 is a CXL system. For example, system 200 may include a host device 210 and a memory system 215, which includes a CXL controller 220 and one or more memory devices 230. Memory system 215 may correspond to memory system 110. Host device 210 may include a CPU. In some implementations, host device 210 corresponds to host system 105 and / or host processor 150. Memory device(s) 230 may include volatile memory. In some implementations, memory device(s) 230 may include DRAM. In some implementations, memory device 230 may correspond to memory device 120.

[0037] The CXL controller 220 may include an ASIC, FPGA, or the like. The CXL controller 220 may include a CXL interface 222, a central controller 224, and one or more memory controllers 223. In some implementations, the CXL interface 222 may correspond to the host interface 140. In some implementations, the memory controller(s) 223 may correspond to the memory system controller 115.

[0038] In some embodiments, Figure 1 and / or Figure 2 One or more systems, devices, equipment, components and / or controllers may be configured to receive a command to: write data to a volatile memory, wherein the command indicates a logical address associated with the data; compare the data with one or more repeating data patterns (a "repeated data pattern" may refer to a data pattern representing data previously written to the memory or the underlying data itself, which may be used to identify whether new data to be written to the memory is a copy of the previously written data) to identify whether the data matches a repeating data pattern in the one or more repeating data patterns; and in response to the data matching the repeating data pattern, map a physical address associated with the repeating data pattern to the logical address without writing the data to the volatile memory.

[0039] In some embodiments, Figure 1 and / or Figure 2One or more systems, devices, equipment, components and / or controllers of a memory system may be configured to receive a command to write data to a volatile memory of a memory system, wherein the command indicates a logical address associated with the data; retrieve a repeating data pattern using information in a local memory of the controller; compare the data to the repeating data pattern to identify whether the data matches the repeating data pattern; and in response to the data matching the repeating data pattern, map a physical address associated with the repeating data pattern to the logical address without writing the data to the volatile memory.

[0040] Figure 2 The number and arrangement of components shown in FIG are provided as examples. In practice, compared to Figure 2 There may be additional components, fewer components, different components, or components arranged in a different manner than those shown in FIG. Figure 2 Two or more components shown in may be implemented in a single component, or Figure 2 The single component shown in may be implemented as multiple distributed components. Additionally or alternatively, Figure 2 A set of components (e.g., one or more components) shown in Figure 2 One or more operations performed by another set of components shown in .

[0041] Figure 3 is a diagram illustrating a central controller 224 and memory devices 230 of system 200. As shown, central controller 224 may include an input logic component 225, a deduplication engine 226, a content addressable memory (CAM) 227, local memory 228 (e.g., SRAM or other volatile memory), and one or more block allocators 229.

[0042] Input logic component 225 may be configured to receive read commands and / or write commands and / or exchange data with CXL interface 222. Additionally, input logic component 225 may be configured to provide address information and / or exchange data with deduplication engine 226.

[0043] The deduplication engine 226 may include a CPU or the like. The deduplication engine 226 may be configured to track the data content of the memory blocks, as described herein. The deduplication engine 226 may also be configured to resolve logical addresses into physical addresses. The deduplication engine 226 may be communicatively coupled to the CAM 227, the local memory 228, and the block allocator 229. The block allocator 229 may control the allocation and freeing (e.g., releasing) of memory blocks of the memory device 230. In an allocation operation, the block allocator 229 may return the address of a block that can be freely written to, which may be used when a user requests to write a unique block. In a release operation, the block allocator 229 may mark a block as no longer needed so that the block can be used for new data, which may be used when overwriting a unique block with copied content, so that the memory location of the block can be used for other purposes. The central controller 224 may include a block allocator 229 for each memory bank of the storage device 230 (eg, to provide improved performance), and the block allocators 229 may be accessed in a round-robin manner.

[0044] Memory device 230 (e.g., DRAM) may include volatile memory 232 (e.g., for user data), a pointer data structure 234 (e.g., a table), a reference counter data structure 236 (e.g., a table), and one or more free block bitmap components 238. In some implementations, volatile memory 232 may correspond to one or more memory arrays 130. Pointer data structure 234 may indicate a mapping of logical addresses to physical addresses of volatile memory 232. Reference counter data structure 236 may indicate corresponding reference counters for corresponding physical addresses of volatile memory 232, as described herein. Memory device 230 may include one free block bitmap component 238 for each bank of memory device 230. Free block bitmap component 238 may provide tracking of free and used blocks of volatile memory 232. In some implementations, pointer data structure and / or reference counter data structure may be cached in central controller 224 to provide improved performance.

[0045] Figure 3 The number and arrangement of components shown in FIG are provided as examples. In practice, compared to Figure 3 There may be additional components, fewer components, different components, or components arranged in a different manner than those shown in FIG. Figure 3 Two or more components shown in may be implemented in a single component, or Figure 3 The single component shown in may be implemented as multiple distributed components. Additionally or alternatively, Figure 3 A set of components (e.g., one or more components) shown in Figure 3One or more operations performed by another set of components shown in .

[0046] Figures 4A to 4C FIG is a diagram of an example 400 of online deduplication of volatile memory. Figures 4A to 4C The described operations may be performed by the memory system 215 and / or one or more components of the memory system 215, such as the CXL controller 220 and / or the central controller 224 (eg, the deduplication engine 226). Additionally or alternatively, in conjunction with Figures 4A to 4C The described operations may be performed by memory system 110 and / or one or more components of memory system 110, such as memory system controller 115, one or more memory devices 120, and / or one or more local controllers 125. As an example, the following description describes operations as being performed by a controller, such as CXL controller 220 and / or central controller 224.

[0047] As shown, example 400 includes CAM 402, data structure 404, map 406, memory device 408, data structure 410, and hash components 412-1, 412-2, and 412-3. CAM 402 may correspond to CAM 227 of central controller 224. In some implementations, CAM 402 may be another type of memory, such as RAM. Data structure 404 may be in local memory 228 of central controller 224. Data structure 404 may be referred to herein as "hot data structure 404." Map 406 may correspond to one or more pointer data structures 234. Memory device 408 may correspond to memory device 230. Data structure 410 may be in local memory 228 of central controller 224. Data structure 410 may be referred to herein as "tracking data structure 410." Hash component 412 may be implemented by central controller 224.

[0048] Memory device 408 may include volatile memory (shown as "Data") and a reference counter data structure (shown as "RefCount"). The volatile memory of memory device 408 may correspond to volatile memory 232. For example, the volatile memory may be DRAM. The reference counter data structure may correspond to reference counter data structure 236. The volatile memory may include multiple memory locations (e.g., blocks), and each memory location may be associated with a physical address. For example, a physical address may indicate a physical location in the volatile memory, such as a block in which data may be stored. Each physical address may be associated with a reference counter that indicates the number of logical addresses mapped to the physical address (e.g., in conjunction with deduplication).

[0049] The CAM 402 and the hot data structure 404 can be used for read and write operations associated with frequently occurring data patterns (e.g., blocks of all 0 bits or blocks of all 1 bits) (which can be referred to as "hot data patterns"). Because these hot data patterns occur frequently, using the CAM 402 and the hot data structure 404, which can be implemented in the local memory 228 of the central controller 224 (e.g., closer to the central controller 224), improves the speed at which read and write operations can be performed. However, in some embodiments, the CAM 402 and the hot data structure 404 may not be used for deduplication operations, such as in conjunction with Figures 5A to 5E described.

[0050] CAM 402 may store an association (e.g., as a key-value pair) between a physical address of volatile memory and an entry address of an entry in hot data structure 404. Hot data structure 404 may store one or more entries. Each entry may be associated with an entry address. Each entry may indicate a repeating data pattern representing data previously written to volatile memory (shown as a "Pattern" field), a physical address of volatile memory containing the previously written data (shown as a "PAddress" field), and a reference counter (shown as a "RefCount" field) indicating the number of logical addresses mapped to the physical address (e.g., in conjunction with deduplication).

[0051] Map 406 may represent a mapping of logical memory addresses (sometimes referred to as logical addresses) to physical memory addresses (sometimes referred to as physical addresses). For example, a physical address written to a location in map 406 addressed by a logical address indicates that the physical address is mapped to the logical address. Tracking data structure 410 may store one or more entries. Each entry may be associated with an entry address. Each entry may indicate a physical address of volatile memory containing previously written data (shown as a "PAddress" field) and a stored data representation of the previously written data (e.g., a hash value of the previously written data).

[0052] Each of the hash components 412 may use a hash function to convert input data into a hash value. For example, the first hash component 412-1 may use a first hash function, the second hash component 412-2 may use a second hash function, and the third hash component 412-3 may use a third hash function. The hash functions may be non-cryptographic hash functions, such as a cyclic redundancy check (CRC). The first hash component 412-1 may be configured to convert data associated with a write command into a hash value that serves as an entry address of an entry in the tracking data structure 410 (e.g., the entry address is used as an index into the tracking data structure 410). The second hash component 412-2 may be configured to convert data associated with a write command into a hash value that serves as a representation of the data in the tracking data structure 410. The third hash component 412-3 may be configured to convert data associated with a write command into a hash value that serves as an entry address of an entry in the hot data structure 404 (e.g., the entry address is used as an index into the hot data structure 404). A hash value derived from data associated with a write command may be smaller than the data itself, thereby allowing the data to be tracked with a reduced storage burden.

[0053] In a write operation, such as Figure 4A 4 and shown by reference number 420, the controller may receive a command to write new data to the volatile memory. The command may come from a host device (e.g., host device 210). The command may indicate a logical address associated with the new data (e.g., a logical address to which the new data is to be written).

[0054] As shown by reference numeral 422, the controller can obtain an old physical address (e.g., of volatile memory) currently mapped to the logical address via mapping 406. For example, the controller can use mapping 406 to translate the logical address into the old physical address. Previously written data (e.g., different from the new data of the write command) may have been stored at the old physical address mapped to the logical address. Therefore, before the logical address can be used in conjunction with the write command, the controller can perform various housekeeping operations with respect to the old physical address, as described in conjunction with reference numerals 424 and 426.

[0055] As shown by reference number 424, the controller may retrieve an old entry address associated with the old physical address from the CAM 402. For example, the controller may search the CAM 402 using the old physical address and, if the old entry address exists in the CAM 402, may retrieve the old entry address. The old entry address may point to an old entry in the hot data structure 404. The old entry may indicate a repeating data pattern representing data previously written to the volatile memory (e.g., for deduplication), an old physical address of the volatile memory for the previously written data, and a reference counter indicating the number of logical addresses mapped to the old physical address.

[0056] As shown by reference number 426, the controller can decrement the reference counter for the old entry in the hot data structure 404. For example, because the logical address will no longer be associated with the old physical address (e.g., once a write command is executed), the reference counter can be decremented to indicate that one less logical address is associated with the old physical address. The controller can decrement the reference counter using a read-modify-write operation.

[0057] After the housekeeping operations with respect to the old physical address are completed, the logical address can then be used for the new data of the write command. However, instead of simply writing the new data to the volatile memory, the controller can perform a deduplication operation to check whether the logical address can be mapped to an already used physical address and not allocate a new block of volatile memory for the new data.

[0058] like Figure 4B As shown in FIG4 and by reference numeral 428, the controller may use the new data of the write command to derive an entry address of the hot data structure 404. For example, the controller may use a third hash function (e.g., using third hash component 412-3) to convert the new data into an entry address. As shown in FIG4 by reference numeral 430, the controller may retrieve an entry associated with the entry address from the hot data structure 404 (e.g., if such an entry exists). In a manner similar to that described above, the entry may indicate a repeating data pattern representing data previously written to the volatile memory (e.g., for deduplication), a physical address of the volatile memory for the previously written data, and a reference counter indicating the number of logical addresses mapped to the physical address. The repeating data pattern may be used to identify duplicate data. Thus, the controller may use information in the controller's local memory (e.g., information in the hot data structure 404) to retrieve the repeating data pattern.

[0059] As shown by reference numeral 432, the controller may compare the new data to the duplicate data pattern to identify whether the new data matches the duplicate data pattern (e.g., is a duplicate thereof). For example, a match between the new data and the duplicate data pattern indicates that the new data can be deduplicated (e.g., not written to volatile memory).

[0060] Thus, in response to the new data matching the duplicate data pattern (e.g., the current write operation uses the hot data pattern), as shown by reference number 434, the controller may map the physical address associated with the data pattern (e.g., indicated by the entry) to a logical address (e.g., the physical address may be written to a location in mapping 406 addressed by the logical address) without writing the new data to the volatile memory. Thus, the duplicated data (e.g., the duplicated block) may be associated with the same physical address but a different logical address. By mapping the physical address to the logical address, although the data is not actually written to the volatile memory in conjunction with the write command, a subsequent read command to the logical address will return the correct data (e.g., will return the duplicate data pattern, which is a copy of the new data of the write command), thereby saving significant memory resources.

[0061] In addition, in response to the new data matching the repeating data pattern, the controller may (e.g., using a read-modify-write operation) increment a reference counter for an entry in the hot data structure 404, as shown by reference number 436. Incrementing the reference counter indicates that an additional logical address is now mapped to the physical address. In some embodiments, the controller may decrement a reference counter associated with the old physical address in volatile memory that was mapped to the logical address prior to the remapping described at reference number 434 (e.g., using a read-modify-write operation). If the reference counter associated with the old physical address has a value of 1, the controller may cause the old physical address to be released (e.g., because there are no longer any logical addresses mapped to the old physical address).

[0062] In a read operation, such as Figure 4C As shown in FIG4 and by reference number 438, the controller may receive a command to read data from the volatile memory. The command may come from a host device (e.g., host device 210). The command may indicate a logical address associated with the data (e.g., a logical address containing the data to be read). As shown by reference number 440, the controller may obtain a physical address (e.g., of the volatile memory) mapped to the logical address by mapping 406 in a manner similar to that described above. As shown by reference number 442, the controller may retrieve an entry address associated with the physical address from CAM 402 in a manner similar to that described above. The entry address may point to an entry in hot data structure 404.

[0063] As shown by reference number 444, the controller can retrieve an entry for the entry address from the hot data structure 404. The entry can indicate a data pattern representing data previously written to the volatile memory (e.g., a repeating data pattern), a physical address of the volatile memory for the previously written data, and a reference counter indicating the number of logical addresses mapped to the physical address, in a manner similar to that described herein. Thus, the data pattern is responsive to the read command (e.g., the data requested by the read command is a duplicate of the data pattern), and the read operation can be performed without retrieving the data from the volatile memory (e.g., which is slower than retrieving the data pattern from the hot data structure 404). As shown by reference number 446, the controller can return (e.g., output) the data pattern to the host device in response to the read command.

[0064] As indicated above, Figures 4A to 4C are provided as examples. Other examples may be relevant to Figures 4A to 4C What is described is different.

[0065] Figures 5A to 5E FIG is a diagram of an example 500 of online deduplication of volatile memory. Figures 5A to 5E The described operations may be performed by the memory system 215 and / or one or more components of the memory system 215, such as the CXL controller 220 and / or the central controller 224 (eg, the deduplication engine 226). Additionally or alternatively, in conjunction with Figures 5A to 5E The described operations may be performed by the memory system 110 and / or one or more components of the memory system 110, such as the memory system controller 115, the one or more memory devices 120, and / or the one or more local controllers 125. As an example, the following description describes the operations as being performed by a controller, such as the CXL controller 220 and / or the central controller 224.

[0066] As shown, instance 500 includes a map 406, a memory device 408, a tracking data structure 410, and hash components 412-1 and 412-2, as described in conjunction with Figures 4A to 4C In some embodiments, the CAM 402 and the hot data structure 404 may not be used for deduplication operations. For example, although the CAM 402 and the hot data structure 404 may improve performance by using hot data patterns, in some embodiments, the CAM 402 and the hot data structure 404 may not be used in order to reduce complexity. As another example, referring back to Figure 4B As shown in reference number 432, when the data pattern (e.g., in an entry of the hot data structure 404) does not match the new data of the write command (e.g., the new data of the write command is not the hot pattern), the CAM 402 and the hot data structure 404 may not be used in the deduplication operation.

[0067] In a write operation, such as Figure 5A and shown by reference numeral 520, the controller may be combined with Figures 4A to 4C In some embodiments, if hot data mode is being used, the controller may execute a command to write new data to the volatile memory in a manner similar to that described above. For example, the command may indicate a logical address associated with the new data. Figure 4B The controller may then execute the operations described at reference numbers 428, 430, and 432 to obtain an entry from the hot data structure 404. If the entry indicates a repeating data pattern that does not match the new data of the write command, the controller may then execute the operations described at reference numbers 428, 430, and 432 to obtain an entry from the hot data structure 404. Figures 4A to 4C Similarly, if the hot data mode is not used (e.g., eliminating CAM 402 and hot data structure 404), the controller may Figures 4A to 4C Deduplication is performed differently as described in .

[0068] As shown by reference number 522, the controller can use the new data for the write command to derive an entry address for the tracking data structure 410. For example, the controller can use a first hash function (e.g., using first hash component 412-1) to convert the new data into an entry address. In some embodiments, the controller can also derive a data representation of the new data. For example, the controller can use a second hash function (e.g., using second hash component 412-2) to convert the new data into a data representation. In some cases, the first hash function can generate a collision, whereby the first hash function can output the same entry address for different input data in the tracking data structure 410 (e.g., because the output hash value generated by the first hash function is smaller than the input data). Therefore, the data representation generated by the second hash function can resolve the collision by providing an auxiliary hash value for the input data (e.g., the likelihood that different input data will generate the same entry address and the same data representation is small).

[0069] As shown by reference number 524, the controller can retrieve an entry associated with the entry address from the tracking data structure 410 (e.g., if such an entry exists). The entry can indicate a physical address of the volatile memory containing the previously written data, and a stored data representation derived using a second hash function on the previously written data. As shown by reference number 526, the controller can compare the data representation with the stored data representation to identify whether the data representation matches the stored data representation. For example, if the data representation does not match the stored data representation, it can indicate that the new data and the previously written data at the physical location are not duplicates (e.g., the first hash function produced a collision). Alternatively, if the data representation matches the stored data representation, it can indicate that the new data and the previously written data at the physical address are likely duplicates.

[0070] As shown by reference number 528, in response to the data representation matching the stored data representation, the controller can retrieve previously written data from the physical address of the volatile memory. The previously written data is a repeating data pattern because the previously written data can be used to identify the repeating data. Therefore, the controller can use information in the controller's local memory (e.g., information in the tracking data structure 410) to retrieve the repeating data pattern. The physical address can be associated with a reference counter indicating the number of logical addresses mapped to the physical address.

[0071] As shown by reference numeral 530, the controller may compare the new data of the write command with the previously written data (i.e., the repeating data pattern) to identify whether the new data matches (e.g., is a duplicate of) the previously written data. For example, a match between the new data and the previously written data indicates that the new data can be deduplicated (e.g., not written to volatile memory).

[0072] Thus, in response to the new data matching the previously written data (eg, the new data is a copied write pattern), as Figure 5B As shown in FIG4 and by reference number 532, the controller may map a physical address associated with previously written data (e.g., indicated by an entry) to a logical address (e.g., the physical address may be written to a location in map 406 addressed by the logical address) without writing the data to the volatile memory. Thus, the copied data (e.g., a copied block) may be associated with the same physical address but a different logical address. By mapping the physical address to the logical address, although the data was not actually written to the volatile memory in conjunction with the write command, a subsequent read command to the logical address will return the correct data (e.g., will return the previously written data that is a copy of the new data of the write command), thereby saving significant memory resources.

[0073] In addition, in response to the new data matching the previously written data, the controller may (e.g., using a read-modify-write operation) increment a reference counter associated with the physical address in the volatile memory, as shown by reference number 534. Incrementing the reference counter indicates that an additional logical address is now mapped to the physical address. In some embodiments, the controller may decrement a reference counter associated with the old physical address in the volatile memory that was mapped to the logical address before the remapping described at reference number 532 (e.g., using a read-modify-write operation). If the reference counter associated with the old physical address has a value of 1, the controller may cause the old physical address to be released (e.g., because there are no longer any logical addresses mapped to the old physical address).

[0074] The data representation does not match the stored data representation and / or the new data does not match the previously written data in the volatile memory may indicate that the new data of the write command is not a duplicate. Therefore, in response to the data representation not matching the stored data representation and / or the new data not matching the previously written data (and / or in response to the address of the entry based on the new data not being present in the hot data structure 404 and / or the tracking data structure 410), the controller may cause the new data to be written to the volatile memory. Figure 5C As shown in FIG4 and by reference number 536, if the reference counter associated with the physical address of the previously written data has a value of 1, the previously written data at the physical address may be overwritten with the new data of the write command. As shown by reference number 538, if corresponding data does not exist in the volatile memory for the logical address (e.g., the logical address that previously pointed to CAM 402 and hot data structure 404) or if the reference counter associated with the physical address of the previously written data has a value greater than 1, the controller may cause a new block to be allocated in the volatile memory. Furthermore, the controller may map the new physical address of the new block to a logical address (e.g., the new physical address may be written to a location addressed by the logical address mapping 406), as shown by reference number 540, and the controller may cause the new data of the write command to be written to the new physical address of the new block, as shown by reference number 542. Furthermore, as shown by reference number 544, if the reference counter associated with the physical address of the previously written data has a value greater than 1, the controller may decrement the reference counter (e.g., using a read-modify-write operation). For example, because the logical address will no longer be associated with a physical address (eg, once a write command is executed), the reference counter may be decremented to indicate that one less logical address is associated with the physical address.

[0075] In some embodiments, if the new data for a write command is written to volatile memory (e.g., the new data is not a replica), then tracking of the new data can be initiated to enable subsequent write commands to check the replica against the new data of the current write command. For example, tracking of the new data can be initiated in response to one or more conditions (e.g., metrics) being met (e.g., the conditions can be evaluated during a write operation). As an example, the condition can be that the new data has low (e.g., does not exceed a threshold) data entropy (e.g., the new data is all 0 bits or all 1 bits). As another example, the condition can be that other data currently being tracked is associated with a low (e.g., does not exceed a threshold) reference count (e.g., the other data is not copied often). Figure 5DTo initiate tracking of new data, the controller may record an entry in the tracking data structure 410 that indicates the physical address in the volatile memory to which the new data is written and a stored data representation of the new data (e.g., derived using the second hash function on the new data) as shown in FIG. 4 and by reference number 546. The entry may be recorded in the tracking data structure 410 at an entry address derived using the new data (e.g., derived using the first hash function on the new data). In some examples, recording an entry at the entry address may overwrite a previous entry at the entry address.

[0076] In some implementations, the new data of a write command can be promoted to hot data mode. For example, the new data can be promoted to hot data mode in response to one or more conditions (e.g., metrics) being met (e.g., the conditions can be evaluated during a write operation). As an example, the condition can be that the physical address containing the new data in the volatile memory is associated with a high (e.g., meeting a threshold) reference count. As another example, the condition can be that the data pattern (representing the new data and its replicas) has been involved in a large number (e.g., meeting a threshold) of read operations and / or write operations. Before promoting the new data to hot data mode, the controller can perform various housekeeping operations to maintain reference counters for the old data pattern to be overwritten, as described in conjunction with reference numbers 548 to 552.

[0077] As shown by reference numeral 548, the controller can use the new data of the write command (e.g., using a third hash function) to derive an entry address of the hot data structure 404, as described herein. As shown by reference numeral 550, the controller can retrieve an old entry at the entry address from the hot data structure 404. The old entry can indicate an old data pattern, an old physical address in volatile memory associated with the old data pattern, and an old reference counter associated with the old data pattern. As shown by reference numeral 552, the controller can update the reference counter in volatile memory associated with the old physical address to the value of the old reference counter.

[0078] After the housekeeping operations for the old data pattern are completed, the new data can then be promoted to the hot data pattern. As shown by reference number 554, the controller can record an entry in the hot data structure 404 indicating the physical address in the volatile memory containing the new data and a repeating data pattern representing the new data (e.g., the repeating data pattern is the same as the new data). The entry can be recorded in the hot data structure 404 at an entry address derived using the new data (e.g., derived using a first hash function on the new data). In some examples, recording the entry at the entry address may overwrite the old entry at the entry address. As shown by reference number 556, the controller can record association data (e.g., a key-value pair) in the CAM 402 (shown in FIG. 4 ) indicating the association between the physical address in the volatile memory containing the new data and the entry address.

[0079] In a read operation, such as Figure 5E As shown in FIG5 and by reference number 558, the controller may receive a command to read data from the volatile memory. The command may come from a host device (e.g., host device 210). The command may indicate a logical address associated with the data (e.g., a logical address containing the data to be read). As shown by reference number 560, the controller may obtain a physical address (e.g., of the volatile memory) mapped to the logical address by mapping 406 in a manner similar to that described above. As shown by reference number 562, the controller may retrieve duplicate data from the physical address of the volatile memory (e.g., if the data requested by the read command is deduplicated). For example, if the physical address is not indexed in CAM 402 (e.g., thereby indicating that the data to be read is not a hot data pattern), the controller may retrieve the duplicate data from the physical address of the volatile memory. As shown by reference number 564, the controller may return (e.g., output) the duplicate data to the host device in response to the read command.

[0080] As indicated above, Figures 5A to 5E are provided as examples. Other examples may be relevant to Figures 5A to 5E What is described is different.

[0081] Figures 6A to 6C FIG is a diagram of an example 600 of online deduplication of volatile memory. Figures 6A to 6C The described operations may be performed by the memory system 215 and / or one or more components of the memory system 215, such as the CXL controller 220 and / or the central controller 224 (eg, the deduplication engine 226). Additionally or alternatively, in conjunction with Figures 6A to 6C The described operations may be performed by memory system 110 and / or one or more components of memory system 110, such as memory system controller 115, one or more memory devices 120, and / or one or more local controllers 125. As an example, the following description describes operations as being performed by a controller, such as CXL controller 220 and / or central controller 224.

[0082] As shown, example 600 includes a map 602, a memory device 604, a data structure 606, and a hash component 608. Map 602 may correspond to one or more pointer data structures 234. Memory device 604 may correspond to memory device 230. Data structure 606 may be in local memory 228 of central controller 224. Data structure 606 may be referred to herein as "pattern data structure 606." Hashing component 608 may be implemented by central controller 224.

[0083] Memory device 604 may include volatile memory (shown as "Data") in a manner similar to memory device 408. The volatile memory of memory device 604 may correspond to volatile memory 232. For example, the volatile memory may be DRAM. The volatile memory may include multiple memory locations (e.g., blocks) and each memory location may be associated with a physical address. For example, a physical address may indicate a physical location in the volatile memory, such as a block in which data may be stored. Memory device 604 may not include a reference counter data structure, such as in conjunction with Figures 4A to 4C and as described in 5A to 5E.

[0084] Map 602 may indicate a mapping of logical addresses to physical addresses in a manner similar to map 406. For example, a physical address written to a location in map 602 addressed by a logical address indicates that the physical address is mapped to a logical address. In some embodiments, map 602 may use a location indicator (e.g., a single bit per physical address) to indicate, for each respective physical address, whether the respective physical address is for volatile memory or pattern data structure 606.

[0085] The pattern data structure 606 may store one or more entries. Each entry may be associated with an entry address. Each entry may indicate a repeating data pattern (shown as a "pattern" field). The repeating data pattern of the pattern data structure 606 may be a configured (e.g., fixed) data pattern. By using the configured data pattern, the combination of Figures 4A to 4C 5A to 5E , thereby simplifying deduplication operations and consuming less processor and / or memory resources. The configured data pattern can be loaded into the pattern data structure 606 by the controller's firmware at boot time. Additionally or alternatively, the configured data pattern can be provided by an end user (e.g., through a specific command) through an out-of-band channel. The configured data pattern can be a data pattern with a high probability of being repeated (e.g., a block of all 0 bits or a block of all 1 bits).

[0086] The hash component 608 can convert the input data into a hash value using a hash function (e.g., the first hash function described in Figures 4 and 5) in a manner similar to that described above. The hash component 608 can be configured to convert the data associated with the write command into a hash value that is used as an entry address of an entry of the pattern data structure 606 (e.g., the entry address is used as an index into the pattern data structure 606).

[0087] In a write operation, such as Figure 6A4 and 5 , the controller may receive a command to write new data to the volatile memory. For example, the command may indicate a logical address associated with the new data. As shown by reference numeral 622, the controller may use mapping 602 to obtain an old physical address mapped to the logical address and a location indicator for the old physical address. The location indicator for the old physical address may indicate whether the old physical address is associated with the volatile memory or the pattern data structure 606.

[0088] As shown by reference number 624, the controller can use the new data of the write command to derive an entry address of the pattern data structure 606. For example, the controller can use a hash function (e.g., using hash component 608) to convert the new data into an entry address. The entry address can point to an entry in the pattern data structure 606.

[0089] As shown by reference number 626, the controller can retrieve an entry associated with the entry address from pattern data structure 606 (e.g., if such an entry exists). The entry can indicate a configured data pattern (i.e., a repeating data pattern). The configured data pattern can be used to identify repeating data. Therefore, the controller can retrieve the repeating data pattern using information in the controller's local memory (e.g., information in pattern data structure 606).

[0090] As shown by reference numeral 628, the controller may compare the new data to the configured data pattern (i.e., the duplicate data pattern) to determine whether the new data matches the configured data pattern (e.g., is a duplicate thereof). For example, a match between the new data and the configured data pattern indicates that the new data can be deduplicated (e.g., not written to volatile memory).

[0091] Therefore, in response to the new data matching the configured data pattern, the controller may map the physical address associated with the configured data pattern (which in this case is the entry address) to a logical address (e.g., may write the entry address to a location of mapping 602 addressed by the logical address) without writing the new data to the volatile memory, as shown by reference number 630. By mapping the physical address to the logical address, although the data is not actually written to the volatile memory in conjunction with the write command, a subsequent read command to the logical address will return the correct data (e.g., will return the configured data pattern, which is a copy of the new data of the write command), thereby saving a significant amount of memory resources.

[0092] Furthermore, in response to the new data of the write command matching the configured data pattern, as shown by reference numeral 632, the controller may set the location indicator in the mapping 602 (which is now associated with the physical address rather than the old physical address) to indicate that the physical address is associated with the pattern data structure 606. If, prior to the remapping described at reference numeral 632, the location indicator had been set to indicate that the old physical address was associated with volatile memory, then as shown by reference numeral 634, the controller may cause the old physical address in the volatile memory to be freed (e.g., because the logical address will no longer be associated with the old physical address in the volatile memory).

[0093] In response to the new data not matching the configured data pattern (and / or in response to the address of the entry based on the new data not being present in the pattern data structure 606), and if the location indicator is set to indicate that the old physical address is associated with volatile memory, then Figure 6B 6 and shown by reference number 636, the controller may cause the new data of the write command to be written to the old physical address in the volatile memory. Conversely, in response to the data not matching the configured data pattern, and if the location indicator is set to indicate that the old physical address is associated with the pattern data structure 606, the controller may cause the new block to be allocated in the volatile memory, as shown by reference number 638. Furthermore, the controller may map the new physical address of the new block to a logical address (e.g., the new physical address may be written to a location of the mapping 602 addressed by the logical address), as shown by reference number 640, set the location indicator of the new physical address to indicate that the new physical address is associated with the volatile memory, as shown by reference number 642, and cause the new data of the write command to be written to the new physical address of the new block, as shown by reference number 644.

[0094] In a read operation, such as Figure 6C As shown in FIG. 4 and by reference number 646, the controller may receive a command to read data from the volatile memory. The command may come from a host device (e.g., host device 210). The command may indicate a logical address associated with the data (e.g., a logical address containing the data to be read). As shown by reference number 648, the controller may obtain the physical address and location indicator mapped to the logical address by mapping 406 in a manner similar to that described above.

[0095] If the location indicator indicates that the physical address is associated with volatile memory, the controller may retrieve duplicate data from the physical address of the volatile memory (e.g., if the data requested by the read command is deduplicated), as shown by reference numeral 650. If the location indicator indicates that the physical address is associated with the pattern data structure 606, the controller may retrieve the configured data pattern from the physical address (e.g., entry address) of the pattern data structure 606, as shown by reference numeral 652. As shown by reference numeral 654, the controller may return (e.g., output) the duplicate data or the configured data pattern (depending on which was retrieved) to the host device in response to the read command.

[0096] As indicated above, Figures 6A to 6C are provided as examples. Other examples may be relevant to Figures 6A to 6C What is described is different.

[0097] Figures 7A to 7C is a diagram of an example of block allocation 700. The techniques described in example 700 can be used to identify addresses of memory blocks (e.g., of volatile memory) that can be freely written to. Thus, these blocks can be allocated for writing in conjunction with the online deduplication of volatile memory described herein.

[0098] Combine Figures 7A to 7C The operations described may be performed by the memory system 215 and / or one or more components of the memory system 215 (e.g., the CXL controller 220 and / or the central controller 224). Additionally or alternatively, in conjunction with Figures 7A to 7C The described operations may be performed by memory system 110 and / or one or more components of memory system 110, such as memory system controller 115, one or more memory devices 120, and / or one or more local controllers 125. As an example, the following description describes the operations as being performed by a controller, such as CXL controller 220 and / or central controller 224. For example, the operations may be performed by central controller 224 using one or more block allocators 229.

[0099] As shown, example 700 includes a data structure 702, a bitmap queue 704, and an available block queue 706. Data structure 702 may be implemented in a memory device described herein, such as memory device 230 (e.g., in one or more free block bitmap components 238), memory device 408, and / or memory device 604. For example, data structure 702 may correspond to free block bitmap component 238 of memory device 230. Data structure 702 may be referred to herein as "available block data structure 702." Available block data structure 702 may store multiple bitmaps 703 in respective entries. Each bit of bitmap 703 corresponds to a respective block of the memory device and indicates whether that block is available (e.g., to be written to) or unavailable. In example 700, a 0 bit is used to indicate that a block is free and a 1 bit is used to indicate that a block is occupied; however, in practice, the reverse may also be used. The bitmaps 703 in available block data structure 702 may represent memory blocks in order. For example, the bitmap 703 in the first entry of the available blocks data structure 702 may represent blocks for memory addresses 0 to 19, the bitmap 703 in the second entry of the available blocks data structure 702 may represent blocks for memory addresses 20 to 39, and so on.

[0100] The bitmap queue 704 may comprise a data structure. The bitmap queue 704 may be implemented in the local memory 228 and / or the block allocator 229 of the central controller 224. The bitmap queue 704 may be used to track the status of the bitmap 703 read from the available block data structure 702. The available block queue 706 may comprise a data structure. The available block queue 706 may be implemented in the local memory 228 and / or the block allocator 229 of the central controller 224. The available block queue may be used to track the addresses of available memory blocks.

[0101] The controller may return the addresses of one or more available blocks in response to a request for available blocks from a requester, such as CXL controller 220, central controller 224, or memory controller 223. For example, the controller may receive a request for available (e.g., free) blocks, and in response to the request, the controller may perform one or more block allocation operations (as described herein) to identify available blocks.

[0102] In some embodiments, the controller may identify that the number of entries in the free block queue 706 is below a threshold, thereby indicating that the free block queue 706 should be replenished. To replenish the free block queue 706, as Figure 7A7 and shown by reference number 710, the controller may read one or more bitmaps 703 from the free block data structure 702. As shown by reference number 712, for each bitmap 703 read from the free block data structure 702, the controller may add a copy 705 of that bitmap as an entry in the bitmap queue 704. For example, the bitmap copy 705 may be added at the end of the bitmap queue 704.

[0103] As shown by reference number 714, for each bitmap 703 read from the available block data structure 702 and copied into the bitmap queue 704, the controller can scan the bitmap 703 to identify any available blocks indicated by the bitmap 703. For example, the controller can iterate over each bit of the bitmap 703 to identify any available blocks. If the bit of the bitmap 703 indicates that the block is occupied (e.g., the bit has a value of 1), the controller can proceed to the next bit. If the bit of the bitmap 703 indicates that the block is available (e.g., the bit has a value of 0), the controller can add an entry 707 at the end of the available block queue 706 and then proceed to the next bit, as shown by reference number 716.

[0104] The entry 707 recorded in the free block queue 706 may have multiple fields. The first field (shown as "Block Address") may indicate the address (e.g., physical address) of the free block. The controller may identify the address corresponding to the free block based on the position of the bit in the bitmap 703 and the position of the entry in the bitmap 703 in the free block data structure 702 (e.g., because the bitmap 703 in the free block data structure 702 may sequentially represent memory addresses, as described herein).

[0105] The second field (shown as "B") (which may be referred to as a "boundary bit") may indicate whether the bit is in the end position (e.g., the leftmost position) of bitmap 703. For example, a 0 bit may be used to indicate that the bit is not in the end position and a 1 bit may be used to indicate that the bit is in the end position; however, in practice, the reverse may also be used. The third field (shown as "F") (which may be referred to as a "released block bit") may indicate whether the available block is available due to being released (e.g., by the requester) or unavailable due to being released (e.g., identifying the available block from bitmap 703). For example, a 0 bit may be used to indicate that the block is not released and a 1 bit may be used to indicate that the block is released; however, in practice, the reverse may also be used.

[0106] like Figure 7BAs shown in FIG. 7 and by reference number 718, when a requester requests a block, the controller may remove and read the first entry 707 from the front of the available block queue 706, and the controller may return (e.g., output) the block address indicated by entry 707 as an available block. Thus, the available block is no longer available. To indicate this, as shown by reference number 720, the controller may update (e.g., flip) the bit corresponding to the block in the first bitmap copy 705 at the front of the bitmap queue 704 to indicate that the block is occupied. For each bitmap copy 705 (e.g., where the boundary bit of entry 707 indicates whether the next entry 707 will represent a different bitmap), the order of the blocks in the available block queue 706 corresponds to the order of the 0s (zeros) in that bitmap copy 705. Thus, when allocating the first block associated with bitmap copy 705, the controller may flip the first (e.g., rightmost) 0 bit in bitmap copy 705, when allocating the second block associated with bitmap copy 705, the controller may flip the second 0 bit in bitmap copy 705, and so on.

[0107] As shown by reference number 722, once all bits in the first bitmap copy 705 indicate an occupied block (e.g., the first bitmap copy 705 indicates a value of 1 for each bit), the controller can remove the first bitmap copy 705 from the bitmap queue 704 and overwrite the corresponding bitmap 703 in the free block data structure 702 with the first bitmap copy 705. Sometimes, the controller can receive an indication from the requestor that a block has been released. Here, as shown by reference number 724, the controller can add a new entry 707 at the end of the free block queue 706 in a manner similar to that described above. In the new entry 707, the freed block bit can indicate that the block is available due to being released (e.g., the freed block bit can be set to 1 in the new entry 707).

[0108] In some embodiments, the controller may identify that the number of entries in the free block queue 706 is above a threshold, thereby indicating that the free block queue 706 should be emptied. To empty the free block queue 706 (e.g., reduce the number of entries therein), as Figure 7C706 , the controller may traverse the entries 707 in the free block queue 706 starting at the front of the free block queue 706. If the entry 707 indicates a free block that was released (e.g., the released block bit has a value of 1), the controller may remove the entry 707 from the front of the free block queue 706 and add the entry 707 back to the end of the free block queue 706. If the entry 707 indicates a free block that was not released (e.g., the released block bit has a value of 0), the controller may remove the entry 707 from the front of the free block queue 706 without adding the entry 707 back to the end of the free block queue 706. Additionally, as shown by reference number 728, the controller may update the bit for that block in the corresponding bitmap copy 705 of the bitmap queue 704 (e.g., which would be at the front of the bitmap queue 704) to indicate that the block is available. As the controller traverses the entries 707, when the controller reaches an entry 707 for an available block whose boundary bit is set to indicate that the block corresponds to a bit at an end position, as shown by reference number 730, the controller may remove the corresponding bitmap copy 705 from the bitmap queue 704 (e.g., after any updates to the bitmap copy 705) and overwrite the corresponding bitmap 703 in the available block data structure 702 with the bitmap copy 705.

[0109] As indicated above, Figures 7A to 7C are provided as examples. Other examples may be relevant to Figures 7A to 7C What is described is different.

[0110] Figure 8 800 is a flow chart of an example method 800 associated with online deduplication of volatile memory. In some implementations, a controller (e.g., memory system controller 115, CXL controller 220, and / or central controller 224) may execute or be configured to execute method 800. In some implementations, another device or group of devices, separate from or including a controller (e.g., local controller 125 and / or memory controller 223), may execute or be configured to execute method 800. Additionally or alternatively, one or more components of the controller (e.g., deduplication engine 226) may execute or be configured to execute method 800. Thus, means for executing method 800 may include the controller and / or one or more components of the controller. Additionally or alternatively, a non-transitory computer-readable medium may store one or more instructions that, when executed by the controller, cause the controller to execute method 800.

[0111] like Figure 8 As shown in FIG, method 800 may include receiving a command to write data to a volatile memory of a memory system, wherein the command indicates a logical address associated with the data (block 810). Figure 8As further shown in FIG. 8 , method 800 may include retrieving a repeating data pattern using information in a local memory of the controller (block 820). Figure 8 As further shown in FIG. 8 , method 800 may include comparing the data to a repeating data pattern to identify whether the data matches the repeating data pattern (block 830). Figure 8 As further shown in FIG. 8 , method 800 may include, in response to the data matching the repeating data pattern, mapping a physical address associated with the repeating data pattern to a logical address without writing the data to volatile memory (block 840 ).

[0112] Method 800 may include additional aspects, such as any single aspect or any combination of aspects described below and / or in combination with one or more other methods or operations described elsewhere herein.

[0113] In a first aspect, method 800 includes deriving an entry address using data, wherein retrieving a repeating data pattern includes retrieving an entry associated with the entry address from a data structure of a local memory of a controller, wherein the entry indicates the repeating data pattern and a physical address.

[0114] In a second aspect, alone or in combination with the first aspect, method 800 includes deriving an entry address and a data representation using data, wherein retrieving a repeating data pattern includes retrieving an entry associated with the entry address from a data structure of a local memory of a controller, wherein the entry indicates a stored data representation and a physical address; comparing the data representation with the stored data representation to identify whether the data representation matches the stored data representation; and in response to the data representation matching the stored data representation, retrieving the repeating data pattern from a physical address of a volatile memory.

[0115] In a third aspect, alone or in combination with one or more of the first and second aspects, method 800 includes, in response to the data not matching a repeating data pattern, causing data to be written to a specific physical address of a volatile memory; recording an entry indicating the specific physical address and a data pattern representing the data in a data structure of a local memory of a controller, wherein an entry address of the entry is derived using the data; and recording association data indicating an association between the specific physical address and the entry address in a content addressable memory of the controller.

[0116] In a fourth aspect, alone or in combination with one or more of the first to third aspects, method 800 includes receiving an additional command to read data from a volatile memory, wherein the command indicates a logical address associated with the data; obtaining a physical address mapped to the logical address by a mapping of logical addresses to physical addresses, wherein the mapping includes a location indicator for the physical address, the location indicator indicating whether the physical address is for volatile memory or for a data structure of a local memory of a controller; retrieving duplicate data from the physical address of the volatile memory if the location indicator indicates that the physical address is for volatile memory, or retrieving a configured data pattern from the physical address of the data structure if the location indicator indicates that the physical address is for a data structure; and returning the duplicate data or the configured data pattern in response to the additional command.

[0117] although Figure 8 Example blocks of method 800 are shown, but in some embodiments, compared to Figure 8 , method 800 may include additional blocks, fewer blocks, different blocks, or blocks arranged in a different manner. Additionally or alternatively, two or more of the blocks of method 800 may be performed in parallel. Method 800 is an example of a method that may be performed by one or more devices described herein. The one or more devices may perform or be configured to perform one or more other methods based on the operations described herein.

[0118] In some embodiments, a system includes a volatile memory; and a controller configured to: receive a command to write data to the volatile memory, wherein the command indicates a logical address associated with the data; compare the data with one or more repeating data patterns to identify whether the data matches a repeating data pattern in the one or more repeating data patterns; and in response to the data matching the repeating data pattern, map a physical address associated with the repeating data pattern to the logical address without writing the data to the volatile memory.

[0119] In some embodiments, a method includes receiving, by a controller of a memory system, a command to write data to a volatile memory of the memory system, wherein the command indicates a logical address associated with the data; retrieving, by the controller, a repeating data pattern using information in a local memory of the controller; comparing, by the controller, the data with the repeating data pattern to identify whether the data matches the repeating data pattern; and mapping, by the controller and in response to the data matching the repeating data pattern, a physical address associated with the repeating data pattern to the logical address without writing the data to the volatile memory.

[0120] In some implementations, a system includes a volatile memory; and a CXL controller including: a CXL interface; and a controller configured to: receive a command to write data to the volatile memory, wherein the command indicates a logical address associated with the data; compare the data to one or more repeating data patterns to identify whether the data matches a repeating data pattern in the one or more repeating data patterns; and in response to the data matching the repeating data pattern, map a physical address associated with the repeating data pattern to the logical address without writing the data to the volatile memory.

[0121] The foregoing disclosure provides illustration and description, but is not intended to be exhaustive or to limit the embodiments to the precise form disclosed. Modifications and variations may be made in light of the above disclosure or may be acquired from practice of the embodiments described herein.

[0122] Even if specific feature combinations are listed in the claims and / or disclosed in the specification, these combinations are not intended to limit the disclosure of the embodiments described herein. Many of these features can be combined in ways not specifically listed in the claims and / or disclosed in the specification. For example, the present disclosure includes the combination of each dependent claim in a claim set with each other independent claim in that claim set, and each combination of multiple claims in that claim set. As used herein, a phrase referring to "at least one" in a list of items refers to any combination of those items, including single members. As an example, "at least one of a, b, or c:" is intended to cover a, b, c, a+b, a+c, b+c, and a+b+c, as well as any combination with multiple identical elements (e.g., a+a, a+a+a, a+a+b, a+a+c, a+b+b, a+c+c, b+b, b+b+b, b+b+c, c+c, and c+c+c, or any other ordering of a, b, and c).

[0123] When "a component" or "one or more components" (or another element, such as "a controller" or "one or more controllers") is described or claimed (within a single claim or across multiple claims) as performing or being configured to perform multiple operations, such language is intended to broadly encompass a variety of architectures and environments. For example, unless expressly claimed otherwise (e.g., by use of "a first component" and "a second component" or other language that distinguishes components in the claims), such language is intended to encompass a single component that performs or is configured to perform all operations, a group of components that collectively perform or are configured to perform all operations, a first component that performs or is configured to perform a first operation and a second component that performs or is configured to perform a second operation, or any combination of components that performs or is configured to perform operations. For example, when a claim has the form "one or more components configured to: perform X; perform Y; and perform Z," that claim should be interpreted to mean "one or more components configured to perform X; one or more (possibly different) components configured to perform Y; and one or more (possibly different) components configured to perform Z."

[0124] The elements, actions or instructions used herein should not be interpreted as critical or necessary unless explicitly described as such. Moreover, as used herein, the articles "a" and "an" are intended to include one or more items and can be used interchangeably with "one or more". In addition, as used herein, the article "said" is intended to include one or more items quoted in conjunction with the article "said" and can be used interchangeably with "the one or more". When only one item is expected, the phrases "only one", "single" or similar language are used. Moreover, as used herein, the terms "has", "have", "having" or the like are intended to be open terms that do not limit the elements they modify (for example, an element "having" A may also have B). In addition, unless otherwise explicitly stated, the phrase "based on" is intended to mean "based at least in part on". As used herein, the term "multiple" can be replaced with "a plurality of" and vice versa. Also, as used herein, the term "or" when used in a series is intended to be inclusive and used interchangeably with "and / or" unless expressly stated otherwise (e.g., if used in combination with "either" or "only one of").

Claims

1. A system comprising: Volatile memory; and A controller configured to: receiving a command to write data to the volatile memory, wherein the command indicates a logical address associated with the data; comparing the data to one or more repeating data patterns to identify whether the data matches a repeating data pattern in the one or more repeating data patterns; and In response to the data matching the repeating data pattern, mapping a physical address associated with the repeating data pattern to the logical address without writing the data to the volatile memory.

2. The system of claim 1 , wherein the controller is further configured to: deriving the entry address using the data; and retrieving an entry associated with the entry address from a data structure in a local memory of the controller, The entry indicates the repeating data pattern and the physical address.

3. The system of claim 2 , wherein the entry further indicates a reference counter indicating the number of logical addresses mapped to the physical address, and Wherein the controller is further configured to increment the reference counter in response to the data matching the repeating data pattern.

4. The system of claim 1 , wherein the controller is further configured to: deriving an entry address and a data representation using the data; retrieving an entry associated with the entry address from a data structure in a local memory of the controller, wherein the entry indicates a stored data representation and the physical address; comparing the data representation to the stored data representation to identify whether the data representation matches the stored data representation; and In response to the data representation matching the stored data representation, the repeating data pattern is retrieved from the physical address of the volatile memory.

5. The system of claim 4 , wherein the physical address of the volatile memory is associated with a reference counter indicating the number of logical addresses mapped to the physical address, and Wherein the controller is further configured to increment the reference counter in response to the data matching the repeating data pattern.

6. The system of claim 1 , wherein the controller is further configured to: receiving an additional command to read the data from the volatile memory, wherein the command indicates the logical address associated with the data; obtaining the physical address mapped to the logical address by mapping the logical address to the physical address; retrieving an entry address associated with the physical address from a content addressable memory of the controller; Retrieving the entry of the entry address from a data structure in the controller's local memory, wherein the entry indicates a data pattern representing data previously written to the volatile memory; and The data mode is returned in response to the additional command.

7. The system of claim 1 , wherein the controller is further configured to: receiving an additional command to read the data from the volatile memory, wherein the command indicates the logical address associated with the data; obtaining the physical address mapped to the logical address by mapping the logical address to the physical address; retrieving duplicate data from the physical address of the volatile memory; and The duplicate data is returned in response to the additional command.

8. The system of claim 1, wherein the repeating data pattern is a configured data pattern.

9. The system of claim 1 , wherein the controller comprises a content addressable memory and a local memory, wherein the local memory is configured to contain at least one data structure, and Wherein the at least one data structure is configured to include the repeating data pattern.

10. A method comprising: receiving, by a controller of a memory system, a command to write data to a volatile memory of the memory system, wherein the command indicates a logical address associated with the data; retrieving, by the controller, a repeating data pattern using information in a local memory of the controller; comparing, by the controller, the data with the repeating data pattern to identify whether the data matches the repeating data pattern; and A physical address associated with the repeating data pattern is mapped to the logical address by the controller and in response to the data matching the repeating data pattern without writing the data to the volatile memory.

11. The method according to claim 10, further comprising: Use said data to derive the entry address, Wherein retrieving the repeated data pattern comprises: retrieving an entry associated with the entry address from a data structure of the local memory of the controller, The entry indicates the repeating data pattern and the physical address.

12. The method according to claim 10, further comprising: Using the data, derive the entry address and data representation, Wherein retrieving the repeated data pattern comprises: retrieving an entry associated with the entry address from a data structure of the local memory of the controller, wherein the entry indicates a stored data representation and the physical address; comparing the data representation to the stored data representation to identify whether the data representation matches the stored data representation; and In response to the data representation matching the stored data representation, the repeating data pattern is retrieved from the physical address of the volatile memory.

13. The method according to claim 10, further comprising: causing the data to be written to a specific physical address of the volatile memory in response to the data not matching the repeating data pattern; recording an entry indicating the specific physical address and a data pattern representing the data in a data structure of the local memory of the controller, wherein an entry address of the entry is derived using the data; and Association data indicating an association between the specific physical address and the entry address is recorded in a content addressable memory of the controller.

14. The method according to claim 10, further comprising: receiving an additional command to read the data from the volatile memory, wherein the command indicates the logical address associated with the data; obtaining the physical address mapped to the logical address by mapping the logical address to the physical address, wherein the mapping includes a location indicator for the physical address, the location indicator indicating whether the physical address is for the volatile memory or for a data structure of a local memory of the controller; retrieving duplicate data from the physical address of the volatile memory if the location indicator indicates that the physical address is for the volatile memory, or retrieving a configured data pattern from the physical address of the data structure if the location indicator indicates that the physical address is for the data structure; and The repeated data or the configured data pattern is returned in response to the additional command.

15. A system comprising: Volatile memory; and Compute Fast Link CXL controller, which includes: CXL interface; and A controller configured to: receiving a command to write data to the volatile memory, wherein the command indicates a logical address associated with the data; comparing the data to one or more repeating data patterns to identify whether the data matches a repeating data pattern in the one or more repeating data patterns; and In response to the data matching the repeating data pattern, mapping a physical address associated with the repeating data pattern to the logical address without writing the data to the volatile memory.

16. The system of claim 15, wherein the repeating data pattern is stored in a data structure in a local memory of the controller.

17. The system of claim 15, wherein the controller is further configured to: deriving the entry address using the data; and retrieving an entry associated with the entry address from a data structure in a local memory of the controller, The entry indicates the repeating data pattern and the physical address.

18. The system of claim 15, wherein the controller is further configured to: deriving an entry address and a data representation using the data; retrieving an entry associated with the entry address from a data structure in a local memory of the controller, wherein the entry indicates a stored data representation and the physical address; comparing the data representation to the stored data representation to identify whether the data representation matches the stored data representation; and In response to the data representation matching the stored data representation, the repeating data pattern is retrieved from the physical address of the volatile memory.

19. The system of claim 15, wherein the controller is further configured to: In response to the data not matching the repeating data pattern, causing the data to be written to a specific physical address of the volatile memory; and recording an entry in a data structure in a local memory of the controller indicating the particular physical address and the stored data representation of the data, The data is used to derive an entry address of the entry.

20. The system of claim 15, wherein the controller is further configured to: receiving an additional command to read the data from the volatile memory, wherein the command indicates the logical address associated with the data; obtaining the physical address mapped to the logical address by mapping the logical address to the physical address; retrieving duplicate data from the physical address of the volatile memory; and The duplicate data is returned in response to the additional command.

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