A data processing system, method, device, medium and program product

Abstract

The application discloses a data processing system, method, device, medium and program product in the computer technical field. In the application, a host and an acceleration device realize cache synchronization and corresponding message notification through a cache consistency protocol, without passing an interrupt message, so that the data transmission delay between the host and the acceleration device can be reduced, and the data transmission efficiency between the host and the acceleration device can be improved; meanwhile, in combination with a memory direct reading technology, the data transmission between the host and the acceleration device and the data transmission between the third party is accelerated.

Description

Technical Field

[0001] The present application relates to the field of computer technology, and in particular to a data processing system, method, device, medium and program product. Background Art

[0002] Currently, in heterogeneous computing scenarios consisting of a host and an acceleration device, the host and the acceleration device need to frequently send message notifications in an interrupt manner. This method consumes a lot of time, increases the delay of data transmission between the host and the acceleration device, and reduces the efficiency of data transmission between the host and the acceleration device.

[0003] Therefore, how to improve the data transmission efficiency between the host and the acceleration device is a problem that needs to be solved by those skilled in the art. Summary of the Invention

[0004] In view of this, the purpose of this application is to provide a data processing system, method, device, medium and program product to improve the data transmission efficiency between a host and an acceleration device.

[0005] In a first aspect, the present application provides a data processing system, comprising: a host and an acceleration device; the host and the acceleration device are connected via a cache consistency protocol; the acceleration device comprises: a first memory area and a second memory area; the host comprises: a cache area; the acceleration device is configured to: write first data into the second memory area, and record descriptor information of the first data in a receive queue in the first memory area; after the receive queue is updated, synchronize the updated receive queue to the cache area using the cache consistency protocol, so that the host receives the first data according to the receive queue in the cache area; the host is configured to: write second data into the second memory area via the cache consistency protocol, and record descriptor information of the second data in a send queue in the cache area; after the send queue is updated, synchronize the updated send queue to the first memory area using the cache consistency protocol, so that the acceleration device sends the second data according to the send queue in the first memory area.

[0006] In a second aspect, the present application provides a data processing method, which is applied to a data processing system, the data processing system including: a host and an acceleration device; the host and the acceleration device are connected via a cache consistency protocol; the acceleration device includes: a first memory area and a second memory area; the host includes: a cache area; the data processing method includes: the acceleration device writes the first data to the second memory area, and records the descriptor information of the first data in the receive queue in the first memory area; after the receive queue is updated, the updated receive queue is synchronized to the cache area using the cache consistency protocol, so that the host receives the first data according to the receive queue in the cache area; the host writes the second data to the second memory area via the cache consistency protocol, and records the descriptor information of the second data in the send queue in the cache area; after the send queue is updated, the updated send queue is synchronized to the first memory area using the cache consistency protocol, so that the acceleration device sends the second data according to the send queue in the first memory area.

[0007] In a third aspect, the present application provides an electronic device, comprising: a memory for storing a computer program; and a processor for executing the computer program to implement the aforementioned disclosed data processing method.

[0008] In a fourth aspect, the present application provides a non-volatile storage medium for storing a computer program, wherein the computer program implements the aforementioned disclosed data processing method when executed by a processor.

[0009] In a fifth aspect, the present application provides a computer program product, comprising a computer program / instruction, which implements the steps of the aforementioned disclosed data processing method when executed by a processor.

[0010] It can be seen from the above scheme that the present application provides a data processing system, including: a host and an acceleration device; the host and the acceleration device are connected through a cache consistency protocol; the acceleration device includes: a first memory area and a second memory area; the host includes: a cache area; the acceleration device is used to: write the first data to the second memory area, and record the descriptor information of the first data in the receive queue in the first memory area; after the receive queue is updated, the updated receive queue is synchronized to the cache area using the cache consistency protocol, so that the host receives the first data according to the receive queue in the cache area; the host is used to: write the second data to the second memory area through the cache consistency protocol, and record the descriptor information of the second data in the send queue in the cache area; after the send queue is updated, the updated send queue is synchronized to the first memory area using the cache consistency protocol, so that the acceleration device sends the second data according to the send queue in the first memory area.

[0011] It can be seen that the technical effect of this application is: the host and the acceleration device realize cache synchronization and corresponding message notification through the cache consistency protocol, without the need to transmit interrupt messages, which can reduce the data transmission delay between the host and the acceleration device and improve the data transmission efficiency between the host and the acceleration device; at the same time, combined with the direct memory read technology, it accelerates the transmission of data between the host and the acceleration device and the data transmission between the host and the acceleration device and the third party.

[0012] Correspondingly, the data processing method, device, medium and program product provided by this application also have the above-mentioned technical effects. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are merely embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without any creative work.

[0014] Figure 1 A schematic diagram of a data processing system disclosed in this application;

[0015] Figure 2 A schematic diagram of another data processing system disclosed in this application;

[0016] Figure 3 A flow chart of a data processing method disclosed in this application;

[0017] Figure 4 A flow chart of another data processing method disclosed in this application;

[0018] Figure 5 A schematic diagram of an electronic device disclosed in this application;

[0019] Figure 6 A server structure diagram provided for this application;

[0020] Figure 7 This is a terminal structure diagram provided for this application. DETAILED DESCRIPTION

[0021] The following will be combined with the accompanying drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0022] It should be noted that, in the description of this application, the terms "comprises," "includes," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. The terms "first," "second," etc., in this application are used to distinguish similar objects, and are not used to describe a particular order or sequence.

[0023] In order to enable those skilled in the art to better understand the present application, the present application is further described in detail below with reference to the accompanying drawings and specific implementation methods.

[0024] Currently, in heterogeneous computing scenarios consisting of a host and an accelerator, the host and the accelerator need to frequently communicate with each other through interrupts. This method consumes a significant amount of time, increases the latency of data transmission between the host and the accelerator, and reduces the efficiency of data transmission between the host and the accelerator. To address this issue, the present application provides a data processing solution that can improve the efficiency of data transmission between the host and the accelerator.

[0025] See also Figure 1 As shown, an embodiment of the present application discloses a data processing system, comprising: a host and an acceleration device; the host and the acceleration device are connected via a cache coherence protocol. The acceleration device comprises: a first memory area and a second memory area; the host comprises: a cache area. The first memory area and the second memory area in the acceleration device can be directly read and written by the host using the cache coherence protocol; correspondingly, the cache area in the host can be directly read and written by the acceleration device using the cache coherence protocol, thereby improving the data transmission efficiency between the host and the acceleration device.

[0026] In this embodiment, the host and the acceleration device belong to the same target end, and data is sent and received between the target end and the third-party device. That is, both sending and receiving operations are performed by the target end. Specifically, when the host sends data to the third-party device, it uses the acceleration device to send data; when the host receives data from the third-party device, it uses the acceleration device to receive data.

[0027] Specifically, the data receiving process includes: the acceleration device writing the first data sent by the third-party device into the second memory area and recording the descriptor information of the first data in the receive queue in the first memory area; after the receive queue is updated, synchronizing the updated receive queue to the cache area using a cache coherence protocol, so that the host receives the first data according to the receive queue in the cache area. Furthermore, after the host completes processing of the first data (e.g., after sending the first data to the remote end), the host updates the receive completion queue and the receive queue in the cache area accordingly. After the receive completion queue and the receive queue are updated, the updated receive completion queue and the updated receive queue are synchronized to the first memory area using a cache coherence protocol.

[0028] Specifically, the data transmission process includes: the host writes the second data to be transmitted into the second memory area via a cache coherence protocol and records the descriptor information of the second data in a transmit queue in the cache area; after the transmit queue is updated, the updated transmit queue is synchronized to the first memory area using the cache coherence protocol, so that the acceleration device transmits the second data according to the transmit queue in the first memory area. Furthermore, after transmitting the second data, the acceleration device updates the transmit completion queue and transmit queue in the first memory area accordingly; after the transmit completion queue and transmit queue are updated, the updated transmit completion queue and transmit queue are synchronized to the cache area using the cache coherence protocol.

[0029] The cache consistency protocol is specifically the CXL protocol. The CXL protocol ensures compatibility and interoperability with PCIe by utilizing the physical layer of PCIe, allowing devices to efficiently process shared data and support the expansion of memory bandwidth and capacity. The CXL protocol includes: CXL.io: responsible for traditional I / O communication, compatible with existing PCIe devices. CXL.cache: provides cache support for acceleration devices and memory. CXL.memory: provides low-latency direct communication between the host and memory. In one embodiment, the first memory area supports the cache access protocol (such as CXL.cache), and the second memory area supports the memory access protocol (such as CXL.mem). Accordingly, the acceleration device also includes: a cache consistency management module; the cache consistency management module is connected to the first memory area through the cache access protocol; the cache consistency management module is connected to the second memory area through the memory access protocol.

[0030] Accordingly, the acceleration device is configured to utilize the cache coherence management module to send a queue update message to the host based on the cache access protocol, so that the host completes synchronization of the updated receive queue according to the queue update message. Accordingly, the host is configured to utilize the cache coherence management module to send a queue update message to the acceleration device based on the memory access protocol, so that the acceleration device completes synchronization of the updated transmit queue according to the queue update message.

[0031] In one embodiment, a host is configured to: read descriptor information of first data from a receive queue in a polling manner; read the first data from a second memory area using a cache coherence protocol based on the read descriptor information; parse the first data and determine the destination of the first data; and send the first data to the destination (i.e., a third-party device). After sending the first data to the destination, the receive queue is updated accordingly. If multiple pieces of first data are relatively small, the host may combine them and send them. In one embodiment, the host is configured to: combine multiple pieces of first data to generate a combined packet; and send the combined packet to the destination.

[0032] In one embodiment, the acceleration device is configured to: read descriptor information of second data from a transmit queue in a polling manner; read the second data from a second memory area based on the read descriptor information; parse the second data and determine a destination of the second data; and transmit the second data to the destination. After transmitting the second data to the destination, the transmit queue is updated accordingly.

[0033] In one embodiment, the acceleration device further includes: a receiving buffer area ( Figure 2 RX) and transmit buffer ( Figure 2 The receiving buffer area is used to temporarily store the first data before writing the first data into the second memory area; the sending buffer area is used to temporarily store the second data after reading the second data from the second memory area and before sending the second data.

[0034] In this embodiment, the host and the acceleration device implement cache synchronization and corresponding message notifications through a cache consistency protocol without the need to transmit interrupt messages, which can reduce the data transmission delay between the host and the acceleration device and improve the data transmission efficiency between the host and the acceleration device; at the same time, combined with the direct memory read technology, it accelerates the transmission of data between the host and the acceleration device and the data transmission between the host and the acceleration device and the third party.

[0035] See Figure 2Another data processing system includes a host and an FPGA board (i.e., an accelerator). The FPGA board includes a first memory area, mem1, a second memory area, mem2, and a CXL.HDM module (CXL management module). By configuring the CXL.HDM module on the FPGA, mem2 is set as the host's extended memory based on the CXL.mem protocol. By configuring the CXL.HDM module on the FPGA, mem1 is set as the host's cacheable extended memory based on the CXL.cache protocol. Furthermore, within the device memory space of mem1, queues (transmit queue TXQ, receive queue RXQ, receive completion queue RXCQ, and transmit completion queue TXCQ) are initialized. These queues are synchronized to the host's cache based on the CXL.cache protocol. Storage space for transmit data (data2) and receive data (data1) is initialized within the memory space of mem2.

[0036] In one example, the data sending process includes:

[0037] 1. User space to kernel protocol stack: The user program calls the send() system call, and the data is copied from the user space buffer to the kernel space sk_buff object via copy_from_user(). The protocol stack encapsulates the data packet layer by layer according to the TCP / IP model, adding the TCP header, IP header, MAC header, etc., to finally generate a network frame.

[0038] 2. Descriptor Write: The host writes the generated network frame directly to the data2 address of mem2 in the FPGA board's memory using CXL.mem. The host writes the descriptor to the TXQ (Transmit Ring Queue), which is shared by the kernel and the network card, and moves the queue pointer backward. The queue manages free and used descriptors using the next_to_use and next_to_clean pointers. The TXQ queue is stored in a coherent memory address between the host and FPGA caches. When the content changes, the CXL module, based on the CXL.cache protocol, notifies the FPGA's TX module to transmit the data.

[0039] 3. FPGA sends data: When the host program moves the pointer to update the TXQ queue, the CXL module triggers a TXQ change notification message (msg) based on the CXL.cache protocol to inform the FPGA. Upon receiving the TXQ queue update message (msg), the FPGA sends data2 to the local TX cache queue (i.e., the transmit buffer) and transmits it through the physical layer.

[0040] 4. Completion Queue (CQ) Notification: After the FPGA completes data transmission, it updates the TXCQ queue. The TXCQ queue is stored in a coherent memory address between the host and FPGA caches. When its contents change, the CXL module, based on the CXL.cache protocol, sends a notification message (msg) to the host. Upon receiving the TXCQ queue change notification, the host triggers an event handler, which in turn calls netif_schedule() to trigger a soft interrupt (NET_TX_SOFTIRQ). The soft interrupt handler (such as net_tx_action()) cleans up the transmitted descriptors, frees the sk_buff memory, and updates the local queue pointer.

[0041] 5. Resource Release: The sent descriptor is marked as free, and the sk_buff data space is reclaimed from the memory pool (e.g., kfree_skb()). As can be seen, after the FPGA sends data, the send completion queue and the send queue are updated accordingly in the first memory area. After the send completion queue and the send queue are updated, the cache coherence protocol is used to synchronize the updated send completion queue and the updated send queue to the host's cache area. This ensures timely synchronization between the send completion queue and the send queue between the host cache and the FPGA's first memory area.

[0042] In one example, the data receiving process includes:

[0043] 1. Data Frame Reception and RXQ Writing: The FPGA receives data frames through the physical interface and stores them in the internal RX cache. After verifying the MAC address, it writes the data frame directly to the local memory area pointed to by the kernel's pre-allocated RXQ descriptor (where data1 resides). Each descriptor contains the physical address and length of the memory area where the data resides. After filling the data, the FPGA updates the descriptor status and the RXQ and RXCQ queue pointers. The RXQ queue is stored at a coherent memory address between the host and FPGA caches. When the content changes, the CXL module sends a notification message (msg) to the host based on the CXL.cache protocol.

[0044] 2. Soft interrupt processing: After the FPGA updates RXQ and RXCQ, the host receives a queue update notification (msg) based on the CXL.cache protocol. The CPU calls the event handler, which triggers a soft interrupt (NET_RX_SOFTIRQ). The soft interrupt handler function net_rx_action() reads batch descriptors from RXQ through polling, encapsulates the data into sk_buff, and submits it to the protocol stack.

[0045] 3. Protocol stack processing and user notification: The protocol stack parses the data packet (stripping the MAC header, IP header, and TCP header), finds the corresponding socket (used for third-party communication) based on the destination port number, and stores the data in the socket receive queue. The user program reads the data from the socket buffer using the recv() system call, and the kernel wakes up the blocked process using wake_up_interruptible().

[0046] 4. Descriptor Recycling and Memory Management: Processed RX descriptors are repopulated with new DMA buffer addresses (available memory addresses), and the receive queue pointer is updated for the next round of data reception. Furthermore, if Generic Receive Offload (GRO) is enabled, the protocol stack will merge multiple packets (for socket transmission) to reduce processing overhead. As can be seen, after the host sends the first data to the third party, it updates the receive completion queue and receive queue in the host cache accordingly. After the receive completion queue and receive queue are updated, the cache coherence protocol is used to synchronize the updated receive completion queue and receive queue in the host cache to the first memory area. This ensures timely synchronization of the receive completion queue and receive queue between the host cache and the FPGA's first memory area.

[0047] It can be seen that this embodiment expands the host memory through the CXL.mem protocol, and stores the data of the network sending data frame and the data of the network receiving data frame in the extended memory on the FPGA board. In addition, the designated memory location on the FPGA board is demarcated based on the CXL.cache protocol, and the TXQ queue RXQ queue TXCQ queue RXCQ queue is configured in this area. Based on CXL.cache, the host automatically synchronizes the content message of TXQ to the FPGA. Subsequently, the FPGA can obtain the address of the data frame to be sent from TXQ, find the location of the corresponding data frame to send data. Based on CXL.cache, after the FPGA receives the network data and updates the RXQ queue, the corresponding update will be automatically synchronized to the host cache. The host obtains the data frame address based on this and reads the corresponding data frame in the extended memory. It can be seen that the host and the FPGA board do not need to exchange messages through reading and writing registers, but instead use the CXL.cache protocol to achieve queue synchronization updates.

[0048] The following introduces a data processing method provided in an embodiment of the present application. The data processing method described below can be referenced with other embodiments described in this document.

[0049] An embodiment of the present application provides a data processing method, which is applied to a data processing system, wherein the data processing system includes: a host and an acceleration device; the host and the acceleration device are connected via a cache consistency protocol; the acceleration device includes: a first memory area and a second memory area; and the host includes: a cache area.

[0050] See also Figure 3 As shown, the data processing method disclosed in the embodiment of the present application includes:

[0051] S301, the acceleration device writes first data into the second memory area, and records the descriptor information of the first data in the receiving queue in the first memory area; after the receiving queue is updated, the updated receiving queue is synchronized to the cache area using the cache consistency protocol.

[0052] S302: The host receives first data according to a receiving queue in the buffer area.

[0053] See also Figure 4 As shown, the data processing method disclosed in the embodiment of the present application includes:

[0054] S401. The host writes the second data into the second memory area through the cache consistency protocol, and records the descriptor information of the second data in the sending queue in the cache area; after the sending queue is updated, the updated sending queue is synchronized to the first memory area using the cache consistency protocol.

[0055] S402: The acceleration device sends second data according to the sending queue in the first memory area.

[0056] In one embodiment, the first memory area supports a cache access protocol (e.g., CXL.cache), and the second memory area supports a memory access protocol (e.g., CXL.mem). Accordingly, the acceleration device further includes a cache coherence management module; the cache coherence management module connects to the first memory area via the cache access protocol; and the cache coherence management module connects to the second memory area via the memory access protocol.

[0057] In one embodiment, the acceleration device is configured to: utilize the cache coherence management module to send a queue update message to the host based on the cache access protocol, so that the host completes synchronization of the updated receiving queue according to the queue update message.

[0058] In one embodiment, the host is configured to: utilize the cache coherence management module to send a queue update message to the acceleration device based on the memory access protocol, so that the acceleration device completes synchronization of the updated sending queue according to the queue update message.

[0059] In one embodiment, the host is used to: read the descriptor information of the first data from the receiving queue in a polling manner; read the first data from the second memory area using a cache consistency protocol based on the read descriptor information; parse the first data and determine the destination of the first data; and send the first data to the destination.

[0060] In one embodiment, the host is configured to: after sending the first data to the destination end, update the receiving queue accordingly.

[0061] In one embodiment, the host is configured to: merge multiple first data to obtain a merged packet; and send the merged packet to a destination end.

[0062] In one embodiment, the acceleration device is used to: read the descriptor information of the second data from the sending queue in a polling manner; read the second data from the second memory area according to the read descriptor information; parse the second data and determine the destination of the second data; and send the second data to the destination.

[0063] In one embodiment, the acceleration device is configured to: after sending the second data to the destination end, update the sending queue accordingly.

[0064] In one embodiment, the acceleration device further includes: a receiving buffer and a sending buffer; the receiving buffer is used to temporarily store the first data before writing the first data into the second memory area; the sending buffer is used to temporarily store the second data after reading the second data from the second memory area and before sending the second data.

[0065] Among them, for more specific working processes of each module and unit in this embodiment, reference can be made to the corresponding contents disclosed in the aforementioned embodiments, which will not be repeated here.

[0066] In this embodiment, the host and the acceleration device implement cache synchronization and corresponding message notifications through a cache consistency protocol without the need to transmit interrupt messages, which can reduce the data transmission delay between the host and the acceleration device and improve the data transmission efficiency between the host and the acceleration device; at the same time, combined with the direct memory read technology, it accelerates the transmission of data between the host and the acceleration device and the data transmission between the host and the acceleration device and the third party.

[0067] An electronic device provided in an embodiment of the present application is introduced below. The electronic device described below can be referenced with other embodiments described herein.

[0068] See also Figure 5 As shown, an embodiment of the present application discloses an electronic device, including: a memory 501 for storing a computer program; a processor 502 for executing the computer program to implement the method disclosed in any of the above embodiments.

[0069] In this embodiment, when the processor executes the computer program stored in the memory, it can specifically implement the following steps: write the first data into the second memory area, and record the descriptor information of the first data in the receiving queue in the first memory area; after the receiving queue is updated, synchronize the updated receiving queue to the cache area using the cache consistency protocol.

[0070] In this embodiment, when the processor executes the computer program stored in the memory, the following steps may be specifically implemented: receiving first data according to a receiving queue in a buffer area.

[0071] In this embodiment, when the processor executes the computer program stored in the memory, it can specifically implement the following steps: write the second data into the second memory area through the cache consistency protocol, and record the descriptor information of the second data in the sending queue in the cache area; after the sending queue is updated, synchronize the updated sending queue to the first memory area using the cache consistency protocol.

[0072] In this embodiment, when the processor executes the computer program stored in the memory, the following steps may be specifically implemented: the acceleration device sends the second data according to the sending queue in the first memory area.

[0073] In this embodiment, when the processor executes the computer program stored in the memory, it can specifically implement the following steps: using the cache consistency management module based on the CXL.cache protocol to send a queue update message to the host, so that the host completes the synchronization of the updated receiving queue according to the queue update message.

[0074] In this embodiment, when the processor executes the computer program stored in the memory, it can specifically implement the following steps: using the cache consistency management module based on the CXL.mem protocol to send a queue update message to the acceleration device, so that the acceleration device completes the synchronization of the updated sending queue according to the queue update message.

[0075] In this embodiment, when the processor executes the computer program stored in the memory, it can specifically implement the following steps: read the descriptor information of the first data from the receiving queue in a polling manner; read the first data from the second memory area using a cache consistency protocol based on the read descriptor information; parse the first data and determine the destination of the first data; and send the first data to the destination.

[0076] In this embodiment, when the processor executes the computer program stored in the memory, the following steps may be specifically implemented: after sending the first data to the destination end, updating the receiving queue accordingly.

[0077] In this embodiment, when the processor executes the computer program stored in the memory, the following steps may be specifically implemented: merging multiple first data to obtain a merged package; and sending the merged package to a destination end.

[0078] In this embodiment, when the processor executes the computer program stored in the memory, it can specifically implement the following steps: read the descriptor information of the second data from the sending queue in a polling manner; read the second data from the second memory area according to the read descriptor information; parse the second data and determine the destination of the second data; and send the second data to the destination.

[0079] In this embodiment, when the processor executes the computer program stored in the memory, the following steps may be specifically implemented: after sending the second data to the destination end, updating the sending queue accordingly.

[0080] Furthermore, the embodiment of the present application also provides an electronic device. The electronic device can be Figure 6 The server shown can also be Figure 7 The terminal shown. Figure 6 and Figure 7 Each of the diagrams is a structural diagram of an electronic device according to an exemplary embodiment, and the contents in the diagrams cannot be considered as any limitation on the scope of use of the present application.

[0081] Figure 6 This is a schematic diagram of the structure of a server provided in an embodiment of the present application. The server may specifically include: at least one processor, at least one memory, a power supply, a communication interface, an input / output interface, and a communication bus. The memory is used to store a computer program, which is loaded and executed by the processor to implement the relevant steps of the data processing disclosed in any of the aforementioned embodiments.

[0082] In this embodiment, the power supply is used to provide operating voltage for each hardware device on the server; the communication interface can create a data transmission channel between the server and external devices. The communication protocol it follows is any communication protocol that can be applied to the technical solution of this application and is not specifically limited here; the input and output interface is used to obtain external input data or output data to the outside world. The specific interface type can be selected according to specific application needs and is not specifically limited here.

[0083] In addition, the memory as a carrier for resource storage can be a read-only memory, random access memory, disk or CD, etc. The resources stored thereon include operating system, computer programs and data, etc. The storage method can be temporary storage or permanent storage.

[0084] The operating system is used to manage and control the hardware devices and computer programs on the server, enabling the processor to operate and process data in the memory. It can be Windows Server, NetWare, Unix, Linux, etc. In addition to computer programs capable of performing the data processing methods disclosed in any of the aforementioned embodiments, computer programs can also include computer programs capable of performing other specific tasks. Data can include data such as application update information and other data such as application developer information.

[0085] Figure 7 This is a schematic diagram of the structure of a terminal provided in an embodiment of the present application. The terminal may specifically include but is not limited to a smartphone, tablet computer, laptop computer or desktop computer.

[0086] Generally, the terminal in this embodiment includes: a processor and a memory.

[0087] The processor may include one or more processing cores, such as a quad-core processor or an octa-core processor. The processor may be implemented in at least one of the following hardware forms: a DSP (Digital Signal Processing), an FPGA (Field-Programmable Gate Array), or a PLA (Programmable Logic Array). The processor may also include a main processor and a coprocessor. The main processor is used to process data in the awake state, also known as a CPU (Central Processing Unit); the coprocessor is a low-power processor used to process data in the standby state. In some embodiments, the processor may be integrated with a GPU (Graphics Processing Unit), which is responsible for rendering and drawing content required to be displayed on the display. In some embodiments, the processor may also include an AI (Artificial Intelligence) processor, which is used to handle computational operations related to machine learning.

[0088] The memory may include one or more computer non-volatile storage media, which may be non-transitory. The memory may also include high-speed random access memory, and non-volatile memory, such as one or more disk storage devices, flash memory storage devices. In this embodiment, the memory is used to store at least the following computer program, wherein, after the computer program is loaded and executed by the processor, it can implement the relevant steps in the data processing method performed by the terminal side disclosed in any of the aforementioned embodiments. In addition, the resources stored in the memory may also include an operating system and data, etc., and the storage method may be temporary storage or permanent storage. Among them, the operating system may include Windows, Unix, Linux, etc. The data may include but is not limited to update information of the application.

[0089] In some embodiments, the terminal may further include a display screen, an input and output interface, a communication interface, a sensor, a power supply, and a communication bus.

[0090] Those skilled in the art will understand that Figure 7 The structure shown in the figure does not constitute a limitation to the terminal, and may include more or fewer components than shown in the figure.

[0091] A non-volatile storage medium provided in an embodiment of the present application is introduced below. The non-volatile storage medium described below can be referenced with other embodiments described herein.

[0092] A non-volatile storage medium for storing a computer program, wherein the computer program, when executed by a processor, implements the data processing method disclosed in the aforementioned embodiment. The non-volatile storage medium is a computer-readable non-volatile storage medium that, as a carrier for resource storage, may be a read-only memory, random access memory, a magnetic disk, or an optical disk. The resources stored thereon include an operating system, a computer program, and data, and the storage method may be either temporary or permanent.

[0093] In this embodiment, when the processor executes a computer program stored in a non-volatile storage medium, the following steps can be specifically implemented: first data is written into the second memory area, and descriptor information of the first data is recorded in the receiving queue in the first memory area; after the receiving queue is updated, the updated receiving queue is synchronized to the cache area using the cache consistency protocol.

[0094] In this embodiment, when the processor executes the computer program stored in the non-volatile storage medium, the following steps may be specifically implemented: receiving first data according to a receiving queue in the buffer area.

[0095] In this embodiment, when the processor executes a computer program stored in a non-volatile storage medium, it can specifically implement the following steps: write the second data into the second memory area through a cache consistency protocol, and record the descriptor information of the second data in the sending queue in the cache area; after the sending queue is updated, synchronize the updated sending queue to the first memory area using the cache consistency protocol.

[0096] In this embodiment, when the processor executes the computer program stored in the non-volatile storage medium, the following steps may be specifically implemented: the acceleration device sends the second data according to the sending queue in the first memory area.

[0097] In this embodiment, when the processor executes the computer program stored in the non-volatile storage medium, it can specifically implement the following steps: using the cache consistency management module based on the CXL.cache protocol to send a queue update message to the host, so that the host completes the synchronization of the updated receiving queue according to the queue update message.

[0098] In this embodiment, when the processor executes a computer program stored in a non-volatile storage medium, the following steps can be specifically implemented: using the cache consistency management module based on the CXL.mem protocol to send a queue update message to the acceleration device, so that the acceleration device completes the synchronization of the updated sending queue according to the queue update message.

[0099] In this embodiment, when the processor executes a computer program stored in a non-volatile storage medium, it can specifically implement the following steps: read the descriptor information of the first data from the receiving queue in a polling manner; read the first data from the second memory area using a cache consistency protocol based on the read descriptor information; parse the first data and determine the destination of the first data; and send the first data to the destination.

[0100] In this embodiment, when the processor executes the computer program stored in the non-volatile storage medium, the following steps may be specifically implemented: after sending the first data to the destination end, updating the receiving queue accordingly.

[0101] In this embodiment, when the processor executes the computer program stored in the non-volatile storage medium, the following steps may be specifically implemented: merging multiple first data to obtain a merged package; and sending the merged package to the destination end.

[0102] In this embodiment, when the processor executes a computer program stored in a non-volatile storage medium, it can specifically implement the following steps: read the descriptor information of the second data from the sending queue in a polling manner; read the second data from the second memory area according to the read descriptor information; parse the second data and determine the destination of the second data; and send the second data to the destination.

[0103] In this embodiment, when the processor executes the computer program stored in the non-volatile storage medium, the following steps may be specifically implemented: after sending the second data to the destination end, updating the sending queue accordingly.

[0104] A computer program product provided in an embodiment of the present application is introduced below. The computer program product described below can be referenced with other embodiments described herein.

[0105] A computer program product comprises a computer program / instruction, which implements the steps of the aforementioned data processing method when executed by a processor.

[0106] An embodiment of the present application further provides another computer program product, including a non-volatile computer-readable storage medium, wherein the non-volatile computer-readable storage medium is used to store a computer program, and when the computer program is executed by a processor, the steps in any of the above embodiments are implemented.

[0107] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0108] The steps of the methods or algorithms described in conjunction with the embodiments disclosed herein may be implemented directly using hardware, a software module executed by a processor, or a combination of the two. The software module may be placed in random access memory (RAM), internal memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, a hard disk, a removable disk, a CD-ROM, or any other form of non-volatile storage medium known in the art.

[0109] This document uses specific examples to illustrate the principles and implementation methods of this application. The description of the above embodiments is only used to help understand the method and core ideas of this application. At the same time, for those skilled in the art, based on the ideas of this application, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as limiting this application.

Claims

1. A data processing system, characterized in that: include: Host and acceleration device; The host and the acceleration device are connected via a cache coherence protocol; The acceleration device includes: a first memory area and a second memory area; the host includes: a cache area; The acceleration device is configured to: write the first data into the second memory area, and record descriptor information of the first data in a receive queue in the first memory area; after the receive queue is updated, synchronize the updated receive queue to the cache area using the cache coherence protocol, so that the host receives the first data according to the receive queue in the cache area; The host is configured to: write second data into the second memory area through the cache coherence protocol, and record descriptor information of the second data in a send queue in the cache area; after the send queue is updated, synchronize the updated send queue to the first memory area using the cache coherence protocol, so that the acceleration device sends the second data according to the send queue in the first memory area; The acceleration device is configured to: after sending the second data, update the sending completion queue and the sending queue in the first memory area accordingly; after the sending completion queue and the sending queue are updated, synchronize the updated sending completion queue and the updated sending queue to the cache area using the cache consistency protocol; Correspondingly, the host is used to: after the first data processing is completed, update the receive completion queue and the receive queue accordingly in the cache area; after the receive completion queue and the receive queue are updated, use the cache consistency protocol to synchronize the updated receive completion queue and the updated receive queue to the first memory area.

2. The system according to claim 1, wherein: The first memory area supports a cache access protocol, and the second memory area supports a memory access protocol; Correspondingly, the acceleration device further includes: a cache consistency management module; the cache consistency management module is connected to the first memory area through the cache access protocol; the cache consistency management module is connected to the second memory area through the memory access protocol.

3. The system according to claim 2, characterized in that The acceleration device is used to: utilize the cache consistency management module to send a queue update message to the host based on the cache access protocol, so that the host completes synchronization of the updated receiving queue according to the queue update message.

4. The system according to claim 2, wherein: The host is configured to: utilize the cache consistency management module to send a queue update message to the acceleration device based on the memory access protocol, so that the acceleration device completes synchronization of the updated sending queue according to the queue update message.

5. The system according to claim 1, wherein: The host is configured to: read the descriptor information of the first data from the receiving queue in a polling manner; and read the first data from the second memory area using the cache coherence protocol according to the read descriptor information; parsing the first data and determining a destination of the first data; The first data is sent to a destination end.

6. The system according to claim 5, characterized in that The host is configured to: after sending the first data to the destination end, update the receiving queue accordingly.

7. The system according to claim 5, characterized in that The host is configured to: merge a plurality of first data to obtain a merged packet; and send the merged packet to a destination end.

8. The system according to claim 1, wherein: The acceleration device is used to: read the descriptor information of the second data from the sending queue in a polling manner; and read the second data from the second memory area according to the read descriptor information; parsing the second data and determining a destination of the second data; The second data is sent to the destination end.

9. The system according to claim 8, characterized in that The acceleration device is configured to: after sending the second data to the destination end, update the sending queue accordingly.

10. The system according to any one of claims 1 to 9, characterized in that The acceleration device also includes: a receiving buffer area and a sending buffer area; The receiving buffer area is used to temporarily store the first data before writing the first data into the second memory area; The sending buffer area is used to temporarily store the second data after reading the second data from the second memory area and before sending the second data.

11. A data processing method, characterized in that: Applied to a data processing system, the data processing system includes: a host and an acceleration device; the host and the acceleration device are connected via a cache consistency protocol; the acceleration device includes: a first memory area and a second memory area; the host includes: a cache area; The data processing method includes: The acceleration device writes the first data into the second memory area and records the descriptor information of the first data in the receive queue in the first memory area; after the receive queue is updated, the updated receive queue is synchronized to the cache area using the cache coherence protocol, so that the host receives the first data according to the receive queue in the cache area; The host writes the second data into the second memory area through the cache coherence protocol and records the descriptor information of the second data in a send queue in the cache area; after the send queue is updated, the host synchronizes the updated send queue to the first memory area using the cache coherence protocol, so that the acceleration device sends the second data according to the send queue in the first memory area; After sending the second data, the acceleration device updates the sending completion queue and the sending queue in the first memory area accordingly, and after the sending completion queue and the sending queue are updated, synchronizes the updated sending completion queue and the updated sending queue to the cache area using the cache consistency protocol; Correspondingly, after the first data processing is completed, the host updates the receive completion queue and the receive queue in the cache area accordingly. After the receive completion queue and the receive queue are updated, the cache consistency protocol is used to synchronize the updated receive completion queue and the updated receive queue to the first memory area.

12. An electronic device, characterized in that: include: memory for storing computer programs; A processor, configured to execute the computer program to implement the method according to claim 11.

13. A non-volatile storage medium, characterized in that: Used for storing a computer program, wherein the computer program implements the method according to claim 11 when executed by a processor.

14. A computer program product comprising a computer program / instructions, characterized in that When the computer program / instructions are executed by a processor, the method of claim 11 is implemented.

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