A high-efficiency bridging device and data recovery method

Abstract

The present invention relates to an efficient bridging device and a data recovery method, wherein the bridging device comprises: a protocol conversion engine; a read / write channel arbitration unit; a HyperBus read timing control unit; an edge-driven data recovery module: wherein the edge detection unit uses a 3x oversampling technique to perform edge detection on the HyperBus RWDS signal, uses the next sampling point of the transition edge as the valid data bit, and outputs it to the data shaping unit; and a cross-clock domain synchronization unit. The data recovery method comprises: oversampling, edge positioning, data extraction, and dynamic shaping. The bridge and data recovery scheme of the present invention eliminates the traditional delay calibration step; the RWDS signal jitter tolerance is ≥0.4 UI, and the bit error rate is ≤10 at -40°C to 125°C. ‑12 As a DDR alternative, its standby power consumption is ≤50mW and cache expansion delay is ≤100ns.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuit design, and in particular to an efficient bridging device for connecting AXI4 and HyperBus and a data recovery method. Background Art

[0002] Advanced eXtensible Interface 4 (AXI4) launched by ARM is the current mainstream high-performance on-chip interconnect bus protocol, widely used in SoC (System-on-Chip) and high-performance computing fields.

[0003] At the same time, Hyperbus is a high-performance, low-pin-count storage bus protocol developed by Cypress Semiconductor, optimized for fast storage access.

[0004] AXI4 and Hyperbus excel in their respective fields. However, modern complex systems often require the simultaneous integration of high-performance computing units (AXI4 interfaces) and high-speed storage devices (Hyperbus interfaces). This leads to the following technical contradictions that need to be resolved urgently:

[0005] Protocol compatibility issues: AXI4 uses independent address / data channels and a complex flow control mechanism, while Hyperbus relies on address multiplexing and shared control signals. The two have significant differences in timing models, data transmission methods, and electrical characteristics. Direct interconnection requires complex protocol conversion logic.

[0006] System performance bottleneck: In traditional designs, AXI4 master devices connect to Hyperbus storage devices through general-purpose parallel interfaces (such as GPIO), requiring the software layer to participate in protocol conversion. This results in reduced data throughput (usually less than 60% of the theoretical Hyperbus bandwidth) and insufficient real-time performance.

[0007] Heterogeneous system integration requirements: In scenarios such as intelligent driving, edge computing, and industrial automation, high-performance processors (AXI4 architecture) need to directly access high-speed Hyperbus storage devices (such as HyperFlash) for data caching, firmware upgrades, or real-time data acquisition. Traditional interface solutions cannot meet the requirements of low latency and high reliability.

[0008] Therefore, developing an efficient, low-latency AXI4-Hyperbus protocol conversion bridge is not only the key to resolving the above-mentioned technical contradictions, but also an inevitable requirement for promoting the deep integration of high-performance computing and high-speed storage technologies.

[0009] Therefore, there is an urgent need to propose an AXI4-Hyperbus protocol conversion bridge based on hardware logic. Through protocol mapping, timing adaptation, and data caching mechanisms, seamless interoperability between the two protocols can be achieved. Subsequent technical solutions will focus on protocol matching between AXI4 and HyperBus, as well as high-reliability data recovery technology. Summary of the Invention

[0010] To address the above technical issues, the present invention provides a high-efficiency bridging device for connecting AXI4 and HyperBus. The high-efficiency bridging device employs edge detection instead of center sampling, replacing the DDR controller, reducing system standby power consumption by 80% to ≤50mW. As a CPU external cache, the device offers access latency of ≤100ns and costs 50% less than an SRAM solution. The device comprises:

[0011] Protocol conversion engine: The input end is connected to the read and write channels of the AXI4 master device, and the output end is connected to the read and write channel arbitration unit, which is used to convert AXI4 variable bursts into HyperBus fixed bursts;

[0012] The protocol conversion engine further implements: address wraparound mapping of AXI4's WRAP burst type to HyperBus fixed burst; splitting AXI4 unaligned access into multiple 8-bit operations of HyperBus, and the splitting logic satisfies: the unaligned address offset Δ triggers an additional 8-bit transmission.

[0013] Read / write channel arbitration unit: The input end is connected to the protocol conversion engine, and the output end is connected to the HyperBus write timing control unit and the HyperBus read timing control unit respectively, using a polling mechanism to distribute concurrent requests;

[0014] HyperBus read timing control unit: The input end is connected to the read / write channel arbitration unit, and the output end is connected to the IO switching unit. It has an internal integrated edge-driven data recovery module.

[0015] Edge-driven data recovery module: The input receives the HyperBus RWDS signal and DQ data, and the output is connected to the cross-clock domain synchronization unit through the data shaping unit. The edge detection unit uses 3x oversampling technology to detect the edge of the HyperBus RWDS signal, uses the next sampling point of the transition edge as the data valid bit, and outputs it to the data shaping unit.

[0016] The cross-clock synchronization unit consists of an asynchronous FIFO and cross-clock synchronization logic. In the read channel, one of the two ports of the asynchronous FIFO is connected to the data shaping unit and the other to the AXI4 read data channel. In the write channel, the two ports of the asynchronous FIFO are connected to the AXI4 write channel and the HyperBus write timing control unit, respectively. The cross-clock synchronization logic is used to synchronize single-bit handshake information and multi-bit control information.

[0017] The protocol conversion engine includes a WRAP burst optimization module that maps the WRAP burst of AXI4 to a fixed 64-byte burst of HyperBus. The address wrapping algorithm satisfies:

[0018] HyperBus_addr = (AXI4_start_addr & ~0x3F) + ((AXI4_addr + offset) %64)

[0019] The offset is the offset within the burst.

[0020] In one embodiment of the present invention, the edge-driven data recovery module includes: an edge detection unit that receives the HyperBus RWDS signal, performs 3x oversampling, and outputs the transition edge position; a sampling point selection unit whose input is connected to the edge detection unit and extracts valid bits from the DQ data stream based on the transition edge position; and a data shaping unit whose input is connected to the sampling point selection unit and concatenates 16-bit data blocks according to data_cnt and temp_valid. Specifically, the 8 / 16-bit data blocks are concatenated according to priority rules based on the number of edges (data_cnt) and the temporary storage status (temp_valid) to generate a continuous AXI4 data stream.

[0021] The edge detection unit contains a 6-bit shift register. Its sampling sequence is reduced to 18 valid states after removing repeated values, including:

[0022] 000000, 000001, 000011, 000111, 000110, 001111, 001100, 011100,011110,

[0023] 011000, 111000, 111100, 110000, 111001, 100001, 110011, 100111,100000.

[0024] In one embodiment of the present invention, the data shaping unit performs: receiving the data bits and corresponding edge number data_cnt output by the sampling point selector; combining the temporary storage state temp_valid, splicing 16-bit data blocks according to preset priority rules; and outputting the spliced ​​data to the asynchronous FIFO write port.

[0025] In one embodiment of the present invention, the input end of the HyperBus write timing control unit is connected to the read-write channel arbitration unit to receive the AXI4 write data and STRB signal; the output end is connected to the IO switching unit to convert the STRB signal into the RWDS timing of HyperBus; and the write data synchronization from CLK_SRC to CLK_DST is realized through the asynchronous FIFO.

[0026] In one embodiment of the present invention, the cross-clock domain synchronization unit includes: an instruction synchronization channel, which transmits control bytes through the REQ / ACK handshake mechanism; a data synchronization channel, which synchronizes write data to CLK_DST via an asynchronous FIFO and read data to CLK_SRC via an asynchronous FIFO.

[0027] In one embodiment of the present invention, the edge-driven data recovery module is connected to the HyperBus read timing control unit via a parallel bus, and its input signals are: RWDS, DQ[7:0], HCLK; and its output signals are: recovered data [15:0], data valid flag.

[0028] The present invention also provides a HyperBus data recovery method, comprising the following steps:

[0029] Step S1: Oversampling, sampling the RWDS signal at 3 times the HyperBus clock frequency to generate a 6-bit sequence;

[0030] Step S2: Edge positioning, performing an XOR operation on the continuous 6-bit sequence to identify the valid transition edge;

[0031] Step S3: Data extraction, taking the next sampling point of the first valid transition edge as the DQ data valid bit;

[0032] Step S4: Dynamic shaping: splicing 16-bit data blocks according to the priority rules based on the edge number data_cnt and the temporary storage state temp_valid.

[0033] The method completely omits the delay calibration step, and the bit error rate is ≤10 under the following conditions -12; Temperature range: -40℃ to 125℃; Supply voltage fluctuation: ±5%; RWDS signal jitter tolerance ≥ 0.4 UI (Unit Interval); Edge detection logic ≤ 500 gates, Dynamic shaping state machine ≤ 0.05mm² (based on 28nm process).

[0034] The priority rules in step S4 include: when data_cnt = 2 and temp_valid = 2'b01: send the first 16 bits (temporarily stored 8 bits + the first 8 bits of the current cycle); temporarily store the remaining 8 bits of the current cycle;

[0035] When data_cnt = 3 and temp_valid = 2'b00: send the first 16 bits; temporarily store the remaining 8 bits.

[0036] In one embodiment of the present invention, a 6-bit shift register is used in step S1 to sample three times each at the rising edge and the falling edge of the HyperBus clock.

[0037] In one embodiment of the present invention, step S2 further includes: filtering illegal sequences containing two consecutive transition edges or a total transition number greater than 3; and reducing the 6-bit XOR result sequence to 12 valid states.

[0038] The above technical solution of the present invention has the following advantages over the prior art:

[0039] 1. Provide efficient AXI4-HyperBus protocol conversion mechanism

[0040] To address the gap between the AXI4 protocol and the HyperBus protocol, the design logic completes the conversion between the AXI4's separated channel architecture (independent read and write channels) and the HyperBus's multiplexed command bus, the conversion between the AXI4's variable-length burst and the HyperBus's fixed 16, 32, 64, and 128-byte burst, and the conversion between the AXI4's unaligned access and the HyperBus's byte access timing.

[0041] 2. Achieving reliable data recovery on high-speed HyperBus interfaces

[0042] In data recovery of read timing, oversampling RWDS transforms the essence of the data recovery problem from "finding the optimal sampling point" in traditional data recovery solutions to "identifying the transition edge position" in this solution, greatly improving the tolerance to clock jitter and the reliability of data recovery.

[0043] 3. Simplify the delay calibration steps

[0044] Traditional data recovery methods based on delay adjustment require repeated calibration of delay parameters under varying manufacturing processes, ambient temperatures, and voltage conditions to ensure the phase relationship between the RWDS signal and DQ data in the HyperBus interface. This solution bypasses the search for the "optimal sampling point" and, while ensuring consistent board-level trace lengths, eliminates the calibration step, significantly simplifying program design.

[0045] In summary, the proposed method solves key technical problems such as protocol conversion, timing matching, and data recovery in high-speed data transmission, and is applicable to embedded systems, IoT devices, and high-performance computing. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] In order to make the contents of the present invention more clearly understood, the present invention is further described in detail below based on specific embodiments of the present invention in conjunction with the accompanying drawings.

[0047] Figure 1 Schematic diagram of the overall architecture of the AXI4-HyperBus bridge of the present invention;

[0048] Figure 2 This is a schematic diagram of the AXI4 read / write channel arbitration logic of the present invention;

[0049] Figure 3 This is a schematic diagram of the instruction and data synchronization logic of the cross-clock domain synchronization unit of the present invention;

[0050] Figure 4 1 is a flow chart of the HyperBus write timing control unit of the present invention;

[0051] Figure 5 1 is a flow chart of the HyperBus read timing control unit of the present invention;

[0052] Figure 6 Schematic diagram of the composition of the HyperBus read timing data recovery unit of the present invention;

[0053] Figure 7 Schematic diagram of RWDS signal edge detection according to the present invention;

[0054] Figure 8 This is a schematic diagram of the state transition of the edge detection principle of the present invention;

[0055] Figure 9 The data shaping unit of the present invention is a schematic diagram of the operation flow;

[0056] Figure 10 It is the HyperBus transaction conversion relationship diagram of the present invention;

[0057] Figure 11It is a schematic diagram of the arbitration hardware truth table and state machine for polling of the present invention;

[0058] Figure 12 It is a schematic diagram of cross-clock domain synchronization of key signal parameters of the present invention;

[0059] Figure 13 It is a schematic diagram of the reliability assurance index of cross-clock domain synchronization according to the present invention;

[0060] Figure 14 It is a schematic diagram of burst length mapping according to the present invention. DETAILED DESCRIPTION Example

[0061] This embodiment provides an efficient bridging device for connecting AXI4 and HyperBus. The efficient bridging device is designed to replace center sampling with edge detection, and is implemented using the following technical solutions:

[0062] Figure 1 The AXI4-HyperBus bridge is composed of a clock domain synchronization unit, a read / write channel arbitration unit, a HyperBus write timing control unit, a HyperBus read timing control unit, and an IO switching unit to realize the protocol conversion from the AXI4 interface to the HyperBus interface.

[0063] The cross-clock domain synchronization unit receives the address, data, burst length and other signals of the AXI4 read and write channels to achieve cross-clock domain synchronization between the AXI4 and HyperBus ends. The read and write channel arbitration unit implements the arbitration function of AXI4 full-duplex read and write requests, and realizes the request distribution of AXI4 read and write requests to the HyperBus end. The HyperBus write timing control unit is responsible for receiving AXI4 type write requests, and converting the write requests of the AXI4 protocol into write timing that meets the requirements of HyperBus, and writing them to the HyperBus end device. The HyperBus read timing control unit is responsible for receiving AXI4 type read requests, and converting the read requests of the AXI4 protocol into read timing that meets the requirements of HyperBus, and obtaining data from the HyperBus end. IO switching is used to implement pin function switching of HyperBus timing under read and write conditions.

[0064] Furthermore, in order to realize the AXI4 full-duplex read and write request arbitration function, the arbitration logic of the read and write channel arbitration unit is used Figure 2Indicates. When there is only a write request or a read request, the read-write channel arbitration unit directly issues the write request or read request. When both a write request and a read request exist, since the HyperBus bus is a read-write time-sharing multiplexed bus, the read request and the write request need to be processed sequentially. In the present invention, a polling method is used to cyclically process the situation where both read and write requests exist.

[0065] At the same time through Figure 11 As shown, the arbitration logic is supplemented, where:

[0066] axi_rd_req: AXI4 read request valid;

[0067] axi_wr_req: AXI4 write request valid;

[0068] last_op_type: last operation selection;

[0069] last_op_update: whether to update last_op_type.

[0070] In addition, the state transition rule of the above truth value is written as Figure 2 A flowchart decision node.

[0071] Furthermore, to implement the cross-clock domain synchronization unit, the instruction and data synchronization logic is as follows: Figure 3 shown.

[0072] Specifically, the source of the control instruction is the AXI4 initiator. To synchronize the instruction type, the transmission control byte must first be spliced. The address, burst length, burst type, read / write type, and other information must be spliced ​​and sent to the cross-clock domain synchronization logic. The cross-clock domain synchronization logic performs cross-clock domain processing to achieve the conversion of the source clock CLK_SRC to the destination clock CLK_DST. Afterwards, on the CLK_DST clock domain side, the transmission control byte is split to generate the control timing of the HyperBus. To ensure the stability of the cross-clock signal, the REQ request signal is sent out synchronously with the transmission control byte on the CLK_SRC side and connected to the cross-clock domain synchronization logic. After receiving the REQ signal, CLK_DST returns an ACK signal, and after synchronization through the cross-clock domain synchronization logic, it returns to the CLK_SRC side to release the REQ request.

[0073] Specifically, the source of write data is the write data channel of the AXI4 initiator. To meet the narrowband transmission requirements of AXI4, the write data and the data valid indication signal STRB need to be split and recombined and written into the asynchronous FIFO, which implements the cross-clock domain conversion of data. The clock on the write side is CLK_SRC. At the read end of the asynchronous FIFO, CLK_DST reads the split data, extracts the STRB information and data information, and generates the RWDS signal timing according to the STRB information in accordance with the HyperBus protocol requirements. The write data is written according to BYTE, completing the access to the HyperBus write timing.

[0074] Specifically, the source of the read data is the HyperBus end. After writing the control byte according to the control instruction, the HyperBus device will return the read byte to the HyperBus bus after the specified delay. Based on the RWDS signal in the HyperBus protocol, the return data valid indication signal STRB is generated, and STRB and the read data are written into the asynchronous FIFO together to achieve the clock domain conversion from CLK_DST to CLK_SRC. On the CLK_SRC side, the data in the FIFO is read, merged and spliced ​​according to the AXI4 protocol requirements, and then returned through the AXI4 read data channel.

[0075] The asynchronous FIFO depth must be able to store at least two complete maximum AXI4 transaction data volumes.

[0076] In a typical scenario (AXI4-bit width 64 bits, burst length 128): Depth ≥ 2 × 128 = 256;

[0077] Therefore, a FIFO with a depth of 256 and a total capacity of 256×64B is selected to implement data buffering to ensure that the HyperBus bus continues to transmit at full load.

[0078] Specifically, HyperBus parameters:

[0079] - Data width: 8 bits (bidirectional)

[0080] - Data transmission: DDR (Double Data Rate), 2 bytes are transmitted per clock cycle (because 8bit*2)

[0081] - Burst length: 16, 32, 64, 128 bytes (corresponding to 8, 16, 32, 64 DDR clock cycles, as 2 bytes are transferred per clock cycle)

[0082] - Maximum burst length: 128 bytes

[0083] AXI4 parameters:

[0084] - Data bit width: 32 bits, 64 bits, 128 bits, 256 bits, 512 bits, etc. (i.e. 4 bytes, 8 bytes, 16 bytes, 32 bytes, 64 bytes)

[0085] - Burst length: 1 to 256 transmissions (the amount of data in each transmission is equal to the number of bytes corresponding to the data bit width)

[0086] In AXI4's WRAP BURST mode, there is usually no need to consider the situation where an AXI4 transfer is split into multiple HyperBus transfers, because HyperBus supports WRAP burst mode and the total data transmission volume of the two can be completely equal.

[0087] Taking AXI4's INCR BURST mode as an example, under different bit widths and different burst lengths, the commonly used AXI4 parameter access conditions can be performed with HyperBus transactions as follows Figure 10 conversion;

[0088] As can be seen, under common AXI4 bus parameters, AXI4 transactions are typically converted into one or more HyperBus transactions. Because the bandwidth of the AXI4 side is generally greater than the bandwidth of the HyperBus bus, and AXI4 supports out-of-order transmission and outstanding features, its transmission efficiency is higher than the transmission efficiency of the HyperBus time-sharing read and write multiplexed bus. These two characteristics dictate that the HyperBus bus must be kept at full capacity as much as possible. In other words, in high-load scenarios, it is necessary to ensure that when the HyperBus bus needs to retrieve data from the FIFO, the data is immediately available.

[0089] Therefore, the FIFO depth must be able to continuously store more than two maximum AXI4 transactions. When using devices such as FPGAs, it is recommended to use a full BRAM for data buffering.

[0090] In addition, regarding the protocol conversion engine, the INCR burst of AXI4 to the fixed burst conversion rules of HyperBus, such as Figure 14 As shown in the figure; when AXI4 burst length × bit width = 16 / 32 / 64 / 128B, it is directly mapped to a single 16 / 32 / 64 / 128B HyperBus fixed burst, otherwise it is split into multiple 128B fixed-length bursts.

[0091] Furthermore, to implement the write timing access of the HyperBus, the operation process of the HyperBus write timing control unit is as follows: Figure 4As shown in the figure, since the HyperBus interface uses dual-edge transmission and the data bus is 8 bits, 16 bits of data must be transmitted in a single CLK_DST clock cycle. To complete HyperBus data writing, the device control registers must be configured first. After all control bytes have been transmitted, the data to be written can be written. Once the written data reaches the specified write length, the write sequential access ends.

[0092] Furthermore, to implement the read timing access of the HyperBus, the operation process of the HyperBus read timing control unit is as follows: Figure 5 As shown. Similarly, since the HyperBus interface data uses dual-edge transmission and the data bus is 8 bits, 16 bits of data need to be sent in a single clock cycle on the CLK_DST side. Similarly, to complete the HyperBus data reading, you first need to configure the device control register, and the configuration content is configured according to the read request content. After all control bytes are sent and the specified delay has passed, the HyperBus device returns the required data. In particular, the read data in the read timing access needs to be recovered from the HyperBus timing. In order to achieve stability and reliability of read data recovery, the data recovery logic needs to be designed separately. After all read data recovery is completed, the read timing access ends.

[0093] Furthermore, in order to realize the read data recovery logic required in the HyperBus read timing control unit, according to Figure 6 The architecture shown in the figure is used to design the HyperBus read timing data recovery module. This module consists of three parts: edge detection unit, sampling point selection unit and data shaping unit.

[0094] In summary, combined Figure 3 As shown, when using logic instead of asynchronous FIFO for cross-clock domain processing, the asynchronous signals that need to be processed synchronously include: Figure 12 As shown; and the above signals all use 3-level synchronization, the MTBF is as follows Figure 13 As shown in the figure, using asynchronous FIFO to synchronize data across clock domains can significantly increase the MTBF value mentioned above, far exceeding the designed lifespan. Example

[0095] This embodiment provides a HyperBus data recovery method. Specifically, the edge detection unit uses a 3x oversampling method to repeatedly sample the RWDS signal. Figure 7As shown in the figure, during HyperBus read access, the RWDS signal output by the device is strictly phase-aligned with the HyperBus output data. The 3x oversampling clock samples the RWDS signal on both the rising and falling edges, generating six sampling results per cycle and storing them in a 6-bit variable. x represents the result of sampling the unstable region and can be either 1 or 0. As time progresses, the 6-bit variable is continuously updated, resulting in the following 24 sampling values:

[0096] 000000 00000x 000001 0000x1 000011 000x11 000111 00x11x 00xxx0 0x11x0111000 x11x00 111000 11x00x 110001 1x00x1 100011 x00x11 11x000 110000 1x0000100000 x00000 000000

[0097] Specifically, since each x represents two possible values, x needs to be replaced. Figure 8 The edge detection principle diagram shown below shows that each x corresponds to two different sampling values. First, the possible sampling values ​​need to be enumerated, and then the repeated sampling values ​​after enumeration are removed to obtain 18 unique sampling results. 000000 000001 000011 000111 000110 001111 001100 011100 011110 011000 111000 111100 110000 111001 100001 110011 100111 100000

[0100] Furthermore, in order to achieve effective sampling of data, the sampling point selection unit needs to find a stable sampling position of the data based on the oversampling result of the RWDS.

[0101] Specifically, the criterion for determining the stable sampling position is the next sampling point of the RWDS edge. Therefore, it is necessary to first find the edge position of RDWS. Figure 8 As shown in the figure, XOR logic is used for edge detection, and repeated XOR results are removed to serve as the input of the subsequent logic. The result after XOR is as follows, where X represents the influence of the previous sampling value on the XOR result.

[0102] 00000X 00001X 00010X 00100X 00101X 01001X 01000X 01010X 10010X 00100X

[0103] 00010X 01000X 01001X 00101X 10001X 10010X 01010X 10100X 10000X

[0104] After removing duplicate XOR values, the result is as follows:

[0105] 00000X 00001X 00010X 00100X 00101X 01001X

[0106] 01000X 01010X 10010X 10001X 10100X 10000X

[0107] Specifically, the sampling point selection unit processes the XOR value of the current cycle's sampling results and, referring to the sampling results of the previous cycle, comprehensively determines the number of edges in the current cycle's sampling results. Edges are closely related to sampling points, and the number of edges is equal to the number of sampling times. The first bit of the current cycle is XORed with the last bit of the previous cycle; simultaneously, the last bit of the current cycle is shifted out for edge determination in the next cycle. This operation enables continuous edge detection across clock cycles, resolving the edge identification problem at clock boundaries.

[0108] Specifically, such as Figure 8 As shown, after obtaining all edge information and determining the number of edges, it is necessary to continue removing several illegal values. The illegal situations include: the XOR value has two consecutive edges, or more than three edges in total.

[0109] Specifically, after the edge information is obtained, the numerical sampling output of the next sampling point is the output result of the sampling point selection unit.

[0110] Furthermore, after obtaining the number of edge values ​​in the current sampling period, the number of possible sampling points may be any of 0, 1, 2, and 3. The number of edge values ​​in the previous period is also random. In order to ensure the output of continuous data stream, the data shaping unit needs to be based on Figure 9 The data sampling operation process shown is used to reshape the data.

[0111] Specifically, in the data shaping unit, data_cnt is used to represent the number of sample values ​​obtained at the next sampling point of the edge according to the edge position, which may be 0, 1, 2, or 3, corresponding to the number of edge values.

[0112] Specifically, in the data shaping unit, temp_valid represents the sampled data that is temporarily stored and not sent because the total number of sampled bits in the previous sampling cycle exceeds 16 bits. The possible values ​​are 2'b00, 2'b01, and 2'b11, which respectively represent the remaining 0 bits, 8 bits, and 16 bits of data that have not been sent in the previous cycle.

[0113] Specifically, when the current number of sampling points data_cnt=0, if temp_valid=2'b00, it means that there are no remaining bits to be sent in the previous cycle, and the current cycle execution is directly terminated.

[0114] Specifically, when the current number of sampling points data_cnt=0, if temp_valid=2'b11, indicating that 16 bits remain to be sent in the previous cycle, the 16-bit data to be sent is directly output, and then the execution ends.

[0115] Specifically, when the current number of sampling points data_cnt=1, if temp_valid=2'b00, it means that there are no remaining bits to be sent in the previous cycle, and the 8 bits of the current cycle need to be temporarily stored, and temp_valid is marked as 2'b01 for use in the next cycle.

[0116] Specifically, when the current number of sampling points data_cnt=1, if temp_valid=2'b01, it means that there are 8 bits left to be sent in the previous cycle. The 8 bits of the current cycle need to be spliced ​​with the 8 bits temporarily stored in the previous cycle and then sent, and temp_valid is marked as 2'b00, indicating that there are no remaining bits to be sent.

[0117] Specifically, when the current number of sampling points data_cnt=1, if temp_valid=2'b11, it means that there are 16 bits left to be sent in the previous cycle. The remaining 16 bits need to be sent first, and then the 8 bits of the current cycle are temporarily stored, and temp_valid is marked as 2'b01 for use in the next cycle.

[0118] Specifically, when the current number of sampling points data_cnt=2, if temp_valid=2'b00, it means that there are no remaining bits to be sent in the previous cycle, and the 16 bits of this cycle can be sent directly, and temp_valid is marked as 2'b00, indicating that there are no remaining bits to be sent.

[0119] Specifically, when the current number of sampling points data_cnt = 2, if temp_valid = 2'b01, it means that there are 8 bits left to be sent in the previous cycle. The 8 bits in the current cycle need to be spliced ​​with the 8 bits temporarily stored in the previous cycle and then sent. At the same time, the remaining 8 bits of the current cycle are temporarily stored, and temp_valid is marked as 2'b01 for use in the next cycle.

[0120] Specifically, when the current number of sampling points data_cnt=2, if temp_valid=2'b11, it means that there are 16 bits left to be sent in the previous cycle. The remaining 16 bits need to be sent first, and then the 16 bits of the current cycle are temporarily stored, and temp_valid is marked as 2'b11 for use in the next cycle.

[0121] Specifically, when the current number of sampling points data_cnt = 3, if temp_valid = 2'b00, it means that there are no remaining bits to be sent in the previous cycle. The 16 bits of the current cycle need to be sent first, and the remaining 8 bits of data need to be temporarily stored. At the same time, temp_valid is marked as 2'b01 for use in the next cycle.

[0122] Specifically, when the current number of sampling points data_cnt = 3, if temp_valid = 2'b01, it means that there are 8 bits left to be sent in the previous cycle. The 8 bits of the current cycle need to be spliced ​​with the 8 bits temporarily stored in the previous cycle and then sent. At the same time, the remaining 16 bits of the current cycle are temporarily stored, and temp_valid is marked as 2'b11 for use in the next cycle.

[0123] Specifically, the data shaping unit can stably output the recovered data stream through the logic implementation of the above data sampling process, return it to the AXI4 end, and complete the transmission of the read data.

[0124] Through the aforementioned solution, the present invention achieves efficient AXI4-to-HyperBus protocol conversion, enabling efficient access to HyperBus devices via the AXI4 interface, thereby implementing the aforementioned AXI4-to-HyperBus bridge. By utilizing the aforementioned oversampling method for data recovery, the present invention transforms the essence of the data recovery problem from "finding the optimal sampling point" in traditional data recovery solutions to "identifying the transition edge position" in this solution, significantly improving the data recovery process's tolerance to clock jitter and the reliability of the data recovery results.

[0125] The data recovery method described in the present invention has the advantage of simplifying and eliminating the delay calibration step required by traditional data recovery methods. Specifically, because the RWDS is strictly aligned with the HyperBus output data phase, traditional data recovery methods achieve stable sampling by adjusting the RWDS phase to bring the RWDS edge closer to the data sampling center. However, due to:

[0126] 1) The phase adjustment method is not universal due to differences in temperature, voltage, and chip manufacturing process;

[0127] 2) As the chip temperature increases, the adjusted RWDS phase will drift;

[0128] 3) In most cases, the RWDS edge cannot be aligned with the data sampling center;

[0129] 4) Sampling delay adjusts the phase, and the adjustment value is limited.

[0130] Due to the four reasons mentioned above, the data sampling method that adjusts the RWDS phase suffers from poor stability and environmental adaptability. The oversampling recovery method described in this invention uses the next sampling point after the RWDS edge as the sampling position. This method is unaffected by clock jitter and eliminates the need for RWDS delay adjustment, significantly simplifying program design.

[0131] At the same time, in order to further illustrate the advantages of the invention of this application, the following usage scenarios are provided to assist in proof.

[0132] This embodiment is used in scenario 1: high-speed storage and energy efficiency optimization in a low-power embedded image processing system

[0133] In traditional image processing systems, DDR (Double Data Rate) memory is widely used due to its high bandwidth and low latency. However, it faces the following core contradictions in low-power embedded scenarios:

[0134] High power consumption bottleneck: DDR memory's dynamic refresh mechanism results in high standby power consumption, typically exceeding 100mW. Combined with the PHY power consumption of the chip's IP, the typical standby power consumption due to DDR is over 500mW. In battery-powered embedded devices (such as drones and smart cameras), power consumption continues to rise as data access increases. DDR's high power consumption significantly shortens battery life.

[0135] High system complexity: The DDR interface requires independent address / data buses and complex timing control (such as pre-charge and refresh cycles), which increases the complexity of PCB wiring and occupies more SoC logic resources.

[0136] Thermal management challenges: The power consumption density during high-bandwidth operation (e.g., 2-3W per GB / s of bandwidth) requires additional heat dissipation design, limiting the miniaturization of the device and its deployment in closed environments.

[0137] Hyperbus storage (such as HyperFlash or HyperRAM) provides a balance of low power consumption and high bandwidth for image processing systems through innovations in protocol design and hardware architecture:

[0138] Low-power architecture: Supports deep sleep mode (Power-Down Mode), reducing standby power consumption to below 10mW (compared to DDR's 100mW); HyperFlash does not require dynamic refresh, and HyperRAM reduces the refresh frequency through a pseudo-static design, significantly reducing overall power consumption.

[0139] High-efficiency bandwidth: At a 200MHz clock frequency, Hyperbus' theoretical bandwidth can reach 400Mbps (8-bit data width DDR transmission), with controller efficiency approaching 74%, approaching the performance of DDR3L while consuming only one-third of DDR3L. It also supports Long Burst Mode, reducing address switching overhead during image data transmission and improving transmission efficiency (data throughput increased by 20% in typical scenarios).

[0140] Simplified system design: Through address / data multiplexing and shared control signals, the pin count is reduced by 40% compared to DDR, reducing PCB routing complexity and cost. Combined with the AXI4-Hyperbus conversion bridge, the software layer is no longer required for protocol conversion, reducing system latency and CPU load.

[0141] Hyperbus storage, through protocol design, hardware architecture, and scenario-based optimization, achieves bandwidth performance comparable to traditional DDR storage in low-power embedded image processing systems while significantly reducing both dynamic and standby power consumption. Its energy efficiency advantage not only extends device battery life but also simplifies system design, providing key technical support for battery-powered devices, deployment in confined environments, and large-scale edge computing nodes.

[0142] This embodiment is in scenario 2: CPU cache architecture innovation based on Hyperbus storage

[0143] In high-performance CPUs (such as the ARM Cortex-A series) or real-time operating systems (RTOS), traditional SRAM caches are limited by cost and capacity, making them difficult to meet the high-speed access requirements of large data volumes. Hyperbus storage devices (such as HyperRAM) are ideal for cache expansion due to their low power consumption and high bandwidth, but they must address the following technical challenges:

[0144] Due to the protocol differences between the CPU's AXI4 interface and Hyperbus storage devices, the CPU cannot directly access external storage devices on the HyperBus interface through the AXI4 interface. The following innovations are achieved through the AXI4-Hyperbus conversion bridge:

[0145] Supports AXI4's WRAP BURST mode. Through protocol mapping optimization, AXI4's read and write transactions are mapped to Hyperbus's WRAP burst read and write instructions. The hardware pipeline compresses the protocol conversion overhead to achieve access speeds close to SRAM.

[0146] By using a HyperBus storage device to expand cache capacity, the HyperBus storage device can be used as a 256MB extended cache, significantly reducing the CPU's reliance on main memory (DDR) and improving program execution efficiency (approximately matching the efficiency of SRAM cache). Compared to traditional SRAM cache solutions, using HyperBus storage devices can reduce hardware costs by over 50%, making it suitable for edge computing devices and IoT gateways.

[0147] In summary, the invention application scheme and implementation examples, relying on the designed AXI4-HyperBus bridge, can achieve:

[0148] AXI4 port accesses HyperBus interface devices;

[0149] In power-sensitive scenarios, it can replace DDR chips and significantly reduce the power consumption of embedded devices;

[0150] When used as a CPU external cache, it can achieve access speeds close to SRAM, significantly reducing costs.

[0151] The data recovery method:

[0152] The delay calibration step can be omitted;

[0153] Simplify program design;

[0154] Stability is not affected by temperature, voltage and manufacturing process.

[0155] The proposed AXI4-HyperBus bridging solution effectively addresses key technical challenges in high-speed bus interfaces through an innovative protocol conversion architecture and unique data recovery methods. Specifically, the design of the data recovery unit shifts the core issue from finding the center of the data sampling window to finding the edges of the RWDS signal, enabling reliable data recovery under high-speed transmission conditions. This solution offers significant advantages, including high performance, low power consumption, and high reliability.

[0156] Obviously, the above embodiments are merely examples for clarity of explanation and are not intended to limit the implementation methods. Those skilled in the art will appreciate that other variations or modifications can be made based on the above description. It is not necessary and impossible to enumerate all implementation methods here. Obvious variations or modifications arising therefrom remain within the scope of protection of the present invention.

Claims

1. An efficient bridging device for connecting AXI4 and HyperBus, wherein edge detection is designed to replace center sampling, characterized in that: include: Protocol conversion engine: The input end is connected to the read and write channels of the AXI4 master device, and the output end is connected to the read and write channel arbitration unit, which is used to convert AXI4 variable bursts into HyperBus fixed bursts; Read / write channel arbitration unit: The input end is connected to the protocol conversion engine, and the output end is connected to the HyperBus write timing control unit and the HyperBus read timing control unit respectively, using a polling mechanism to distribute concurrent requests; HyperBus read timing control unit: The input end is connected to the read / write channel arbitration unit, and the output end is connected to the IO switching unit. It has an internal integrated edge-driven data recovery module. Edge-driven data recovery module: The input receives the HyperBus RWDS signal and DQ data, and the output is connected to the cross-clock domain synchronization unit through the data shaping unit. The edge detection unit uses 3x oversampling technology to detect the edge of the HyperBus RWDS signal, uses the next sampling point of the transition edge as the data valid bit, and outputs it to the data shaping unit. Cross-clock domain synchronization unit: contains an asynchronous FIFO, whose write port is connected to the data shaping unit and the read port is connected to the AXI4 read data channel.

2. The high-efficiency bridging device according to claim 1, characterized in that: The edge-driven data recovery module includes: an edge detection unit; receiving the RWDS signal of HyperBus, performing 3x oversampling and outputting the transition edge position; a sampling point selection unit; the input end of which is connected to the edge detection unit and extracts valid bits from the DQ data stream based on the transition edge position; and a data shaping unit; the input end of which is connected to the sampling point selection unit and splices 16-bit data blocks according to data_cnt and temp_valid.

3. The high-efficiency bridging device according to claim 2, characterized in that: The data shaping unit performs: receiving the data bits and the corresponding edge number data_cnt output by the sampling point selector; combining the temporary storage state temp_valid, splicing 16-bit data blocks according to the preset priority rule; and outputting the spliced ​​data to the asynchronous FIFO write port.

4. The high-efficiency bridging device according to claim 1, characterized in that: The input end of the HyperBus write timing control unit is connected to the read / write channel arbitration unit to receive AXI4 write data and STRB signals; the output end is connected to the IO switching unit to convert the STRB signal into the RWDS timing of HyperBus; and the write data synchronization from CLK_SRC to CLK_DST is achieved through the asynchronous FIFO.

5. The high-efficiency bridging device according to claim 1, characterized in that: The cross-clock domain synchronization unit includes: an instruction synchronization channel, which transmits control bytes through the REQ / ACK handshake mechanism; a data synchronization channel, which synchronizes write data to CLK_DST via the asynchronous FIFO and read data to CLK_SRC via the asynchronous FIFO.

6. The high-efficiency bridging device according to claim 1, characterized in that: The edge-driven data recovery module is connected to the HyperBus read timing control unit via a parallel bus. Its input signals are: RWDS, DQ[7:0], HCLK; and its output signals are: recovered data[15:0], data valid flag.

7. A HyperBus data recovery method, referring to the efficient bridging device design of any one of claims 1 to 6, characterized in that: The steps include: Step S1: Oversampling, sampling the RWDS signal at 3 times the HyperBus clock frequency to generate a 6-bit sequence; Step S2: Edge positioning, performing an XOR operation on the continuous 6-bit sequence to identify the valid transition edge; Step S3: Data extraction, taking the next sampling point of the first valid transition edge as the DQ data valid bit; Step S4: Dynamic shaping, splicing 16-bit data blocks according to the priority rules based on the edge number data_cnt and the temporary storage state temp_valid; The priority rules in step S4 include: when data_cnt=2 and temp_valid=2'b01: send the first 16 bits; temporarily store the remaining 8 bits of the current cycle; When data_cnt = 3 and temp_valid = 2'b00: send the first 16 bits; temporarily store the remaining 8 bits.

8. The data recovery method according to claim 7, wherein: In step S1, a 6-bit shift register is used to sample three times each on the rising edge and falling edge of the HyperBus clock.

9. The data recovery method according to claim 7, wherein: Step S2 further includes: filtering illegal sequences containing two consecutive transition edges or a total transition number greater than 3; and reducing the 6-bit XOR result sequence to 12 valid states.

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