Heterogeneous integrated signal processing device and signal processor for high-frequency wide signal acquisition

Abstract

The invention discloses a heterogeneous integrated signal processing device and a signal processor for high-frequency wide signal acquisition. The device comprises an FPGA (Field Programmable Gate Array) functional unit, a DSP (Digital Signal Processor) functional unit and an RFSOC (Radio Frequency System On Chip) functional unit, the FPGA functional unit is connected with the DSP functional unit, the RFSOC functional unit and the connector, the DSP functional unit is also connected with the RFSOC functional unit and the connector, and the RFSOC functional unit is connected with each ADC application. The DSP function unit, the FPGA function unit and the RFSOC function unit are deeply coupled, dynamic reconstruction of a signal processing link is achieved, the FPGA function unit undertakes preprocessing of data signals of the ADC module unit, the RFSOC function unit completes digital down-conversion and channelization, the DSP function unit accelerates a complex algorithm, the computing power bottleneck of a traditional single chip is broken through, and the FPGA function unit and the RFSOC function unit are integrated. And the high instantaneous bandwidth processing capability is accelerated.

Description

Technical Field

[0001] The present invention relates to the technical field of high-frequency signal processing, and in particular to a heterogeneous integrated signal processing device and a signal processor for high-frequency bandwidth signal acquisition. Background Art

[0002] With the rapid development of 5G communications, radar detection, electronic countermeasures and other fields, the bandwidth requirements of the system for signal acquisition and processing have exceeded the GHz level, and the traditional signal processing architecture faces severe challenges. The existing technologies mainly adopt the following architectures: (1) The single DSP architecture is limited by the computing power bottleneck and it is difficult to achieve real-time processing of GHz-level signals; (2) Although the pure FPGA solution has high parallelism, the algorithm flexibility is insufficient; (3) The discrete multi-chip architecture has low clock synchronization accuracy (JESD204B interface clock jitter>100fs), high power consumption density (>15W / cm 2 ), poor system stability and other prominent problems. Summary of the Invention

[0003] The main purpose of this invention is to propose a heterogeneous integrated signal processing device and signal processor for high-bandwidth signal acquisition, aiming to break through the bottleneck of traditional single-chip computing power and achieve high instantaneous bandwidth processing capabilities.

[0004] To achieve the above-mentioned object, the present invention proposes a heterogeneous integrated signal processing device for high-bandwidth signal acquisition, which includes: an FPGA functional unit, a DSP functional unit and an RFSOC functional unit;

[0005] The FPGA functional unit is connected to the DSP functional unit, the RFSOC functional unit and a connector, the DSP functional unit is further connected to the RFSOC functional unit and the connector, and the RFSOC functional unit is connected to each ADC application;

[0006] The RFSOC functional unit is used to synchronize the received data signals of the ADC applications and transmit them to the FPGA functional unit when the synchronization is completed;

[0007] The FPGA functional unit is used to pre-process the data signal;

[0008] The RFSOC functional unit is used to perform multi-channel digital down-conversion processing on the pre-processed data signal;

[0009] The DSP functional unit is used to perform calculation processing on the multiple processed data signals simultaneously according to the algorithm library.

[0010] In one embodiment, the DSP functional unit further includes: a host software module and a DSP software module;

[0011] The DSP software module is also connected to the RFSOC functional unit, the connector and the host software module;

[0012] The host software module is configured to receive a control instruction input by a user and output the control instruction to the corresponding DSP software module;

[0013] The DSP software module is used to perform corresponding operations according to the control instructions.

[0014] In one embodiment, the DSP software module further includes: a top-level module, an algorithm module, a communication module, and a driver module;

[0015] The algorithm module connects the top-level module and the communication module, and the driver module connects the communication module and each unit;

[0016] The top-level module is configured to receive the control instructions from the host software module and transmit the control instructions to the algorithm module;

[0017] The algorithm module is used to process the control instruction through the algorithm library to obtain the driving signal;

[0018] The communication module is used to receive and transmit the driving signal to each of the DSP software modules;

[0019] The driving module is used to drive corresponding hardware resources using an operation function according to the driving signal.

[0020] In one embodiment, the host software module further includes: a host top-level module, a thread module, and a host driver module;

[0021] The thread module connects the host top-level module and the host driver module;

[0022] The host top-level module is used to distinguish each of the DSP software modules and establish a corresponding relationship between each of the DSPs and the corresponding threads;

[0023] The host driving module is used to generate corresponding driving signals according to user commands;

[0024] The thread module is used to mobilize the corresponding DSP software module according to the driving signal.

[0025] In one embodiment, the RFSOC functional unit includes: a synchronization unit and an ADC functional unit;

[0026] The ADC functional unit is connected to the FPGA functional unit and the corresponding ADC application, and the synchronization unit is connected to the FPGA functional unit and the DSP functional unit;

[0027] The ADC functional unit is configured to transmit data signals of the connected ADC applications to the FPGA functional unit;

[0028] The synchronization unit is used to cache the data signal of each unit using a buffer when the data signal reaches the FPGA functional unit; and transmit the synchronized data signal to the DSP functional unit when the data signal stops inputting.

[0029] In one embodiment, the plurality of ADC functional units are all connected to the same clock, and the clock signals output by the clock have the same phase when arriving at each of the ADC applications.

[0030] In one embodiment, the synchronization unit is further configured to add a timestamp control bit to the data of each unit, and perform frame clock phase synchronization via the timestamp control bit.

[0031] In one embodiment, the apparatus further comprises: an MCU functional unit;

[0032] The MCU functional unit is connected to the DSP functional unit, the FPGA functional unit and the connector;

[0033] The MCU functional unit is used to collect status information of each unit and adjust the power consumption of each unit according to the status information.

[0034] In one embodiment, the MCU functional unit is also used to locate and repair faults.

[0035] The present invention further provides a signal processor, which includes the heterogeneous integrated signal processing device for high-bandwidth signal acquisition as described above.

[0036] The present invention discloses a heterogeneous integrated signal processing device and signal processor for high-bandwidth signal acquisition. The device includes: an FPGA functional unit, a DSP functional unit, and an RFSOC functional unit; the FPGA functional unit is connected to the DSP functional unit, the RFSOC functional unit, and a connector, the DSP functional unit is further connected to the RFSOC functional unit and the connector, and the RFSOC functional unit is connected to each ADC application; the RFSOC functional unit is used to synchronize the received data signals of each ADC application and transmit them to the FPGA functional unit when the synchronization is completed; the FPGA functional unit is used to preprocess the data signals; the RFSOC functional unit is used to perform multi-channel digital down-conversion processing on the preprocessed data signals; and the DSP functional unit is used to simultaneously perform calculation processing on multiple processed data signals according to an algorithm library. This application deeply couples the three major computing units, DSP functional unit, FPGA functional unit and RFSOC functional unit, through the VNX architecture, realizing dynamic reconstruction of the signal processing link. The FPGA functional unit is responsible for the preprocessing of the ADC module unit data signal, the RFSOC functional unit completes digital down-conversion and channelization, and the DSP functional unit accelerates complex algorithms. This device breaks through the bottleneck of traditional single-chip computing power and achieves high instantaneous bandwidth processing capabilities. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the structures shown in these drawings without paying any creative work.

[0038] Figure 1 A schematic diagram of the modules of the first embodiment of the heterogeneous integrated signal processing device for high-bandwidth signal acquisition provided by the present invention;

[0039] Figure 2 A schematic structural diagram of a first embodiment of a heterogeneous integrated signal processing device for high-bandwidth signal acquisition provided by the present invention;

[0040] Figure 3 A schematic structural diagram of a second embodiment of a heterogeneous integrated signal processing device for high-bandwidth signal acquisition provided by the present invention;

[0041] Figure 4 A first structural diagram of a third embodiment of the heterogeneous integrated signal processing device for high-bandwidth signal acquisition provided by the present invention;

[0042] Figure 5A second structural diagram of the third embodiment of the heterogeneous integrated signal processing device for high-bandwidth signal acquisition provided by the present invention;

[0043] Figure 6 A third structural diagram of the third embodiment of the heterogeneous integrated signal processing device for high-bandwidth signal acquisition provided by the present invention;

[0044] Figure 7 A fourth structural diagram of the third embodiment of the heterogeneous integrated signal processing device for high-bandwidth signal acquisition provided by the present invention;

[0045] Figure 8 A fifth structural diagram of the third embodiment of the heterogeneous integrated signal processing device for high-bandwidth signal acquisition provided by the present invention;

[0046] Figure 9 A sixth structural diagram of the third embodiment of the heterogeneous integrated signal processing device for high-bandwidth signal acquisition provided by the present invention;

[0047] Figure 10 A seventh structural diagram of the third embodiment of the heterogeneous integrated signal processing device for high-bandwidth signal acquisition provided by the present invention;

[0048] Figure 11 This is an eighth structural diagram of the third embodiment of the heterogeneous integrated signal processing device for high-bandwidth signal acquisition provided by the present invention.

[0049] Description of Figure Numbers:

[0050] Label name Label name 100 ADC Applications 500 Connectors 200 FPGA functional unit 400 DSP functional unit 300 RFSOC functional unit

[0051] The purpose, features and advantages of the present invention will be further described with reference to the accompanying drawings and in conjunction with the embodiments. DETAILED DESCRIPTION

[0052] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making any creative efforts shall fall within the scope of protection of the present invention.

[0053] It should be noted that if the embodiments of the present invention involve directional indications (such as up, down, left, right, front, back, etc.), the directional indications are only used to explain the relative position relationship, movement status, etc. between the components under a certain specific posture. If the specific posture changes, the directional indications will also change accordingly.

[0054] In addition, if there are descriptions involving "first", "second", etc. in the embodiments of the present invention, the descriptions of "first", "second", etc. are only for descriptive purposes and cannot be understood as indicating or suggesting their relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features limited to "first" and "second" may explicitly or implicitly include at least one of such features. In addition, if "and / or" or "and / or" appears in the full text, its meaning includes three parallel solutions. Taking "A and / or B" as an example, it includes solution A, solution B, or solutions that satisfy both A and B. In addition, the technical solutions between the various embodiments can be combined with each other, but it must be based on the ability of ordinary technicians in this field to implement. When the combination of technical solutions is mutually contradictory or cannot be implemented, it should be deemed that such a combination of technical solutions does not exist and is not within the scope of protection required by the present invention.

[0055] With the rapid development of 5G communications, radar detection, electronic countermeasures and other fields, the bandwidth requirements of the system for signal acquisition and processing have exceeded the GHz level, and the traditional signal processing architecture faces severe challenges. The existing technologies mainly adopt the following architectures: (1) The single DSP architecture is limited by the computing power bottleneck and it is difficult to achieve real-time processing of GHz-level signals; (2) Although the pure FPGA solution has high parallelism, the algorithm flexibility is insufficient; (3) The discrete multi-chip architecture has low clock synchronization accuracy (JESD204B interface clock jitter>100fs), high power consumption density (>15W / cm 2 ), poor system stability and other prominent problems.

[0056] The heterogeneous integrated signal processing device proposed in this application for high-bandwidth signal acquisition innovatively constructs a three-dimensional heterogeneous computing system.

[0057] like Figure 1 As shown in FIG, a structural diagram of the first embodiment of the heterogeneous integrated signal processing device for high-bandwidth signal acquisition proposed in this embodiment.

[0058] The device includes: an FPGA functional unit 200, a DSP functional unit 400 and an RFSOC functional unit 300; the FPGA functional unit is connected to the DSP functional unit, the RFSOC functional unit and a connector, the DSP functional unit is also connected to the RFSOC functional unit and the connector, and the RFSOC functional unit is connected to each ADC application 100; the RFSOC functional unit is used to receive and synchronize the data signals of each ADC application, and transmit them to the FPGA functional unit when the synchronization is completed; the FPGA functional unit is used to preprocess the data signals; the RFSOC functional unit is used to perform multi-channel digital down-conversion processing on the preprocessed data signals; and the DSP functional unit is used to simultaneously perform calculation processing on multiple processed data signals according to an algorithm library.

[0059] It is understandable that if Figure 2 As shown, this application is based on the VNX architecture and adopts one domestic FT-M6678dsp (8 cores, main frequency 1GHz); one Xilinx Virtex UltraScale+ series FPGA (XCVU9P-2FLGB2104I); one XILINX RFSOC XCZU27DR-L1FFVG1517I; one ADI company's HMC7044 clock distribution chip with JESD204B interface; one Chengdu Huawei MCU for low-power control and multiple DDR4, DDR3, Flash, RS422, TTL and other chips. The board integrates BMC function, which can report temperature, voltage and main chip working status information, and receive chassis management commands to realize module power on and off, reset and other functions.

[0060] It's important to note that the VNX architecture is centered around network switching, optimizing network resource utilization through internal logical connections for efficient data transmission. VNX storage devices consist of two storage processors (SPs), the SPA and SPB, each with corresponding external ports. Unisphere integrates management for storage configuration, monitoring, maintenance, and data protection, supporting unified installation assistance, software upgrades, and online community resources.

[0061] Specifically, the FPGA functional unit is responsible for resetting and configuring each module, as well as interface conversion. It also leverages the FPGA's reconfigurability and programmability to implement diverse functional algorithms. The FPGA functional unit uses the Xilinx Ultrascale+ series FPGA XCVU9P-2FLGB2104I, which offers high performance, low power consumption, and optimal price-performance. The device also features 2,586,150 logic resources, 6,840 DSP resources, 76 32.75 Gb / s high-speed transceivers (GTYs), and 702 I / O interfaces.

[0062] The DSP functional unit utilizes the National University of Defense Technology's high-performance military multi-core floating-point processor, the FT-M6678, to perform data signal preprocessing, filtering, predistortion, and compensation. The DSP functional unit boasts flexible addressing and high computational speed. Utilizing DSP technology for parameterized design, such as radar signal pulse and repetition rate, this accelerates information processing, reduces the number of computations required, and improves computational accuracy.

[0063] The RFSOC functional unit is responsible for 8-channel data acquisition, digital down-conversion, data filtering, signal processing, data packaging, data distribution, and external interfacing. The Xilinx XCZU28DR-L1FFVG1517I FPGA from the RFSOC series is used for this RFSOC. This device features 930K logic resources, 4272 DSP cores, 38.0Mb of block RAM, 214 PSIOs, 48 HDIOs, 299 HPIOs, 4 GTRs, 16 GTYs, 8 RF-ADCs, and 8 RF-DACs. The RFSOC supports direct digitization of RF signals up to 18 GHz (such as the AMD Versal RF series), eliminating the distortion and latency associated with analog down-conversion. By integrating the ADC / DAC, FPGA, ARM processor, and high-speed interfaces (such as 100Gbps QSFP), the system footprint is reduced by over 50% and power consumption is reduced to one-third of traditional solutions. Compared with conventional signal acquisition boards, using the ADC function unit integrated inside the RFSOC function unit can save cost and space, and more functions can be implemented in a limited layout space.

[0064] The device further includes: an MCU functional unit; the MCU functional unit is connected to the DSP functional unit, the FPGA functional unit and the connector; the MCU functional unit is used to collect status information of each unit and adjust the power consumption of each unit according to the status information.

[0065] The MCU functional unit is also used to locate and repair faults.

[0066] It is understandable that the MCU functional unit implements power consumption control through the Huawei MCU, and the BMC module builds a multi-dimensional state perception network, which can achieve sub-millisecond fault location and self-repair. The BMC module monitors the server's temperature, voltage, fan speed, power status and other key parameters in real time, supports sensor data collection, and ensures that the hardware operates within a safe range. It provides out-of-band management (Out-of-Band Management) function, and administrators can remotely access the server through the network. Even if the operating system is not started or crashes, troubleshooting and repairs can still be performed. Control the power status of the server (power on, power off, restart, cycle power on), support power policy configuration, and optimize energy consumption and heat dissipation.

[0067] In this embodiment, the three major computing units of FT-M6678 multi-core DSP, Virtex UltraScale+FPGA, and RFSOC are deeply coupled through the VNX architecture to achieve dynamic reconstruction of the signal processing chain: FPGA is responsible for the pre-processing of 10GSPS-level ADC data, RFSOC completes digital down-conversion and channelization (supports 2048 channels of parallel processing), and FT-M6678 accelerates complex algorithms through the SIMD instruction set. The power management system is controlled by the MCU for power consumption, and the BMC module builds a multi-dimensional state-aware network that can achieve sub-millisecond fault location and self-repair. While achieving high instantaneous bandwidth processing capabilities, this device provides a highly reliable, strong real-time, and scalable autonomous solution for high-bandwidth signal processing.

[0068] like Figure 3 As shown in FIG, a structural diagram of a second embodiment of a heterogeneous integrated signal processing device for high-bandwidth signal acquisition proposed in this embodiment.

[0069] Based on the above first embodiment, a second embodiment of a heterogeneous integrated signal processing device for high-bandwidth signal acquisition of the present invention is proposed.

[0070] The DSP functional unit also includes: a host software module and a DSP software module; the DSP software module is also connected to the RFSOC functional unit, the ADC module unit, the connector and the host software module; the host software module is used to receive control instructions input by the user and output the control instructions to the corresponding DSP software module; the DSP software module is used to perform corresponding operations according to the control instructions.

[0071] It is understood that the DSP functional unit simultaneously performs computational processing on multiple processed data signals based on the algorithm library. To meet the aforementioned technical requirements for software design, a layered approach was adopted in the development of the software platform, constructing a complete, universal, and scalable software development model. The DSP software module was divided into four relatively independent layers: the top-level module, the algorithm module, the communication module, and the driver module; and the host software module was divided into three layers: the top-level module, the thread module, and the driver module.

[0072] The DSP software module also includes: a top-level module, an algorithm module, a communication module and a driver module; the algorithm module connects the top-level module and the communication module, and the driver module connects the communication module and each unit; the top-level module is used to receive the control instructions of the host software module and transmit the control instructions to the algorithm module; the algorithm module is used to process the control instructions through the algorithm library to obtain a driving signal; the communication module is used to receive and transmit the driving signal to each DSP software module; the driver module is used to drive the corresponding hardware resources using the operation function according to the driving signal.

[0073] It should be noted that if Figure 3 As shown, the top-level module is the main process and the outermost process of the entire application. The algorithm module includes algorithm implementation and algorithm library. The algorithm implementation general algorithm module uses the algorithm library's efficient functions to implement typical radar signal processing algorithms, such as MTD and pulse compression; the algorithm library includes a set of efficient algorithm functions, such as FFT, complex multiplication, format conversion, etc. The communication module includes an interrupt service program and a debugging and monitoring communication core. The interrupt service program encapsulates various interrupt processing functions of the DSP. The debugging and monitoring communication core is responsible for multi-DSP communication, control tasks, and resource access, and implements bus-independent debugging and monitoring data paths in a message-passing manner. The driver module includes a board driver and a universal driver. The board driver is for the operation functions of the DSP board hardware environment, and the universal driver is applicable to the operation functions of the DSP chip.

[0074] The host software module also includes: a host top-level module, a thread module and a host driver module; the thread module connects the host top-level module and the host driver module; the host top-level module is used to distinguish each of the DSP software modules and establish a corresponding relationship between each DSP and the corresponding thread; the host driver module is used to generate a corresponding driving signal according to a user's command; and the thread module is used to mobilize the corresponding DSP software module according to the driving signal.

[0075] It is understood that the top-level module consists of the main framework and graphical interface. The main framework includes object relationships and thread division, and the graphical interface includes a graphical user interface. The thread module includes control threads for calling drivers and controlling hardware operations. The driver module includes board drivers and universal drivers. The board drivers are specific to the 6678 board's operating functions, while the universal drivers are based on Windows operating drivers.

[0076] Specifically, the DSP function module includes a low-level driver library, a common vector algorithm library, a matrix access function library, etc. The low-level driver library includes an external high-speed function interface and an internal configuration module driver. The external high-speed function interface includes: SRIO operation interface, used for SRIO initialization, SRIO doorbell operation, SRIO DIO mode reading and writing, SRIO Maitain mode reading and writing, SRIOTYPE11 / TYPE9 reading and writing; PCIE operation access interface; DDR operation interface, used for DDR initialization function; Emif16 operation interface, based on Emif16 to access Norflash, Nandflash, FPGA interface; I2C operation interface, based on I2C to access E2Prom, SRIO Switch, temperature sensor, etc.; GPIO operation interface; SPI operation interface. The internal configuration module driver includes: interrupt operation interface, which is used for interrupt service function hooking, interrupt clearing, manual interrupt triggering, etc.; timer operation interface, which is used for timer setting and timer access; cache operation interface, which is used for cache enabling, cache invalidation, cache write-back, cache freezing, etc.; EDMA operation interface, which implements one-dimensional data access, two-dimensional data access, three-dimensional data access, subframe extraction, data transposition, data ping-pong operation, etc. based on EDMA.

[0077] The Common Vector Algorithm Library implements operations such as continuous memory copy, jump memory copy, increasing sequence generation, real vector parity merge, complex parity vector merge, real vector parity split, and complex vector parity split. The library provides a series of functions for efficiently processing vectorized data. Among them, continuous memory copy copies data from one continuous memory area to another continuous memory area. Jump memory copy skips certain elements or copies at a specific step size during memory copy. Increasing sequence generation generates an increasing sequence of values, such as [0, 1, 2, 3, ...]. Real vector parity merge merges the odd-indexed elements and even-indexed elements of two real vectors into a new vector. Complex parity merge merges the odd-indexed elements and even-indexed elements of two complex vectors into a new vector. Real vector parity split splits the odd-indexed elements and even-indexed elements of a real vector into two new vectors. Complex Vector Odd-Even Split: Splits the odd-indexed elements and even-indexed elements of a complex vector into two new vectors.

[0078] The basic vector processing functions include: complex vector dot multiplication by complex vector, which calculates the sum of the products of corresponding elements of two complex vectors; complex vector dot addition / dot subtraction, which calculates the sum / difference of corresponding elements of two complex vectors; complex vector conjugation, which calculates the conjugate of a complex vector (the real part remains unchanged, and the imaginary part is negated); complex vector dot multiplication / dot addition / dot subtraction by a constant, which multiplies, adds or subtracts a complex vector from a constant; complex vector squaring, which calculates the square of each element of a complex vector; complex vector summation, which calculates the sum of all elements of a complex vector; complex vector phase angle calculation, which calculates the phase angle (angle) of each element of a complex vector; real angle corresponding complex vector calculation, which generates the corresponding complex vector based on the real angle (for example, angle θ corresponds to the complex number cosθ+isinθ); real vector logarithm calculation, which calculates the phase angle of each element of a real vector Logarithm of; Real vector summation, calculate the sum of all elements of a real vector; Real vector linear fit, perform linear fit on a real vector to find the best fitting line; Single-precision vector square root, calculate the square root of each element of a single-precision floating-point vector; Real vector absolute value, calculate the absolute value of each element of a real vector; Real vector mean, calculate the average value of all elements of a real vector; Real vector standard deviation, calculate the standard deviation of all elements of a real vector; Cos sequence generation, generate a cosine sequence, such as [cos(0), cos(1), cos(2), ...]; Sin sequence generation, generate a sine sequence, such as [sin(0), sin(1), sin(2), ...]; Sin_Cos sequence generation, generate both sine and cosine sequences.

[0079] A matrix access function library for real and complex matrix inversion, real and complex matrix addition, real and complex matrix dot multiplication, and real and complex matrix maximum and minimum. General signal processing algorithms for window function generation, CFAR detection, large-scale FFT transforms, pulse compression functions, and chirp signal generation.

[0080] Optionally, the FPGA, DSP and MCU on the board can be remotely updated by sending control commands and update codes to the host software module via the RS485 interface.

[0081] In this embodiment, the DSP functional unit simultaneously performs computations on multiple processed data signals based on an algorithm library. To meet the aforementioned technical requirements for software design, a layered approach was adopted in the development of the software platform, constructing a complete, universal, and scalable software development model. The DSP software module is divided into four relatively independent layers: the top-level module, the algorithm module, the communication module, and the driver module; and the host software module is divided into three layers: the top-level module, the thread module, and the driver module. The DSP functional unit features flexible addressing and high computational speed. Utilizing DSP technology for parameterized design, such as radar signal pulse and repetition rate, this accelerates information processing, reduces the number of data operations, and improves computational accuracy.

[0082] like Figure 4 FIG. 1 is a schematic structural diagram of a third embodiment of a heterogeneous integrated signal processing device for high-bandwidth signal acquisition proposed in this embodiment.

[0083] Based on the above-mentioned first embodiment and / or second embodiment, a third embodiment of the present invention is proposed, which is a heterogeneous integrated signal processing device for high-bandwidth signal acquisition.

[0084] The RFSOC functional unit includes: a synchronization unit and an ADC functional unit; the ADC functional unit is connected to the FPGA functional unit and the corresponding ADC application, and the synchronization unit is connected to the FPGA functional unit and the DSP functional unit; the ADC functional unit is used to transmit the data signals of each connected ADC application to the FPGA functional unit; the synchronization unit is used to cache the data signals of each unit using a buffer when the data signals reach the FPGA functional unit; and transmit the synchronized data signals to the DSP functional unit when the data signals stop inputting.

[0085] It is understandable that if Figure 4As shown, timestamp control bits are added to multiple ADCs. The JESD204 standard allows for the inclusion of "control bits" in sampled data to convey sample information from the transmitter to the receiver. In ADC applications, the control bits can be used as timestamps, marking samples that coincide with an external reference signal. The SYNC~ signal can also be used in multiple ADC applications connected to a single logic device. The synchronization unit requires multi-chip synchronization, provides an external reference signal to the ADC, and supports the control bits in the JESD204 transmitter. The JESD204 standard is a high-speed serial interface for data transmission between data converters (such as ADCs and DACs) and logic devices (such as FPGAs or ASICs). JESD204B and subsequent versions introduce a deterministic latency mechanism to ensure repeatable and deterministic latency from one power cycle to the next. The SYNC~ signal is a key signal in the JESD204 standard for synchronizing receivers and transmitters.

[0086] It should be noted that once all ADC applied samples are time stamped, downstream logic devices can Figure 5 Sample alignment is performed as shown. The accuracy and reliability of deterministic latency in a JESD204B system depends on the relationship between the device clock and SYSREF. The device clock is the system reference clock that provides the sampling clock (generally), the JESD204B clock, and the serializer clock. It is used to capture SYSREF and perform phase alignment of the leading edge of the frame and multiframe clocks, as shown in Figure 1. Figure 6 The JESD204B standard provides requirements and recommendations for SYSREF and device clock.

[0087] Specifically, in ADC applications, the SYNC~ deassertion signal is captured by the detection clock (usually the device clock) and used to reset the phase of its LMFC. After detecting and capturing the SYNC~ signal, in addition to resetting its local LMFC, the JESD204B transmitter will also begin sending K28.5 characters and will continue to do so until the system clock is established. After the clock is established, the ILAS portion of the synchronization process will begin at the LMFC boundary. In the ADC system, the LMFC alignment operation of the ADC is not an iterative process and is completed by a single assertion of SYNC~, such as Figure 7As shown in the figure, a periodic SYNC signal can also be used to monitor the phase alignment of the transmitter's LMFC. LMFC is a local clock signal within the device that defines the boundaries of a multi-frame, each containing a fixed number of frames. ILAS is a specific data sequence used to align multiple data lanes during the JESD204B initialization phase. ILAS ensures that all lanes are synchronized before data transmission begins, including frame synchronization, multi-frame synchronization, and inter-lane alignment, laying the foundation for subsequent high-speed data transmission.

[0088] The plurality of ADC functional units are all connected to the same clock, and the clock signals output by the clock have the same phase when arriving at each of the ADC applications.

[0089] It's understood that all ADC applications must use the same clock, with the same reference serving as the sampling drive clock. Furthermore, the phase of the clock reaching each ADC application must be aligned as closely as possible. Phase deviation between clocks directly translates to sampling synchronization deviation. Hardware design must ensure that multiple ADCs use the same clock source. Hardware routing errors and system errors can be accurately calculated and compensated for.

[0090] The SYSREF design of the JESD204B interface ADC is as follows Figure 8 The JESD204B standard allows for the inclusion of "control bits" in sampled data to convey sample information from the transmitter to the receiver. In ADC applications, the control bits can be used as "timestamps," marking samples that coincide with an external reference signal, as shown in the figure below. The fundamental requirement for multichip synchronization is providing an external reference signal, SYSREF, to the ADC and supporting the control bits in the JESD204B transmitter.

[0091] The synchronization unit is further configured to add a timestamp control bit to the data of each unit and perform frame clock phase synchronization via the timestamp control bit.

[0092] It can be understood that by using the additional control bits as triggers (marked to coincide with the front-end analog input) and adding time stamp samples, the FPGA can align signal chain samples with different delays, such as Figure 9 shown.

[0093] Specifically, the synchronization unit generates synchronization characters in each channel 204B through synchronization control. After the data of each channel reaches the receiving end FGPA, it will be cached in the buffer of each channel until all the data are together and then enter the internal logical link. Figure 10As shown in Figure 1, within the JES204B transmitter, the samples are aligned to the frame and multiframe clocks after the clock latches onto the system reference (SYSREF) edge. For clarity, the multiframe defined in this article consists of only 8 samples. Finally, the frame clock phase alignment is performed using SYSREF as shown in Figure 1. Figure 11 shown.

[0094] In this embodiment, the heterogeneous integrated signal processing device proposed in this patent brings significant benefits to the field of high-bandwidth signal processing through multi-dimensional technological innovation. In terms of technical performance, it adopts a three-dimensional heterogeneous architecture of DSP+FPGA+RFSoC to break through the bottleneck of traditional single-chip computing power and achieve high instantaneous bandwidth processing capabilities, which is more than 3 times higher than the existing discrete solution. It also supports flexible switching of multiple scenarios such as radar beamforming and communication signal demodulation through a dynamic reconstruction mechanism. In terms of system reliability, in conjunction with the status monitoring network of the BMC module, sub-millisecond fault location and redundant switching can be achieved, and the system MTBF (mean time between failures) is increased to more than 5,000 hours. In terms of energy efficiency control, the intelligent power consumption control strategy implemented by the domestic MCU reduces dynamic power consumption to meet the requirements of harsh environments such as airborne and satellite-borne.

[0095] It should be noted that, in this document, the terms "comprises," "includes," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, article, or system comprising a series of elements includes not only those elements but also other elements not explicitly listed, or elements inherent to such process, method, article, or system. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, method, article, or system comprising the element.

[0096] The present invention also proposes a signal processor, which includes a heterogeneous integrated signal processing device for high-bandwidth signal acquisition. The specific structure of the device refers to the above-mentioned embodiment. Since the maintenance auxiliary prompt device adopts all the technical solutions of all the above-mentioned embodiments, it has at least all the beneficial effects brought by the technical solutions of the above-mentioned embodiments, which will not be repeated here.

[0097] The above description is merely an exemplary embodiment of the present invention and does not limit the patent scope of the present invention. Any equivalent structural transformation made by utilizing the contents of the present invention's description and drawings under the technical concept of the present invention, or directly / indirectly applied in other related technical fields, is included in the patent protection scope of the present invention.

Claims

1. A heterogeneous integrated signal processing device for high-bandwidth signal acquisition, characterized in that: The device comprises: an FPGA functional unit, a DSP functional unit and an RFSOC functional unit; The FPGA functional unit is connected to the DSP functional unit, the RFSOC functional unit and a connector, the DSP functional unit is further connected to the RFSOC functional unit and the connector, and the RFSOC functional unit is connected to each ADC application; The RFSOC functional unit is used to synchronize the received data signals of the ADC applications and transmit them to the FPGA functional unit when the synchronization is completed; The FPGA functional unit is used to pre-process the data signal; The RFSOC functional unit is used to perform multi-channel digital down-conversion processing on the pre-processed data signal; The DSP functional unit is used to perform calculation processing on the multiple processed data signals simultaneously according to the algorithm library.

2. The heterogeneous integrated signal processing device for high-bandwidth signal acquisition according to claim 1, characterized in that: The DSP functional unit further includes: a host software module and a DSP software module; The DSP software module is also connected to the RFSOC functional unit, the connector and the host software module; The host software module is configured to receive a control instruction input by a user and output the control instruction to the corresponding DSP software module; The DSP software module is used to perform corresponding operations according to the control instructions.

3. The heterogeneous integrated signal processing device for high-bandwidth signal acquisition according to claim 2, characterized in that: The DSP software module also includes: a top-level module, an algorithm module, a communication module and a driver module; The algorithm module connects the top-level module and the communication module, and the driver module connects the communication module and each unit; The top-level module is configured to receive the control instructions from the host software module and transmit the control instructions to the algorithm module; The algorithm module is used to process the control instruction through the algorithm library to obtain the driving signal; The communication module is used to receive and transmit the driving signal to each of the DSP software modules; The driving module is used to drive corresponding hardware resources using an operation function according to the driving signal.

4. The heterogeneous integrated signal processing device for high-bandwidth signal acquisition according to claim 3, characterized in that: The host software module also includes: a host top-level module, a thread module and a host driver module; The thread module connects the host top-level module and the host driver module; The host top-level module is used to distinguish each of the DSP software modules and establish a corresponding relationship between each of the DSPs and the corresponding threads; The host driving module is used to generate corresponding driving signals according to user commands; The thread module is used to mobilize the corresponding DSP software module according to the driving signal.

5. The heterogeneous integrated signal processing device for high-bandwidth signal acquisition according to claim 3, characterized in that: The RFSOC functional unit includes: a synchronization unit and an ADC functional unit; The ADC functional unit is connected to the FPGA functional unit and the corresponding ADC application, and the synchronization unit is connected to the FPGA functional unit and the DSP functional unit; The ADC functional unit is configured to transmit data signals of the connected ADC applications to the FPGA functional unit; The synchronization unit is used to cache the data signal of each unit using a buffer when the data signal reaches the FPGA functional unit; and transmit the synchronized data signal to the DSP functional unit when the data signal stops inputting.

6. The heterogeneous integrated signal processing device for high-bandwidth signal acquisition according to claim 5, characterized in that: The plurality of ADC functional units are all connected to the same clock, and the clock signals output by the clock have the same phase when arriving at each of the ADC applications.

7. The heterogeneous integrated signal processing device for high-bandwidth signal acquisition according to claim 6, characterized in that: The synchronization unit is further configured to add a timestamp control bit to the data of each unit and perform frame clock phase synchronization via the timestamp control bit.

8. The heterogeneous integrated signal processing device for high-bandwidth signal acquisition according to claim 3, characterized in that: The device further comprises: an MCU functional unit; The MCU functional unit is connected to the DSP functional unit, the FPGA functional unit and the connector; The MCU functional unit is used to collect status information of each unit and adjust the power consumption of each unit according to the status information.

9. The heterogeneous integrated signal processing device for high-bandwidth signal acquisition according to claim 8, characterized in that: The MCU functional unit is also used to locate and repair faults.

10. A signal processor, characterized in that: It comprises a heterogeneous integrated signal processing device for high-bandwidth signal acquisition as described in any one of claims 1 to 9.

Images