Gate driver and display device including the same

Abstract

The invention discloses a gate driver and a display device including the same. The gate driver includes a plurality of stages. An nth stage of the plurality of stages includes: a pull-up transistor configured to control a flow of current between an output node and an input terminal of an nth clock based on a voltage of a Q node; a pull-down transistor configured to control a flow of current between the output node and an input terminal of a first low power supply based on a voltage of a QB node; and a QB node controller configured to control a voltage of the QB node based on a voltage of a control power supply and a voltage of the Q node, where the voltage of the control power supply has an on level in a vertical active period of one frame and an off level in a vertical blanking period of one frame.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of Korean Patent Application No. 10-2024-0020502, filed on February 13, 2024, which is hereby incorporated by reference as if fully set forth herein. Technical Field

[0003] The present invention relates to a gate driver and a display device including the gate driver. Background Art

[0004] The display device includes a plurality of pixels arranged in a matrix form and provides image data synchronized with a scan signal to the pixels, thereby adjusting the brightness of the pixels. The display device generates a scan signal by using a gate driver including a plurality of gate stages. Each of the gate stages of the gate driver is connected to a gate line of the display panel. Each gate stage includes a plurality of transistors and outputs a scan signal that swings between a scan-on voltage and a scan-off voltage to the gate line of the display panel.

[0005] Since the number of gate lines increases as the resolution of a display screen having a certain size increases, the number of gate stages increases in a high-resolution display device. When the number of gate stages increases, the area of the frame region including the gate stages may inevitably increase. For this reason, there is a limit to reducing the frame of the display device. Summary of the Invention

[0006] In order to solve the above-mentioned problems of the related art, the present invention may provide a gate driver and a display device including the gate driver, in which the construction of a gate stage may be simplified, thereby achieving a narrow frame.

[0007] To achieve these objects and other advantages, in accordance with the intent of the present invention, as embodied and broadly described herein, a gate driver includes a plurality of stages. An nth stage of the plurality of stages includes: a pull-up transistor configured to control the flow of current between an output node and an input terminal of an nth clock based on a voltage at a Q node; a pull-down transistor configured to control the flow of current between the output node and an input terminal of a first low power supply based on a voltage at a QB node; and a QB node controller configured to control the voltage of the QB node based on a voltage of a control power supply and the voltage of the Q node, wherein the voltage of the control power supply has an on-level in a vertical active period of one frame and has an off-level in a vertical blanking period of one frame.

[0008] On the other hand, a display device is provided, comprising: a display panel including a plurality of gate lines; and a gate driver including a plurality of stages, the plurality of stages being connected to the plurality of gate lines, wherein the nth stage of the plurality of stages comprises: a pull-up transistor configured to control the flow of current between an output node and an input terminal of an nth clock based on a voltage of a Q node; a pull-down transistor configured to control the flow of current between the output node and an input terminal of a first low power supply based on a voltage of a QB node; and a QB node controller configured to control the voltage of the QB node based on a voltage of a control power supply and the voltage of the Q node, wherein the voltage of the control power supply has an on-level in a vertical effective period of one frame and has an off-level in a vertical blanking period of one frame. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The accompanying drawings, which provide a further understanding of the present invention and are incorporated in and constitute a part of this application, illustrate embodiments of the present invention and, together with the description, serve to explain the principles of the present invention. In the drawings:

[0010] Figure 1 is a diagram illustrating a display device according to an embodiment of the present invention;

[0011] Figure 2 It is a schematic diagram in Figure 1 A diagram of an equivalent circuit of a pixel provided in a display panel;

[0012] Figure 3 is a diagram illustrating a gate stage connected to a gate line;

[0013] Figure 4 is a diagram illustrating an n-th gate stage connected to an n-th gate line;

[0014] Figure 5 is a diagram illustrating a driving signal for driving an nth gate stage;

[0015] Figure 6 and 7 is a diagram illustrating the operation of the nth gate stage during a first period;

[0016] Figure 8 and 9 is a diagram illustrating the operation of the nth gate stage during the second period;

[0017] Figure 10 and 11 is a diagram illustrating the operation of the nth gate stage during a third period;

[0018] Figure 12 and 13 is a diagram illustrating the operation of the nth gate stage during a fourth period;

[0019] Figure 14 and 15 is a diagram illustrating the operation of the n-th gate stage during the fifth period. DETAILED DESCRIPTION

[0020] The present invention will be described more fully hereinafter with reference to the accompanying drawings, in which exemplary embodiments of the invention are shown. However, the present invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the inventive concept to those skilled in the art.

[0021] The advantages and features of the present invention and their implementation methods will become apparent from the following detailed description with reference to the accompanying drawings. However, the present invention may be embodied in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the scope of the present invention to those skilled in the art. Furthermore, the present invention is limited only by the scope of the claims.

[0022] The shapes, sizes, proportions, angles, quantities, etc. disclosed in the accompanying drawings for describing various embodiments of the present invention are merely examples, and the present invention is not limited thereto. Similar reference numerals refer to similar elements throughout. Throughout this specification, identical elements are referred to by identical reference numerals. As used herein, the terms "include," "have," "comprise," etc. imply that additional parts may be added unless used with the term "only." As used herein, the singular is intended to include the plural unless the context clearly indicates otherwise.

[0023] Even if not explicitly stated, the elements in the embodiments of the present invention should be construed as including an error margin.

[0024] When describing a positional relationship, for example, when the positional relationship between two parts is described as "on", "above", "below", or "after", one or more other parts may be disposed between the two parts unless "just" or "directly" is used.

[0025] It will be understood that although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element without departing from the scope of the present invention.

[0026] In the present invention, the pixel circuit and gate driver provided on the substrate of the display panel can be implemented using transistors having an N-type metal oxide semiconductor field effect transistor (MOSFET), but is not limited thereto. The transistor can be a three-electrode element including a gate, a source, and a drain. The source can be an electrode that provides carriers to the transistor. In the transistor, carriers can flow from the source. The drain can be an electrode that allows carriers to flow out of the transistor. That is, in a MOSFET, carriers flow from the source to the drain. In an NMOS, since the carriers are holes, the source voltage can be higher than the drain voltage, so that holes flow from the source to the drain. In an NMOS, since holes flow from the drain to the source, current can flow from the drain to the source. It should be noted that the source and drain of a MOSFET are not fixed. For example, the source and drain of a MOSFET can switch between them. Therefore, when describing the embodiments of the present invention, one of the source and drain can be described as a first electrode, and the other of the source and drain can be described as a second electrode.

[0027] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. The following description will primarily focus on an organic light-emitting display device including an organic light-emitting material among electroluminescent display devices. However, it should be noted that the inventive concept is not limited to organic light-emitting display devices and can also be applied to inorganic light-emitting display devices including inorganic light-emitting materials.

[0028] Figure 1 is a diagram illustrating a display device according to an embodiment of the present invention. Figure 2 It is a schematic diagram in Figure 1 A diagram of an equivalent circuit of a pixel provided in a display panel. Figure 3 is a diagram illustrating a gate stage connected to a gate line.

[0029] Reference Figure 1 The display device according to the embodiment of the present invention may include a display panel 100, a timing controller 110, a data driver 120, a gate driver 130, and a level shifter 150. The display device according to the embodiment of the present invention may be implemented as an electroluminescent display device, but is not limited thereto.

[0030] In the display panel 100, as in Figure 2In the embodiment of the present invention, the pixels PXL connected to the data lines 14 and the gate lines 15 can be arranged in a matrix to form a pixel array. A plurality of horizontal pixel rows can be included in the pixel array, and a plurality of pixels PXL that are horizontally adjacent to each other and commonly connected to the gate line 15 can be arranged in each horizontal pixel row. Here, a horizontal pixel row may refer to a group of pixels in a horizontal row implemented by horizontally adjacent pixels PXL, rather than a physical signal line. The pixel array may include a power supply line for transmitting a high-level pixel source voltage EVDD to the pixels PXL. In addition, the pixels PXL can be further connected to a low-level pixel source voltage EVSS.

[0031] As in Figure 2 In the embodiment, each pixel PXL may include a light-emitting device OLED and a pixel driving circuit PCC for driving the light-emitting device OLED. The pixel driving circuit PCC may include: a driving element that generates a driving circuit to be applied to the light-emitting device OLED; and a switching circuit connected to the driving element. The switching circuit can set and maintain the gate-source voltage of the driving element. To this end, the switching circuit can be provided with a data voltage Vdata via the data line 14, a gate signal Gout via the gate line 15, and a high-level pixel source voltage EVDD via the power line, thereby setting the gate-source voltage of the driving element. The gate of the switching element included in the switching circuit can be connected to the gate line 15, and the first electrode (or second electrode) of the switching element included in the switching circuit can be connected to the data line.

[0032] Each pixel PXL can be one of a red pixel, a green pixel, a blue pixel, and a white pixel. The red pixel, the green pixel, the blue pixel, and the white pixel can constitute a unit pixel and can realize various colors. The color realized in the unit pixel can be determined based on the luminous efficiency of each of the red pixel, the green pixel, the blue pixel, and the white pixel. In addition, the white pixel can be omitted. In this case, the unit pixel can be configured using a red pixel, a green pixel, and a blue pixel. In addition, the number of gate lines 15 connected to the pixel PXL can be singular or plural.

[0033] Reference Figure 1The data driver 120 may receive image data DATA and a source timing control signal DDC from the timing controller 110. In response to the source timing control signal DDC from the timing controller 110, the data driver 120 may convert the image data DATA into a gamma compensation voltage to generate a data voltage Vdata, and may provide the data voltage Vdata to the data line 14 of the display panel 100 based on the timing of providing the gate signal Gout. The data driver 120 may be connected to the data line 14 of the display panel 100 via a chip-on-glass (COG) process or a tape automated bonding (TAB) process. The data driver 120 may be divided into a plurality of data drivers, but is not limited thereto, and may be provided as one data driver.

[0034] Reference Figure 1 The level shifter 150 may generate a gate timing control signal GDC for driving a switching element of a pixel based on an on / off control clock having a transistor-transistor-logic (TTL) level and input from the timing controller 110. The gate timing control signal GDC may include a start signal and a clock signal that swing between an on level and an off level. The level shifter 150 may provide the gate timing control signal GDC to the gate driver 130.

[0035] Reference Figures 1 to 3 The gate driver 130 may operate based on the gate timing control signal GDC input from the level shifter 150 to generate a gate signal Gout required for driving the pixel PXL. In addition, the gate driver 130 may provide the gate signal Gout to the gate line 15.

[0036] The gate driver 130 may be directly disposed on the lower substrate of the display panel 100 by using a gate-in-panel (GIP) type. The gate driver 130 may be disposed in a non-display area (i.e., a bezel area BZ) located outside the screen of the display panel 100. In the GIP type, the level shifter 150 may be mounted on a printed circuit board (PCB) 140 together with the timing controller 110.

[0037] The gate driver 130 may include a plurality of gate stages STG connected to each other based on a cascade mechanism. Each of the plurality of gate stages STG may be connected to a corresponding gate line 15 and may output a gate signal Gout to the corresponding gate line 15.

[0038] Some gate stages of the plurality of gate stages STG may be based on a start signal ( Figure 5 Furthermore, each of the other gate stages except these gate stages may start operating based on the output of the previous gate stage that operates before it (ie, the previous carry signal).

[0039] The gate driver 130 may be disposed in two bezel zones BZ facing the display panel 100 and may provide a scan signal to each gate line based on a dual feeding mechanism, thereby minimizing signal distortion caused by a load deviation of each gate line.

[0040] Reference Figure 1 The timing controller 110 can be connected to an external host system through various interface types known to those skilled in the art. The timing controller 110 can receive video data DATA from the host system, correct the video data DATA to compensate for brightness deviation caused by electrical characteristic differences, and transmit the corrected video data to the data driver 120.

[0041] The timing controller 110 may receive timing signals such as a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a data enable signal DE, and a main clock MCLK from a host system, and may generate an on / off control clock based on a source timing control signal DDC and a gate timing control signal GDC based on the timing signals.

[0042] Figure 4 is a diagram illustrating an n-th gate stage STG(n) connected to an n-th gate line; Figure 5 is a diagram illustrating a driving signal for driving the n-th gate stage STG(n).

[0043] Reference Figure 4 and 5 , in the nth gate stage STG(n), the voltage of the control power supply VDD applied to the second block BK2 can use an alternating current (AC) voltage instead of a direct current (DC) voltage so as to reduce the number of transistors included in the second block BK2, where n is an integer greater than 4.

[0044] In the related art, an additional transistor driven based on the VDD_DC voltage and the AC control signal to precharge the QB node is required to control the QB node.

[0045] The AC-type control power supply VDD according to an embodiment of the present invention can replace the VDD_DC voltage and the AC control signal. According to an embodiment of the present invention, the additional transistor of the related art for precharging the QB node can be omitted. In an embodiment of the present invention, the AC-type control power supply VDD with a conduction level can be applied to the QB node through transistors T4 and T6.

[0046] The voltage of the AC type control power source VDD (VDD_AC) according to the embodiment of the present invention may be input at an on level Lon in a vertical active period VA of one frame, and may be input at an off level Loff in a vertical blanking period VB of one frame.

[0047] The configuration of the n-th gate stage STG(n) will be described in detail below.

[0048] The n-th gate stage STG(n) may include a first block BK1 , a second block BK2 , a third block BK3 , and a fourth block BK4 .

[0049] The first block BK1 may be a Q-node controller for controlling the voltage of the Q-node. The Q-node controller may be configured to control the voltage of the Q-node based on a carry signal and the voltage of the QB node. The first block BK1 may include: a transistor T1 connected to the Q-node and an input terminal of a carry signal Gout(n-4) input from the (n-4)th stage; a transistor T2 connected to the Q-node according to a carry signal Gout(n+6) input from the (n+6)th stage; and a transistor T3 connected to the Q-node according to a carry signal Gout(n+6) input from the (n+6)th stage. The carry signal may be used to charge the Q-node with a turn-on voltage, and the carry signal may be used to discharge the Q-node to a turn-off voltage. In an embodiment of the present invention, the output of the (n-4)th stage may be provided as a carry signal, and the output of the (n+6)th stage may be provided as a carry signal, but the inventive concept is not limited thereto. However, when the output of the (n+6)th stage is applied as the last-carry signal instead of the output of the (n-4)th stage, the Q-node charge retention time can be increased, thereby ensuring operational stability.

[0050] The gate and drain of transistor T1 may be connected to the input terminal of the carry signal Gout(n-4), and the source of transistor T1 may be connected to the Q node. The gate of transistor T2 may be connected to the input terminal of the carry signal Gout(n+6), the drain of transistor T2 may be connected to the Q node, and the source of transistor T2 may be connected to the input terminal of the second low power supply GVGL. The gate of transistor T3 may be connected to the QB node, the drain of transistor T3 may be connected to the Q node, and the source of transistor T3 may be connected to the input terminal of the second low power supply GVGL.

[0051] The second block BK2 may be a QB node controller for controlling the voltage of the QB node. The second block BK2 may include: a transistor T4 connected to the first control node Nx and the input terminal of the control power supply VDD; a transistor T5 connected to the first control node Nx and the input terminal of the second low power supply GVGL by using the voltage of the Q node; a transistor T6 applied to the voltage of the control power supply VDD to the QB node by using the voltage of the first control node Nx; and a transistor T7 connected to the QB node and the input terminal of the second low power supply GVGL by using the voltage of the Q node.

[0052] The gate and drain of transistor T4 may be connected to an input terminal of the control power supply VDD, and the source of transistor T4 may be connected to a first control node Nx. The gate of transistor T5 may be connected to the Q node, the drain of transistor T5 may be connected to the first control node Nx, and the source of transistor T5 may be connected to an input terminal of the second low power supply GVGL. The gate of transistor T6 may be connected to the first control node Nx, the drain of transistor T6 may be connected to an input terminal of the control power supply VDD, and the source of transistor T6 may be connected to the QB node. The gate of transistor T7 may be connected to the Q node, the drain of transistor T7 may be connected to the QB node, and the source of transistor T7 may be connected to an input terminal of the second low power supply GVGL.

[0053] The third block BK3 may be an output unit for outputting a gate signal Gout(n). The third block BK3 may include: a pull-up transistor PU that controls the flow of current between an input terminal of the nth clock CLK(n) and an output terminal NO based on a voltage at a Q node; and a pull-down transistor PD that controls the flow of current between an input terminal of a first low power supply AVGL and an output node NO based on a voltage at a QB node.

[0054] The gate of the pull-up transistor PU may be connected to the Q node, the drain of the pull-up transistor PU may be connected to the input terminal of the n-th clock CLK(n), and the source of the pull-up transistor PU may be connected to the output node NO. The gate of the pull-down transistor PD may be connected to the QB node, the drain of the pull-down transistor PD may be connected to the output node NO, and the source of the pull-down transistor PD may be connected to the input terminal of the first low power supply AVGL.

[0055] The fourth block BK4 may be a reset unit that resets the voltage of the output node NO to the voltage of the first low power supply AVGL and resets the voltage of the QB node to the voltage of the second low power supply GVGL during the vertical blank period VB.

[0056] The fourth block BK4 may include a transistor T8 connecting the QB node to the input terminal of the second low power supply GVGL based on the reset signal RST and a transistor T9 connecting the output node NO to the input terminal of the first low power supply AVGL based on the reset signal RST.

[0057] The gate of transistor T8 may be connected to the second control node Ny, the drain of transistor T8 may be connected to the QB node, and the source of transistor T8 may be connected to the input terminal of the second low power supply GVGL. The gate of transistor T9 may be connected to the second control node Ny, the drain of transistor T9 may be connected to the output node NO, and the source of transistor T9 may be connected to the input terminal of the first low power supply AVGL.

[0058] The QB node is maintained at the on-voltage level for a longer time than the Q node is maintained at the on-voltage level, and for this reason, the pull-down transistor PD may be easily degraded. The fourth block BK4 may reset the voltage of the QB node to the voltage of the second low power supply GVGL in the vertical blanking period VB based on the reset signal RST, thereby reducing the degradation in the pull-down transistor PD.

[0059] To this end, the reset signal RST may be input at the on-level Lon during a portion of the vertical blanking period VB, and may be input at the off-level Loff during the vertical active period VA and the rest of the vertical blanking period VB.

[0060] When the pull-down transistor PD degrades, an off-current may flow through the pull-down transistor PD in the off state. This off-current may distort the waveform of the gate signal Gout(n). To prevent the off-current of the pull-down transistor PD, the voltage of the first low power supply AVGL may be set to be greater than the voltage of the second low power supply GVGL. When the pull-down transistor PD is in the off state, the second low power supply GVGL may be connected to the gate of the pull-down transistor PD, and the first low power supply AVGL may be connected to the source of the pull-down transistor PD. At this time, when the voltage of the first low power supply AVGL is greater than the voltage of the second low power supply GVGL, the off-current may not flow in the pull-down transistor PD due to the reverse bias applied between the gate and source of the pull-down transistor PD.

[0061] The operation of the nth gate stage STG(n) can be divided into the first to fifth periods ( Figures 6 to 15 Here, the first to fourth time periods ( Figures 6 to 15 X1 to X4 in the figure may correspond to the vertical effective period VA, the fifth period ( Figures 6 to 15 X5) in may correspond to the vertical blanking period VB.

[0062] Figure 6 and 7 is a diagram illustrating the operation of the n-th gate stage STG(n) during the first period X1.

[0063] Reference Figure 6 and 7During the first period X1, the voltage of the control power supply VDD may be input at the on-level Lon, thereby turning on transistors T4 and T6. Based on the voltage of the control power supply VDD having the on-level Lon, the voltage of the QB node may have the on-level Lon. Based on the voltage of the QB node having the on-level Lon, transistor T3 and the pull-down transistor PD may be turned on. Based on the second low power supply GVGL connected via transistor T3, the voltage of the Q node may have the off-level Loff. Based on the first low power supply AVGL connected via the pull-down transistor PD, the voltage of the output node NO may have the off-level Loff.

[0064] Figure 8 and 9 is a diagram illustrating the operation of the n-th gate stage STG(n) during the second period X2.

[0065] Reference Figure 8 and 9 During the second period X2, transistor T1 can be turned on by the carry signal Gout(n-4) having the conduction level Lon, and the Q node can be charged at the conduction level Lon. Based on the voltage of the Q node having the conduction level Lon, transistor T5, transistor T7 and pull-up transistor PU can be turned on. As transistor T5 is turned on, the second low power supply GVGL can be connected to the first control node Nx, thereby turning off transistor T6. Even if the voltage of the control power supply VDD having the conduction level Lon is applied to the first control node Nx via transistor T4 during the second period X2, the voltage of the control power supply VDD having the conduction level Lon can be discharged to the voltage of the second low power supply GVGL via transistor T5. As transistor T7 is turned on, the voltage of the QB node can have the off level Loff. As the pull-up transistor PU is turned on, the clock signal CLK(n) having the off level Loff can be output to the output node NO.

[0066] Figure 10 and 11 is a diagram illustrating the operation of the n-th gate stage STG(n) during the third period X3.

[0067] Reference Figure 10 and 11, when the clock signal CLK(n) having the on-level Lon is input during the third period X3, the voltage of the Q node may be shifted from the on-level Lon to the bootstrap level Lbst based on the coupling of the parasitic capacitor connected between the gate and the drain of the pull-up transistor PU. The bootstrap level Lbst may be a voltage higher than the on-level Lon. When the voltage of the Q node shifts up to the bootstrap level Lbst, the on-response characteristic of the pull-up transistor PU may be accelerated. When the voltage of the Q node shifts up to the bootstrap level Lbst, the gate-source voltage of the pull-up transistor PU may increase, thereby increasing the amount of current flowing in the pull-up transistor PU. At this time, the clock signal CLK(n) having the on-level Lon may be output to the output node NO based on the conduction of the pull-up transistor PU, thereby becoming the gate signal Gout(n) having the on-level Lon.

[0068] Figure 12 and 13 is a diagram illustrating the operation of the n-th gate stage STG(n) during the fourth period X4.

[0069] Reference Figure 12 and 13 During the fourth period X4, transistor T2 may be turned on by the carry-after signal Gout(n+6) having the on-level Lon, and the Q node may be discharged to the off-level Loff. Based on the voltage of the Q node having the off-level Loff, transistor T5, transistor T7, and pull-up transistor PU may be turned off. As transistor T5 is turned off, transistor T6 may be turned on, whereby the voltage of the QB node may have the on-level Lon. Based on the voltage of the QB node having the on-level Lon, transistor T3 and pull-down transistor PD may be turned on. Based on the second low power supply GVGL connected via transistor T3, the voltage of the Q node may maintain the off-level Loff while transistor T3 is turned on. Based on the first low power supply AVGL connected via the pull-down transistor PD, the voltage of the output node NO may have the off-level Loff.

[0070] Figure 14 and 15 is a diagram illustrating the operation of the n-th gate stage STG(n) during the fifth period X5.

[0071] Reference Figure 14 and 15During the fifth period X5, the voltage of the control power supply VDD can be input at the off-level Loff, and the reset signal RST can be input at the on-level Lon. Transistors T8 and T9 can be turned on by the reset signal RST having the on-level Lon. As a result, the voltage of the QB node can be reset to the voltage of the second low power supply GVGL, and the output node NO can be reset to the first low power supply AVGL, thereby preventing abnormal operation (i.e., waveform distortion of the gate signal Gout(n)) caused by coupling of the external source voltage during the vertical blanking period VB. When the voltage of the QB node is reset to the voltage of the second low power supply GVGL in each vertical blanking period VB, degradation in transistors T3 and PD including the gate connected to the QB node can be reduced.

[0072] In the gate driver and the display device including the gate driver according to the embodiments of the present invention, the configuration of the gate stage can be simplified, and thus a narrow bezel can be achieved.

[0073] The effects according to the present invention are not limited to the above-described examples, and other various effects may be included in this specification.

[0074] While the invention has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as disclosed in the following claims.

Claims

1. A gate driver comprising a plurality of stages, wherein the nth stage of the plurality of stages comprises: a pull-up transistor configured to control a flow of current between the output node and an input terminal of an n-th clock based on a voltage of the Q node; a pull-down transistor configured to control a flow of current between the output node and an input terminal of a first low power supply based on a voltage of the QB node; as well as a QB node controller configured to control a voltage of the QB node based on a voltage of a control power source and a voltage of the Q node; The voltage of the control power source has an on-level in a vertical effective period of one frame and has an off-level in a vertical blanking period of one frame.

2. The gate driver according to claim 1 , wherein the QB node controller comprises: a fourth transistor connected to an input terminal of the control power supply and a first control node; a fifth transistor configured to connect the first control node to an input terminal of a second low power source based on a voltage of the Q node; a sixth transistor configured to apply a voltage of the control power supply to the QB node based on the voltage of the first control node; as well as a seventh transistor configured to connect the QB node to an input terminal of the second low power source based on the voltage of the Q node. 3 . The gate driver of claim 1 , further comprising a Q-node controller configured to control a voltage of the Q-node based on a carry signal and a voltage of the QB-node.

4. The gate driver according to claim 3, wherein the Q-node controller comprises: a first transistor connected to the Q node and an input terminal of a carry signal input from an (n-4)th stage; a second transistor configured to connect the Q node to an input terminal of a second low power source based on a last-carry signal input from an (n+6)th stage; as well as a third transistor configured to connect the Q node to an input terminal of the second low power source based on a voltage of the QB node.

5. The gate driver according to claim 1 , further comprising: an eighth transistor configured to connect the QB node to an input terminal of a second low power source based on a reset signal; as well as a ninth transistor configured to connect the output node to an input terminal of the first low power source based on the reset signal. 6 . The gate driver according to claim 5 , wherein the reset signal is input at an on-level during a portion of the vertical blanking period, and is input at an off-level during the vertical active period and the rest of the vertical blanking period. 7 . The gate driver according to claim 2 , wherein a voltage of the first low power source is greater than a voltage of the second low power source.

8. A display device comprising: A display panel including a plurality of gate lines; as well as a gate driver comprising a plurality of stages connected to the plurality of gate lines, wherein the nth level of the plurality of levels comprises: a pull-up transistor configured to control a flow of current between the output node and an input terminal of an n-th clock based on a voltage of the Q node; a pull-down transistor configured to control a flow of current between the output node and an input terminal of a first low power supply based on a voltage of the QB node; and a QB node controller configured to control a voltage of the QB node based on a voltage of a control power source and a voltage of the Q node; The voltage of the control power source has an on-level in a vertical effective period of one frame and has an off-level in a vertical blanking period of one frame.

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