Driving circuit for solving image color gradation fault

Abstract

The invention relates to a driving circuit for solving image color gradation faults. The driving circuit comprises an input module and a master control module, the master control module comprises a chip UP1 and an anti-interference unit, the anti-interference unit comprises a resistor R15, a capacitor C23 and an inductor L2, the input module is electrically connected with the chip UP1, the first end of the resistor R15 is electrically connected with the chip UP1, the second end of the resistor R15 is electrically connected with the first end of the capacitor C23, the second end of the capacitor C23 is grounded, and the first end of the capacitor C23 is grounded. The first end of the inductor L2 is electrically connected with the first end of the resistor R15, and the second end of the inductor L2 is electrically connected with the second end of the capacitor C23. According to the scheme provided by the invention, the anti-interference capability of the TCON logic board can be improved, so that the Gamma voltage is prevented from being influenced by external noise, and the problem of color gradation fault of a picture is solved.

Description

Technical Field

[0001] The present invention relates to the technical field of circuit design, and in particular to a driving circuit for solving color gradation discontinuity of a picture. Background Art

[0002] The TCON logic board, the core carrier of gamma voltage regulation, primarily addresses nonlinear brightness distortion and ensures accurate grayscale rendering. The TCON generates multiple sets of drive voltages through integrated circuits, precisely controlling the gamma deflection angles of the liquid crystal molecules to adjust light transmittance.

[0003] In related technologies, the TCON logic board has weak anti-interference capabilities, and external noise will affect the fluctuation of the Gamma voltage, causing color discontinuity in the picture, thereby affecting the authenticity of the picture. Summary of the Invention

[0004] The purpose of the present invention is to overcome the shortcomings of the prior art and provide a driving circuit to solve the problem of color gradation discontinuity of the picture, which can improve the anti-interference ability of the TCON logic board and prevent external noise from affecting the Gamma voltage, thereby solving the problem of color gradation discontinuity of the picture.

[0005] The object of the present invention is achieved through the following technical solutions:

[0006] In a first aspect, the present application provides a driving circuit for solving the problem of color gradation discontinuity in a picture, comprising: an input module; a main control module, comprising a chip UP1 and an anti-interference unit, wherein the anti-interference unit comprises a resistor R15, a capacitor C23 and an inductor L2, the input module being electrically connected to the chip UP1, a first end of the resistor R15 being electrically connected to the chip UP1, a second end of the resistor R15 being electrically connected to a first end of the capacitor C23, a second end of the capacitor C23 being grounded, a first end of the inductor L2 being electrically connected to a first end of the resistor R15, and a second end of the inductor L2 being electrically connected to a second end of the capacitor C23.

[0007] The input module includes a fuse F1, a voltage regulator diode DZ2, a capacitor C1, a capacitor C2 and a capacitor C3. The first end of the voltage regulator diode DZ2 is electrically connected to the fuse F1 and the first end of the capacitor C1 respectively, the second end of the voltage regulator diode DZ2 is electrically connected to the second end of the capacitor C1, the first end of the capacitor C2 is electrically connected to the first end of the capacitor C1, the second end of the capacitor C2 is electrically connected to the second end of the capacitor C1, the first end of the capacitor C3 is electrically connected to the first end of the capacitor C2, and the second end of the capacitor C3 is grounded.

[0008] The main control module also includes a capacitor C26 and a capacitor C27. The first end of the capacitor C26 is electrically connected to the chip UP1, the second end of the capacitor C26 is grounded, and the first end of the capacitor C27 is electrically connected to the first end of the capacitor C26 and the first end of the capacitor C3 respectively.

[0009] The main control module also includes a voltage processing unit, which includes an inductor L3, a voltage regulator DZ4, a capacitor C21, a capacitor C22 and a resistor R18. The first end of the inductor L3 is electrically connected to the first end of the capacitor C3, the second end of the inductor L3 is electrically connected to the first end of the voltage regulator DZ4, the second end of the voltage regulator DZ4 is electrically connected to the first end of the capacitor C21, the second end of the capacitor C21 is grounded, the first end of the capacitor C22 is electrically connected to the first end of the capacitor C21 and the chip UP1 respectively, the second end of the capacitor C22 is grounded, the first end of the resistor R18 is electrically connected to the second end of the inductor L3, and the second end of the resistor R18 is electrically connected to the chip UP1.

[0010] The main control module also includes a purification unit, which includes a capacitor C17, a resistor RJ1, a capacitor C41, a capacitor C42, a capacitor C43, a capacitor C44, an inductor L4 and a voltage regulator tube DZ5. The first end of the capacitor C17 is electrically connected to the chip UP1, and the second end of the capacitor C17 is grounded. The first end of the resistor RJ1 is electrically connected to the first end of the capacitor C17, the second end of the resistor RJ1 is electrically connected to the first end of the capacitor R41, and the second end of the capacitor C41 is grounded. 2 is electrically connected to the first end of the capacitor C41, the second end of the capacitor C42 is grounded, the first end of the capacitor C43 is electrically connected to the first end of the capacitor C42, the second end of the capacitor C43 is grounded, the first end of the capacitor C44 is electrically connected to the first end of the capacitor C43, the second end of the capacitor C44 is grounded, the first end of the inductor L4 is electrically connected to the first end of the capacitor C44, the second end of the inductor L4 is electrically connected to the voltage regulator tube DZ5, and the second end of the voltage regulator tube DZ5 is grounded.

[0011] The main control module further includes a resistor R13 and a capacitor C16. A first end of the resistor R13 is electrically connected to the chip UP1. A second end of the resistor R13 is electrically connected to a first end of the capacitor C16. A second end of the capacitor C16 is grounded.

[0012] The main control module also includes a MOS transistor Q1, a resistor R6, and a resistor R3. The gate of the MOS transistor Q1 is electrically connected to the chip UP1 and the first end of the resistor R6, respectively. The drain of the MOS transistor Q1 is electrically connected to the chip UP1 and the first end of the resistor R3, respectively. The second end of the resistor R3 is electrically connected to the second end of the resistor R6.

[0013] The main control module also includes a MOS transistor Q2, a capacitor C8, a capacitor C4, a capacitor C5, a capacitor C6, and a capacitor C7. The gate of the MOS transistor Q2, the first end of the capacitor C7, and the first end of the capacitor C8 are respectively electrically connected to the chip UP1. The first end of the capacitor C7 is also electrically connected to the drain of the MOS transistor Q2. The first end of the capacitor C8 is also electrically connected to the source of the MOS transistor Q2. The second end of the capacitor C7 and the second end of the capacitor C8 are respectively electrically connected to the gate of the MOS transistor Q2. The first end of the capacitor C4 is electrically connected to the first end of the capacitor C5. The second end of the capacitor C4 is grounded. The second end of the capacitor C5 is grounded. The first end of the capacitor C6 is respectively electrically connected to the first end of the capacitor C5 and the first end of the capacitor C7. The second end of the capacitor C6 is grounded.

[0014] The main control module also includes a resistor R7, a resistor R8, a resistor R9, a transistor Q3 and a transistor Q4. The resistor R7 is electrically connected to the collector of the transistor Q3, the first end of the resistor R8 is electrically connected to the chip UP1, and the second end of the resistor R8 is electrically connected to the base of the transistor Q3 and the base of the transistor Q4 respectively. The first end of the resistor R9 is electrically connected to the chip UP1, and the second end of the resistor R9 is electrically connected to the emitter of the transistor Q3 and the emitter of the transistor Q4 respectively.

[0015] The main control module further includes a resistor R12 , a first end of the resistor R12 is electrically connected to the collector of the transistor Q4 , and a second end of the resistor R12 is grounded.

[0016] Compared with the prior art, the present invention has at least the following advantages:

[0017] Resistor R15 and capacitor C23 form a high-frequency oscillation compensation circuit, and in conjunction with inductor L2 to ground, filter out low-frequency interference signals, reduce crosstalk signals from entering the circuit, enhance the anti-interference capability of the driving circuit, and avoid crosstalk signals affecting the gamma output of the LCD screen and causing color gradation discontinuity. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required for use in the embodiments.

[0019] Figure 1 A functional block diagram of a driving circuit for resolving image gradation discontinuity in one embodiment of the present invention;

[0020] Figure 2 FIG. 4 is a circuit diagram of a driving circuit for resolving image gradation discontinuity in one embodiment of the present invention. DETAILED DESCRIPTION

[0021] The following describes embodiments of the present application in more detail with reference to the accompanying drawings. Although the accompanying drawings illustrate embodiments of the present application, it should be understood that the present application can be implemented in various forms and should not be limited by the embodiments described herein. Rather, these embodiments are provided to make the present application more thorough and complete, and to fully convey the scope of the present application to those skilled in the art.

[0022] It should be understood that although the terms "first", "second", "third", etc. may be used in this application to describe various information, this information should not be limited to these terms. These terms are only used to distinguish information of the same type from each other. For example, without departing from the scope of this application, the first information may also be referred to as the second information, and similarly, the second information may also be referred to as the first information. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of this application, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0023] Unless otherwise expressly specified or limited, the terms "mounted," "connected," "connect," "fixed," and the like should be interpreted broadly. For example, they may refer to fixed connection, detachable connection, or integration; mechanical connection or electrical connection; direct connection or indirect connection through an intermediate medium; and internal communication between two components or interaction between two components. Those skilled in the art will understand the specific meanings of the above terms in this application based on the specific circumstances.

[0024] The TCON logic board has weak anti-interference ability, and external noise will affect the fluctuation of Gamma voltage, causing color level discontinuity in the picture, thus affecting the authenticity of the picture.

[0025] In response to the above problems, an embodiment of the present application provides a driving circuit for solving the problem of color gradation discontinuity in the picture, which can improve the anti-interference ability of the TCON logic board, thereby preventing external noise from affecting the Gamma voltage, thereby solving the problem of color gradation discontinuity in the picture.

[0026] The technical solutions of the embodiments of the present application are described in detail below with reference to the accompanying drawings.

[0027] See also Figure 1 and Figure 2A driving circuit for resolving color gradation discontinuity in an image includes an input module 100 and a main control module 200. The main control module 200 includes a chip UP1 and an anti-interference unit. The anti-interference unit includes a resistor R15, a capacitor C23, and an inductor L2. The input module 100 is electrically connected to the chip UP1. A first end of the resistor R15 is electrically connected to the chip UP1. A second end of the resistor R15 is electrically connected to a first end of the capacitor C23. A second end of the capacitor C23 is grounded. A first end of the inductor L2 is electrically connected to a first end of the resistor R15. A second end of the inductor L2 is electrically connected to a second end of the capacitor C23.

[0028] It should be noted that input module 100 receives the VIN voltage transmitted from the TCON logic board. The chip UP1 can be the EK86309A. Furthermore, the high-frequency oscillation compensation circuit composed of resistor R15 and capacitor C23, combined with the grounding of inductor L2, filters out low-frequency interference signals, reduces crosstalk signals from entering the circuit, strengthens the circuit's anti-interference capability, and prevents crosstalk signals from affecting the gamma output and causing color discontinuity on the LCD screen.

[0029] It should also be noted that the anti-interference unit also includes a diode DZ3, a capacitor C18, a capacitor C19, a capacitor C20, a resistor R14 and a resistor R16. The first end of the diode DZ3 is electrically connected to the first end of the inductor L2, and the second end of the diode DZ3 is electrically connected to the first end of the capacitor C18, the first end of the capacitor C19, and the first end of the capacitor C20, respectively. The second end of the capacitor C18, the second end of the capacitor C19, and the second end of the capacitor C20 are grounded respectively. The resistor R14 is electrically connected to the first end of the resistor R16, the first end of the resistor R16 is electrically connected to the first end of the capacitor C20, and the second end of the resistor R16 is grounded.

[0030] As you can understand, capacitors C18, C19, and C20 are filter capacitors, and resistors R14 and R16 are current-limiting resistors. The 8-pin output of chip UP1 retains a valid electrical signal after passing through the pre-filter circuit. Limiting diode DZ3 then limits the voltage amplitude to a safe range, protecting the TCON logic board from high voltage damage. The signal is then filtered by capacitors C18, C19, and C20, divided by the resistors R14 and R16 nodes, and combined with the 9-pin VGL signal output (VGL_OUT), a complete electrical signal that is ultimately provided to the central control processing screen signal on the TCON logic board.

[0031] See also Figure 2In one embodiment, the input module 100 includes a fuse F1, a voltage regulator diode DZ2, a capacitor C1, a capacitor C2, and a capacitor C3. The first end of the voltage regulator diode DZ2 is electrically connected to the first end of the fuse F1 and the first end of the capacitor C1, respectively. The second end of the voltage regulator diode DZ2 is electrically connected to the second end of the capacitor C1. The first end of the capacitor C2 is electrically connected to the first end of the capacitor C1. The second end of the capacitor C2 is electrically connected to the second end of the capacitor C1. The first end of the capacitor C3 is electrically connected to the first end of the capacitor C2. The second end of the capacitor C3 is grounded.

[0032] It's important to note that the VIN startup voltage transmitted by the TCON logic board first passes through fuse F1 and Zener diode DZ2 to block the pulse current input into the circuit. Fuse F1 prevents subsequent circuit breakdown and burnout, providing fuse protection. Zener diode DZ2 filters out voltage spikes to ground, preventing damage to sensitive components in the circuit. It also provides a reference voltage to capacitors C1, C2, and C3 for filtering to ground, outputting a stable operating voltage VIN12, which is then transmitted to chip UP1 to provide operating voltage.

[0033] See also Figure 2 In one embodiment, the main control module 200 further includes a capacitor C26 and a capacitor C27, a first end of the capacitor C26 is electrically connected to the chip UP1, a second end of the capacitor C26 is grounded, and a first end of the capacitor C27 is electrically connected to a first end of the capacitor C26 and a first end of the capacitor C3, respectively.

[0034] It should be noted that capacitor C26 and capacitor C27 play a filtering role.

[0035] See also Figure 2 In one embodiment, the main control module 200 further includes a voltage processing unit, which includes an inductor L3, a voltage regulator diode DZ4, a capacitor C21, a capacitor C22, and a resistor R18. The first end of the inductor L3 is electrically connected to the first end of the capacitor C3, the second end of the inductor L3 is electrically connected to the first end of the voltage regulator diode DZ4, the second end of the voltage regulator diode DZ4 is electrically connected to the first end of the capacitor C21, the second end of the capacitor C21 is grounded, the first end of the capacitor C22 is electrically connected to the first end of the capacitor C21 and the chip UP1 respectively, the second end of the capacitor C22 is grounded, the first end of the resistor R18 is electrically connected to the second end of the inductor L3, and the second end of the resistor R18 is electrically connected to the chip UP1.

[0036] It should be noted that the VIN12 voltage flows to the chip UP1 in two ways. Specifically, one of the ways is filtered by capacitors C26 and C27, and then connected to the 6pin and 7pin inputs of the chip UP1 as the power input of the chip UP1; the other way is connected to the LC filter circuit of capacitor C24 and inductor L3 to purify the voltage, first absorbing high-frequency noise through the voltage regulator DZ4, capacitor C21, and capacitor C22 components, and then connected to the 25pin of the chip UP1 to provide the driving voltage; at the same time, the inductor L3 is also connected to the current limiting resistor R18, providing a pull-up voltage to the 24pin to meet the working requirements of the built-in circuit of the chip UP1. After the power pin of the chip UP1 inputs a stable voltage, the TCON logic board outputs the PWON central control signal, which is transmitted to the 14pin enable pin EN of the chip UP1 to ensure that the enable pin EN is in a low level state when the circuit is powered on. The chip UP1 then starts the driving work of the built-in circuit to prevent the built-in circuit of the chip UP1 from starting up by mistake.

[0037] See also Figure 2 In one embodiment, the main control module 200 further includes a purification unit, which includes a capacitor C17, a resistor RJ1, a capacitor C41, a capacitor C42, a capacitor C43, a capacitor C44, an inductor L4, and a voltage regulator DZ5. A first end of the capacitor C17 is electrically connected to the chip UP1, and a second end of the capacitor C17 is grounded. A first end of the resistor RJ1 is electrically connected to a first end of the capacitor C17, a second end of the resistor RJ1 is electrically connected to a first end of the capacitor R41, a second end of the capacitor C41 is grounded, a first end of the capacitor C42 is electrically connected to a first end of the capacitor C41, a second end of the capacitor C42 is grounded, a first end of the capacitor C43 is electrically connected to a first end of the capacitor C42, a second end of the capacitor C43 is grounded, a first end of the capacitor C44 is electrically connected to a first end of the capacitor C43, a second end of the capacitor C44 is grounded, a first end of the inductor L4 is electrically connected to a first end of the capacitor C44, a second end of the inductor L4 is electrically connected to the voltage regulator DZ5, and a second end of the voltage regulator DZ5 is grounded.

[0038] It should be noted that after the chip UP1 enters the working state, the 10-pin external capacitor C17 of the chip UP1 filters the output VCC3V3 voltage to the ground, and then connects one end of the resistor RJ1 for current limiting. The other end is combined with the VBK1 signal output by the 2-pin of the chip UP1. The voltage is purified by the LC filter circuit composed of capacitors C41, C42, C43, C44, and inductor L4, and then the reference voltage of the voltage regulator DZ5 is connected to output the LXBK1 electrical signal, which is then transmitted back to the 4-pin of the chip UP1.

[0039] See also Figure 2In one embodiment, the main control module 200 further includes a resistor R13 and a capacitor C16, a first end of the resistor R13 is electrically connected to the chip UP1, a second end of the resistor R13 is electrically connected to a first end of the capacitor C16, and a second end of the capacitor C16 is grounded.

[0040] It should be noted that the 22-pin external resistor R13 and capacitor C16 of chip UP1 form an RC series circuit to provide a compensation voltage to the built-in boost converter of chip UP1.

[0041] See also Figure 2 In one embodiment, the main control module 200 further includes a MOS transistor Q1, a resistor R6, and a resistor R3. The gate of the MOS transistor Q1 is electrically connected to the chip UP1 and the first end of the resistor R6, respectively. The drain of the MOS transistor Q1 is electrically connected to the chip UP1 and the first end of the resistor R3, respectively. The second end of the resistor R3 is electrically connected to the second end of the resistor R6.

[0042] It should be noted that the 23Pin of the chip UP1 is connected to the gate control pin of the MOS tube Q1 and the pull-down resistor R6, and then the CS signal output by the 24Pin of the chip UP1 is connected to the drain pin of the MOS tube Q1. The MOS tube Q1 combines the control signal and outputs the MOS_D signal through the source to the central control processing of the TCON logic board.

[0043] See also Figure 2 In one embodiment, the main control module 200 further includes a MOS transistor Q2, a capacitor C8, a capacitor C4, a capacitor C5, a capacitor C6, and a capacitor C7. The gate of the MOS transistor Q2, the first end of the capacitor C7, and the first end of the capacitor C8 are electrically connected to the chip UP1, respectively. The first end of the capacitor C7 is also electrically connected to the drain of the MOS transistor Q2. The first end of the capacitor C8 is also electrically connected to the source of the MOS transistor Q2. The second end of the capacitor C7 and the second end of the capacitor C8 are electrically connected to the gate of the MOS transistor Q2, respectively. The first end of the capacitor C4 is electrically connected to the first end of the capacitor C5. The second end of the capacitor C4 is grounded. The second end of the capacitor C5 is grounded. The first end of the capacitor C6 is electrically connected to the first end of the capacitor C5 and the first end of the capacitor C7, respectively. The second end of the capacitor C6 is grounded.

[0044] It should be noted that the 26-pin output SWG signal of chip UP1 is connected to the gate control pin of MOS tube Q2, capacitor C7, and the second end of capacitor C8. The 27-pin output SWO signal of chip UP1 is combined with the front-stage voltage compensation VCC3V3 voltage, filtered by capacitors C4, C5, and C6, and then grounded and connected to the drain pin of Q2 and the first end of capacitor C7. The source output SWI signal of MOS tube Q2 is connected to the first end of capacitor C8, and the signal is fed back to the built-in circuit of 25-pin input chip UP1.

[0045] See also Figure 2 In one embodiment, the main control module 200 further includes a resistor R7, a resistor R8, a resistor R9, a transistor Q3, and a transistor Q4. The resistor R7 is electrically connected to the collector of the transistor Q3. The first end of the resistor R8 is electrically connected to the chip UP1. The second end of the resistor R8 is electrically connected to the base of the transistor Q3 and the base of the transistor Q4, respectively. The first end of the resistor R9 is electrically connected to the chip UP1. The second end of the resistor R9 is electrically connected to the emitter of the transistor Q3 and the emitter of the transistor Q4, respectively.

[0046] Specifically, the main control module 200 further includes a resistor R12 , a first end of the resistor R12 is electrically connected to the collector of the transistor Q4 , and a second end of the resistor R12 is grounded.

[0047] It should be noted that the 28-pin output HAVDD signal of chip UP1 is connected to the first ends of resistors R8 and R9, and the base pins of transistors Q3 and Q4 are controlled through the second end of resistor R8. The collector of transistor Q3 is connected to the bias voltage of voltage VCC3V3 through pull-up resistor R7, and the collector of transistor Q4 is connected to the pull-down resistor R12 and grounded. The second end of resistor R9 is connected to the emitter pins of transistors Q3 and Q4; the HAVDD signal controls the working status of transistors Q3 and Q4 respectively, so that transistors Q3 and Q4 are cross-conducted to output HVAA signal, which is fed back to the 29-pin of chip UP1 for processing.

[0048] It should also be noted that the chip UP1 receives the I2C communication signal transmitted by the TCON logic board, and outputs the Gamma signal from Pin 32-45 to the LCD screen to display the real picture.

[0049] See also Figure 2 In another embodiment, the main control module 200 further includes a temperature compensation unit, which includes a capacitor C31, a resistor R21, a resistor R22, and a thermistor R23. A first end of the capacitor C31 is electrically connected to the chip UP1, and a second end of the capacitor C31 is grounded. A first end of the resistor R21 is electrically connected to a first end of the capacitor C31, and a second end of the resistor R21 is electrically connected to a first end of the resistor R22 and a first end of the thermistor R23, respectively. A second end of the resistor R22 is grounded, and a second end of the thermistor R23 is grounded.

[0050] It should be noted that the 1-pin built-in power regulator pin of chip UP1 is connected to an external capacitor C31 for filtering, then connected to resistors R21 and R22 for node voltage division. The output reference voltage is then provided to negative temperature thermistor R23 for temperature detection. When the ambient temperature changes, such as when the temperature rises, the number of carriers in the germanium and silicon semiconductor materials built into thermistor R23 increases, causing the resistance value to decrease. Conversely, the resistance value is maximum at room temperature. The temperature compensation unit combines the voltage change of negative temperature thermistor R23 and feeds it back to the 5-pin built-in circuit of chip UP1 for processing, preventing the gamma voltage from drifting zero when the TCON logic board is in high temperature conditions, thereby controlling the output of the gamma signal.

[0051] Specifically, when thermistor R23 senses a change in ambient temperature, the resistance of its internal material structure changes. Simultaneously, the node voltage between resistors R21 and R22 is output to thermistor R23, generating a real-time temperature-dependent voltage value that is connected to the 5-pin feedback input of chip UP1. The purpose here is to convert the NTC resistance into a voltage value. After receiving the temperature-dependent voltage, chip UP1 collects it and sends it to the built-in ADC module for digitization and software correction. The LMS algorithm can be used to estimate the real-time voltage drift and calculate the compensation in real time. The built-in output reference voltage or gain parameters are adjusted to offset the voltage zero drift caused by temperature changes. Because chip UP1 has a temperature control interface pin, the real-time voltage change can be obtained based on the measured resistance value using the NTC temperature curve pre-stored in the IC. The output voltage is then adjusted based on the temperature coefficient of the target output circuit to compensate for the zero drift. Finally, the compensation voltage is provided to the VGH, VGL, and GAMMA signal outputs.

[0052] See also Figure 2 In another embodiment, the main control module 200 further includes a high-voltage protection unit, which includes a resistor R1, a capacitor C9, a capacitor C10, an inductor L1, a resistor R5, a capacitor C13, a diode DZ1, and a resistor R2. A first end of the resistor R1 is electrically connected to the chip UP1, a second end of the resistor R1 is electrically connected to the first end of the capacitor C9 and the first end of the capacitor C10, respectively, a second end of the resistor C9 is grounded, a second end of the capacitor C10 is grounded, a first end of the inductor L1 is electrically connected to the second end of the resistor R1, a second end of the inductor L1 is electrically connected to the first end of the resistor R5, a second end of the resistor R5 is electrically connected to the first end of the capacitor C13, a second end of the capacitor C13 is grounded, a first end of the diode DZ1 is electrically connected to the second end of the inductor L1, and a second end of the diode DZ1 is electrically connected to the resistor R2.

[0053] It should be noted that the 19th pin of chip UP1 outputs the VGH electrical signal, while the 20th pin of chip UP1 is connected to resistor R1 for current limiting. After passing through capacitors C9 and C10 to ground, high-frequency interference noise in the signal is filtered out. Inductor L1 isolates the high-frequency signal and passes through the low-frequency effective electrical signal. A low-frequency oscillation compensation circuit consisting of resistor R5 and capacitor C13 is superimposed. Limiting diode DZ1 is then connected to limit the voltage amplitude to a safe range, protecting the TCON logic board from high voltage damage. The complete VGH_OUT electrical signal is then output through current-limiting resistor R2.

[0054] The scheme of the present application has been described in detail above with reference to the accompanying drawings. In the above embodiments, the descriptions of each embodiment have their own emphasis. For parts that are not described in detail in a certain embodiment, please refer to the relevant descriptions of other embodiments. Those skilled in the art should also be aware that the actions and modules involved in the description are not necessarily required for this application. In addition, it is understood that the steps in the method of the embodiment of the present application can be adjusted in sequence, merged and deleted according to actual needs, and the modules in the device of the embodiment of the present application can be merged, divided and deleted according to actual needs.

[0055] The embodiments of the present application have been described above. The above description is exemplary, not exhaustive, and is not limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is selected to best explain the principles of the embodiments, their practical applications, or improvements to the technology in the market, or to enable other persons skilled in the art to understand the embodiments disclosed herein.

Claims

1. A driving circuit for solving the problem of color gradation discontinuity in a picture, characterized in that: include: Input module; The main control module includes a chip UP1 and an anti-interference unit, which includes a resistor R15, a capacitor C23 and an inductor L2. The input module is electrically connected to the chip UP1, the first end of the resistor R15 is electrically connected to the chip UP1, the second end of the resistor R15 is electrically connected to the first end of the capacitor C23, the second end of the capacitor C23 is grounded, the first end of the inductor L2 is electrically connected to the first end of the resistor R15, and the second end of the inductor L2 is electrically connected to the second end of the capacitor C23.

2. The driving circuit for solving the problem of image gradation discontinuity according to claim 1, characterized in that: The input module includes a fuse F1, a voltage regulator diode DZ2, a capacitor C1, a capacitor C2 and a capacitor C3. The first end of the voltage regulator diode DZ2 is electrically connected to the fuse F1 and the first end of the capacitor C1 respectively, the second end of the voltage regulator diode DZ2 is electrically connected to the second end of the capacitor C1, the first end of the capacitor C2 is electrically connected to the first end of the capacitor C1, the second end of the capacitor C2 is electrically connected to the second end of the capacitor C1, the first end of the capacitor C3 is electrically connected to the first end of the capacitor C2, and the second end of the capacitor C3 is grounded.

3. The driving circuit for solving the problem of color gradation discontinuity of a picture according to claim 2, characterized in that: The main control module also includes a capacitor C26 and a capacitor C27. The first end of the capacitor C26 is electrically connected to the chip UP1, the second end of the capacitor C26 is grounded, and the first end of the capacitor C27 is electrically connected to the first end of the capacitor C26 and the first end of the capacitor C3 respectively.

4. The driving circuit for solving the problem of image gradation discontinuity according to claim 2, wherein: The main control module also includes a voltage processing unit, which includes an inductor L3, a voltage regulator DZ4, a capacitor C21, a capacitor C22 and a resistor R18. The first end of the inductor L3 is electrically connected to the first end of the capacitor C3, the second end of the inductor L3 is electrically connected to the first end of the voltage regulator DZ4, the second end of the voltage regulator DZ4 is electrically connected to the first end of the capacitor C21, the second end of the capacitor C21 is grounded, the first end of the capacitor C22 is electrically connected to the first end of the capacitor C21 and the chip UP1 respectively, the second end of the capacitor C22 is grounded, the first end of the resistor R18 is electrically connected to the second end of the inductor L3, and the second end of the resistor R18 is electrically connected to the chip UP1.

5. The driving circuit for solving the problem of image gradation discontinuity according to claim 1, wherein: The main control module also includes a purification unit, which includes a capacitor C17, a resistor RJ1, a capacitor C41, a capacitor C42, a capacitor C43, a capacitor C44, an inductor L4 and a voltage regulator tube DZ5. The first end of the capacitor C17 is electrically connected to the chip UP1, and the second end of the capacitor C17 is grounded. The first end of the resistor RJ1 is electrically connected to the first end of the capacitor C17, the second end of the resistor RJ1 is electrically connected to the first end of the capacitor R41, and the second end of the capacitor C41 is grounded. 2 is electrically connected to the first end of the capacitor C41, the second end of the capacitor C42 is grounded, the first end of the capacitor C43 is electrically connected to the first end of the capacitor C42, the second end of the capacitor C43 is grounded, the first end of the capacitor C44 is electrically connected to the first end of the capacitor C43, the second end of the capacitor C44 is grounded, the first end of the inductor L4 is electrically connected to the first end of the capacitor C44, the second end of the inductor L4 is electrically connected to the voltage regulator tube DZ5, and the second end of the voltage regulator tube DZ5 is grounded.

6. The driving circuit for solving the problem of image gradation discontinuity according to claim 5, characterized in that: The main control module further includes a resistor R13 and a capacitor C16. A first end of the resistor R13 is electrically connected to the chip UP1. A second end of the resistor R13 is electrically connected to a first end of the capacitor C16. A second end of the capacitor C16 is grounded.

7. The driving circuit for solving the problem of image gradation discontinuity according to claim 1, wherein: The main control module also includes a MOS transistor Q1, a resistor R6, and a resistor R3. The gate of the MOS transistor Q1 is electrically connected to the chip UP1 and the first end of the resistor R6, respectively. The drain of the MOS transistor Q1 is electrically connected to the chip UP1 and the first end of the resistor R3, respectively. The second end of the resistor R3 is electrically connected to the second end of the resistor R6.

8. The driving circuit for solving the problem of image gradation discontinuity according to claim 1, wherein: The main control module also includes a MOS transistor Q2, a capacitor C8, a capacitor C4, a capacitor C5, a capacitor C6, and a capacitor C7. The gate of the MOS transistor Q2, the first end of the capacitor C7, and the first end of the capacitor C8 are respectively electrically connected to the chip UP1. The first end of the capacitor C7 is also electrically connected to the drain of the MOS transistor Q2. The first end of the capacitor C8 is also electrically connected to the source of the MOS transistor Q2. The second end of the capacitor C7 and the second end of the capacitor C8 are respectively electrically connected to the gate of the MOS transistor Q2. The first end of the capacitor C4 is electrically connected to the first end of the capacitor C5. The second end of the capacitor C4 is grounded. The second end of the capacitor C5 is grounded. The first end of the capacitor C6 is respectively electrically connected to the first end of the capacitor C5 and the first end of the capacitor C7. The second end of the capacitor C6 is grounded.

9. The driving circuit for solving the problem of image gradation discontinuity according to claim 1, wherein: The main control module also includes a resistor R7, a resistor R8, a resistor R9, a transistor Q3 and a transistor Q4. The resistor R7 is electrically connected to the collector of the transistor Q3, the first end of the resistor R8 is electrically connected to the chip UP1, and the second end of the resistor R8 is electrically connected to the base of the transistor Q3 and the base of the transistor Q4 respectively. The first end of the resistor R9 is electrically connected to the chip UP1, and the second end of the resistor R9 is electrically connected to the emitter of the transistor Q3 and the emitter of the transistor Q4 respectively.

10. The driving circuit for solving the problem of image gradation discontinuity according to claim 9, wherein: The main control module further includes a resistor R12 , a first end of the resistor R12 is electrically connected to the collector of the transistor Q4 , and a second end of the resistor R12 is grounded.

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