Capacitive coupling voltage type sense amplifier, memory and sense method

Abstract

The invention provides a capacitive coupling voltage type sense amplifier, a memory and a reading method, the capacitive coupling voltage type sense amplifier comprises a first step-down branch, a coupling capacitor and a first drainage branch; the coupling capacitor comprises a test capacitor; the first voltage reduction branch is connected with one end of the test capacitor and is used for reducing the voltage of one end of the test capacitor to a preset value in a margin development stage; the other end of the test capacitor is respectively connected with the first drainage branch and the magnetic tunnel junction; and the first drainage branch is used for sharing the current on the magnetic tunnel junction in a detection stage. According to the technical scheme provided by the invention, the problems that the critical write-in current cannot be reduced and the read-out reliability cannot be improved at the same time in the prior art and other problems caused by the problems are solved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductors, and more particularly to a capacitively coupled voltage-type sense amplifier and a sense method. Background Art

[0002] Spin-transfer torque magnetic random access memory (STT-MRAM) is a promising candidate for next-generation memory technology, known for its compact bit cell area. Furthermore, optimizing the magnetic tunnel junction (MTJ) stack for lower write currents by relaxing retention requirements can make it suitable for high-density working memory, with memory capacities up to tens of Mb already demonstrated. However, STT-MRAM faces the challenge of a small read window due to its low tunnel magnetoresistance (TMR) and parallel state resistance (RP).

[0003] Currently, mainstream sense amplifiers (SAs) are primarily categorized into two types: current-source sense amplifiers (CSAs) and voltage-source sense amplifiers (VSAs). CSAs typically have a shorter sensing margin development time than VSAs. The margin of a CSA is monotonically increasing, while that of a VSA is not. This is because the cell current and reference current reach steady state in a CSA, while the margin of a VSA depends on the difference between the two discharge BL voltages, which begins to decrease after reaching a peak. The monotonically increasing margin of a CSA comes at the expense of maintaining DC current during read operations, resulting in higher power consumption.

[0004] A new type of capacitive-coupled voltage-amplified sense amplifier (CVSA) uses the coupling effect of capacitors to increase the sensing margin of the VSA. Instead of reaching a peak value and then decreasing over time, the sensing margin continues to increase.

[0005] However, in the final voltage difference amplification stage, since the potential of the upper part of the capacitor will be directly connected to the ground, that is, the voltage will suddenly change from close to VDD-Vth to 0, due to the coupling effect of the capacitor, the voltage at the lower end, that is, the voltage at the upper end of the MTJ, will also decrease by VDD-Vth. The previous terminal voltage VREAD is much smaller than VDD-Vth. After the voltage of VDD-Vth decreases, the voltage at the upper end of the MTJ will generate a large reverse voltage, further forming a large reverse current, increasing the possibility of erroneous writing. Summary of the Invention

[0006] In view of the above analysis, the present application aims to propose a capacitively coupled voltage-type sense amplifier and a readout method to reduce the probability of erroneous writing.

[0007] In a first aspect, one or more embodiments of this specification provide a spin-transfer torque amplifier, comprising: a first step-down branch, a coupling capacitor, and a first current-draining branch;

[0008] The coupling capacitor includes a test capacitor;

[0009] The first voltage reduction branch is connected to one end of the test capacitor and is used to reduce the voltage of the one end of the test capacitor to a preset value in the margin development stage;

[0010] The other end of the test capacitor is connected to the first drain branch and the magnetic tunnel junction respectively;

[0011] The first diversion branch is used to share the current on the magnetic tunnel junction during the detection phase.

[0012] Furthermore, the amplifier further comprises a second voltage-reducing branch and a second current-draining branch; the coupling capacitor comprises a reference capacitor;

[0013] The second voltage-reducing branch is connected to one end of the reference capacitor and is used to reduce the voltage of the one end of the reference capacitor to a preset value during the margin development stage;

[0014] The other end of the reference capacitor is connected to the second drainage branch and the load respectively;

[0015] The second current diversion branch is used to share the current on the load during the detection phase.

[0016] Furthermore, the second step-down branch is a first MOS transistor, a first electrode of the first MOS transistor is connected to one electrode plate of the reference capacitor, and a second electrode of the first MOS transistor is grounded.

[0017] Furthermore, the second drain branch is a second MOS transistor, a first electrode of the second MOS transistor is connected to the other electrode plate of the reference capacitor, and a second electrode of the second MOS transistor is grounded.

[0018] Furthermore, the first step-down branch is a third MOS transistor, a first electrode of the third MOS transistor is connected to one electrode plate of the test capacitor, and a second electrode of the third MOS transistor is grounded.

[0019] Furthermore, the first drain branch is a fourth MOS transistor, a first electrode of the fourth MOS transistor is connected to the other electrode plate of the test capacitor, and a second electrode of the fourth MOS transistor is grounded.

[0020] In a second aspect, one or more embodiments of this specification provide a spin-transfer torque magnetic random access memory, comprising at least: a capacitively coupled voltage-type sense amplifier as described in any one of the first aspects.

[0021] In a third aspect, one or more embodiments of this specification provide an electronic device comprising at least: the memory described in the second aspect.

[0022] In a fourth aspect, one or more embodiments of this specification provide a readout method based on the capacitively coupled voltage-type sense amplifier according to any one of the first aspects, including:

[0023] In the margin development stage, for the circuit where the test capacitor in the coupling capacitor is located, the first voltage reduction branch and the first current drain branch are closed simultaneously.

[0024] Further, the coupling capacitor includes a reference capacitor;

[0025] The method further comprises:

[0026] In the margin development stage, for the circuit where the reference capacitor is located, the first voltage-reducing branch and the first current-draining branch are simultaneously connected.

[0027] Compared with the existing technology, this application can at least achieve the following technical effects:

[0028] The addition of a drainage branch allows the current generated by the reverse voltage to mainly pass through the drainage branch rather than the magnetic tunnel junction, thereby greatly reducing the current flowing through the magnetic tunnel junction and further reducing the risk of miswriting. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] In order to more clearly illustrate one or more embodiments of this specification or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments recorded in this specification. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0030] Figure 1 A schematic diagram of the structure of a capacitively coupled voltage-type sense amplifier provided in one or more embodiments of this specification;

[0031] Figure 2 A schematic structural diagram of another capacitively coupled voltage-type sense amplifier provided in one or more embodiments of this specification;

[0032] Figure 3 Simulation results of an amplifier without a drain circuit provided in one or more embodiments of this specification;

[0033] Figure 4 The present invention provides simulation results of an amplifier with a current drain circuit according to one or more embodiments of the present invention. DETAILED DESCRIPTION

[0034] In order to enable those skilled in the art to better understand the technical solutions in one or more embodiments of this specification, the technical solutions in one or more embodiments of this specification will be clearly and completely described below in conjunction with the drawings in one or more embodiments of this specification. Obviously, the described embodiments are only part of the embodiments of this specification, not all of the embodiments. Based on one or more embodiments of this specification, all other embodiments obtained by ordinary technicians in this field without making creative efforts should fall within the scope of protection of this document.

[0035] The present invention provides a capacitively coupled voltage sense amplifier (CVSA), such as Figure 1 As shown, it includes an amplifier (not shown), a first step-down branch, a first current-drawing branch, a second step-down branch, a second current-drawing branch, a pair of coupling capacitors (test capacitor CL, reference capacitor CR), a bit line clamp component (inverter INV, N-type MOS transistor N1, N-type MOS transistor N2), a bit line selector (BLMUX) and an equalizer (N5). cell Represents the bit line unit in the memory, BL REP Indicates the bit line reference circuit. BL cell The corresponding circuit is the circuit where the magnetic tunnel junction is located, BL REP The corresponding circuit is used to provide a reference voltage.

[0036] Specifically, the first step-down branch is connected to one end of the CL, and is used to reduce the voltage at one end of the CL to a preset value during the margin development phase. The other end of the CL is respectively connected to the first drain branch and the magnetic tunnel junction MTJ. The first drain branch is used to share the current on the magnetic tunnel junction during the detection phase. The second step-down branch is connected to one end of the CR pair, and is used to reduce the voltage at one end of the CR to a preset value during the margin development phase. The other end of the CR is respectively connected to the second drain branch and the load. The second drain branch is used to share the current on the load during the detection phase.

[0037] By setting the first current-guiding branch in parallel with the magnetic tunnel junction, the first current-guiding branch bears most of the current generated by the reverse voltage, thereby reducing the probability of miswriting. The second current-guiding branch is used to eliminate the differences caused by cross-coupling to improve reading accuracy.

[0038] The working process of the above circuit is as follows: in the precharge stage (PRE), based on PREB, the voltage of nodes CPL and CPR is increased to VDD-VTH to eliminate the cross-coupled NMOS VTH difference. At the same time, the W side and WB side are precharged to VREAD. In the margin development stage, WL (magnetic tunnel junction switch) is activated, and the BL voltage is discharged through MTJ (magnetic tunnel junction). The first step-down branch is connected, and the first drainage branch is connected, so that the voltage at CPL decreases proportionally with the BL voltage discharge. At the same time, the second step-down branch is connected, and the second drainage branch is connected, so that the voltage at CPR decreases proportionally with the BL voltage discharge. Afterwards, the voltage difference between CPL and CPR is amplified at INL / INR. Finally, an amplifier is connected at INL / INR to further amplify the voltage difference between CPL and CPR.

[0039] It should be noted that those skilled in the art can select a corresponding amplifier according to actual scenarios, for example, a latch-type sense amplifier.

[0040] Preferably, in order to facilitate on-chip integration and simultaneous start-up, the first voltage-reducing branch, the first current-draining branch, the second voltage-reducing branch, and the second current-draining branch can all be designed as the same MOS transistor (SAEN).

[0041] Specifically, Figure 2 As shown,

[0042] The second step-down branch is a first MOS transistor, a first electrode of the first MOS transistor is connected to one electrode plate of the reference capacitor, and a second electrode of the first MOS transistor is grounded.

[0043] The second drain branch is a second MOS transistor, a first electrode of the second MOS transistor is connected to the other electrode plate of the reference capacitor, and a second electrode of the second MOS transistor is grounded.

[0044] The first step-down branch is a third MOS transistor, a first electrode of the third MOS transistor is connected to one electrode plate of the test capacitor, and a second electrode of the third MOS transistor is grounded.

[0045] The first drain branch is a fourth MOS transistor, a first electrode of the fourth MOS transistor is connected to the other electrode plate of the test capacitor, and a second electrode of the fourth MOS transistor is grounded.

[0046] To illustrate the feasibility of the above solution, the following example is given:

[0047] like Figure 3Figure 1 shows the simulation results before the improvement, where I3 / p and I2 / p are the currents in the MTJ and reference circuits. It can be seen that after SAEN is turned on, the CPL / CPR voltage rapidly decreases to near zero through the ground branch, and the voltage drop is also coupled to the W / WB through capacitive coupling, causing the voltage at the W / WB to become a large negative value. The current reaches -25uA when discharging through the MTJ, while the write current is around 100uA, indicating a high probability of erroneous writes.

[0048] like Figure 4 The figure below shows the improved results, where I3 / p and I2 / p represent the currents in the MTJ and reference circuits. It can be seen that due to the addition of a ground branch at the W / WB, even if capacitive coupling still exists, the voltage drop across the W / WB can be quickly dissipated through the ground branch. This significantly reduces the current flowing through the MTJ, with the maximum current on the MTJ being -5uA, much lower than before the improvement. Compared to the 100uA write current, the probability of erroneous writes is significantly reduced.

[0049] An embodiment of the present application provides a memory comprising the capacitively coupled voltage-type sense amplifier and the magnetic tunnel junction as described in any one of the above embodiments.

[0050] An embodiment of the present application provides an electronic device, including: the memory described in the above embodiment.

[0051] An embodiment of the present application provides a readout method based on the capacitively coupled voltage-type sense amplifier described in any one of the above embodiments, comprising the following steps:

[0052] In the margin development stage, for the circuit where the test capacitor in the coupling capacitor is located, the first voltage reduction branch and the first current drain branch are closed simultaneously.

[0053] In an embodiment of the present application, the coupling capacitor includes a reference capacitor; and the method further includes:

[0054] In the margin development stage, for the circuit where the reference capacitor is located, the first voltage-reducing branch and the first current-draining branch are simultaneously connected.

[0055] It should also be noted that the terms "comprises," "includes," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, commodity, or apparatus that includes a series of elements includes not only those elements but also other elements not explicitly listed, or includes elements inherent to such process, method, commodity, or apparatus. In the absence of further limitations, an element defined by the phrase "comprises a ..." does not exclude the presence of other identical elements in the process, method, commodity, or apparatus that includes the element.

[0056] The various embodiments in this specification are described in a progressive manner. Similar parts between the various embodiments can be referred to in conjunction with each other. Each embodiment focuses on the differences between the other embodiments. In particular, the system embodiments are generally similar to the method embodiments, so the description is relatively simple. For relevant parts, refer to the description of the method embodiments.

[0057] The foregoing description is merely an example of the present invention and is not intended to limit the present invention. Persons skilled in the art will readily appreciate that various modifications and variations of the present invention are possible. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of the present invention are intended to be included within the scope of the claims herein.

Claims

1. A capacitively coupled voltage-type sense amplifier, characterized in that: include: a first step-down branch, a coupling capacitor, and a first current drain branch; The coupling capacitor includes a test capacitor; The first voltage reduction branch is connected to one end of the test capacitor and is used to reduce the voltage of the one end of the test capacitor to a preset value in the margin development stage; The other end of the test capacitor is connected to the first drain branch and the magnetic tunnel junction respectively; The first diversion branch is used to share the current on the magnetic tunnel junction during the detection phase.

2. The amplifier according to claim 1, wherein The amplifier further comprises a second voltage-reducing branch and a second current-draining branch; the coupling capacitor comprises a reference capacitor; The second voltage-reducing branch is connected to one end of the reference capacitor and is used to reduce the voltage of the one end of the reference capacitor to a preset value during the margin development stage; The other end of the reference capacitor is connected to the second drainage branch and the load respectively; The second current diversion branch is used to share the current on the load during the detection phase.

3. The amplifier according to claim 2, characterized in that The second step-down branch is a first MOS transistor, a first electrode of the first MOS transistor is connected to one electrode plate of the reference capacitor, and a second electrode of the first MOS transistor is grounded.

4. The amplifier according to claim 3, characterized in that The second drain branch is a second MOS transistor, a first electrode of the second MOS transistor is connected to the other electrode plate of the reference capacitor, and a second electrode of the second MOS transistor is grounded.

5. The amplifier according to claim 1, wherein The first step-down branch is a third MOS transistor, a first electrode of the third MOS transistor is connected to one electrode plate of the test capacitor, and a second electrode of the third MOS transistor is grounded.

6. The amplifier according to claim 5, characterized in that The first drain branch is a fourth MOS transistor, a first electrode of the fourth MOS transistor is connected to the other electrode plate of the test capacitor, and a second electrode of the fourth MOS transistor is grounded.

7. A spin-transfer torque magnetic random access memory, characterized in that: At least: A capacitively coupled voltage-type sense amplifier according to any one of claims 1 to 6.

8. An electronic device, characterized in that: At least: The memory according to claim 7.

9. A readout method based on the capacitively coupled voltage-type sense amplifier according to any one of claims 1 to 6, characterized in that: include: In the margin development stage, for the circuit where the test capacitor in the coupling capacitor is located, the first voltage reduction branch and the first current drain branch are closed simultaneously.

10. The method according to claim 9, characterized in that The coupling capacitor includes a reference capacitor; The method further comprises: In the margin development stage, for the circuit where the reference capacitor is located, the first voltage-reducing branch and the first current-draining branch are simultaneously connected.

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