Flash memory data decoding method, device, electronic device and readable storage medium

Abstract

The present application discloses a flash memory data decoding method, device, electronic device and readable storage medium, relating to the field of data decoding technology. The method includes obtaining the current data reading result of a storage unit through the current left-offset reference voltage, the no-offset reference voltage and the right-offset reference voltage in the current read voltage. If the decoding of the current data reading result fails, the current left-offset reference voltage is immediately and dynamically adjusted based on a preset offset, so that the adjusted first left-offset reference voltage is less than the current right-offset reference voltage to generate a first reading voltage. Furthermore, when the flash memory storage unit experiences characteristic changes such as threshold voltage drift during long-term use, the fixed reference voltage is no longer used. Instead, the reading voltage is flexibly adjusted to avoid decoding failures caused by insufficient voltage adaptation and improve the probability of successful decoding.

Description

Technical Field

[0001] The present application relates to the field of data decoding technology, and in particular to a flash memory data decoding method, device, electronic device and readable storage medium. Background Art

[0002] Currently, when reading data from NAND flash memory using the soft decoding method, three consecutive read operations are performed using a left-offset reference voltage, a no-offset reference voltage, and a right-offset reference voltage to obtain the read original data and the corresponding log-likelihood ratio (LLR) table. Then, during the decoding process, the information in the LLR table, combined with the three read original data, can help the ECC decoding module perform error correction more accurately, thereby improving the accuracy and success rate of data reading. This is especially effective when dealing with read errors caused by factors such as wear and tear and voltage drift in NAND flash memory.

[0003] However, in traditional methods, the left and right offset reference voltages are often preset to fixed values ​​during reading. However, these fixed offset reference voltages are difficult to adapt to the characteristics of memory cells with varying degrees of aging, which can lead to a decrease in read data accuracy. For example, the threshold voltage of a severely aged memory cell may drift significantly. If the initial fixed offset reference voltage is still used for reading, the raw data read three times will not accurately reflect the actual state of the memory cell, resulting in data decoding failure. Summary of the Invention

[0004] The present application provides a flash memory data decoding method, device, electronic device and readable storage medium to at least solve the problem of high data decoding failure rate in the related art.

[0005] The present application provides a flash memory data decoding method, comprising:

[0006] Based on the current read data voltage, the memory cell on the target word line in the flash memory is read to obtain the current data read result; the current read data voltage includes the current left offset reference voltage, the no offset reference voltage and the current right offset reference voltage;

[0007] In the case where the decoding of the current data read result fails, adjusting the current left offset reference voltage according to a first preset offset to obtain a first left offset reference voltage to generate a first read voltage; the first read voltage includes the first left offset reference voltage, the no-offset reference voltage, and the current right offset reference voltage; the first left offset reference voltage is less than the current left offset reference voltage;

[0008] Based on the first read voltage, the memory cells on the target word line are re-read to obtain a first data read result.

[0009] The present application also provides a flash memory data decoding device, comprising:

[0010] A data reading unit, configured to read a storage cell on a target word line in the flash memory based on a current read data voltage to obtain a current data read result; the current read data voltage includes a current left offset reference voltage, a no-offset reference voltage, and a current right offset reference voltage;

[0011] an adjustment unit, configured to, when decoding of the current data read result fails, adjust the current left offset reference voltage according to a first preset offset to obtain a first left offset reference voltage to generate a first read voltage; the first read voltage includes the first left offset reference voltage, the no-offset reference voltage, and the current right offset reference voltage; the first left offset reference voltage is less than the current left offset reference voltage;

[0012] The data reading unit is further configured to re-read the storage unit on the target word line based on the first reading voltage to obtain a first data reading result.

[0013] The present application also provides an electronic device, comprising: a memory for storing a computer program; and a processor for implementing the steps of any one of the above-mentioned flash memory data decoding methods when executing the computer program.

[0014] The present application also provides a computer-readable storage medium, in which a computer program is stored. When the computer program is executed by a processor, the steps of any of the above-mentioned flash memory data decoding methods are implemented.

[0015] The present application also provides a computer program product, including a computer program, which implements the steps of any of the above-mentioned flash memory data decoding methods when executed by a processor.

[0016] When the present application obtains the current data reading result of the storage cell through the current left-offset reference voltage, the no-offset reference voltage and the right-offset reference voltage in the current read voltage, if the decoding of the current data reading result fails, the current left-offset reference voltage is immediately and dynamically adjusted based on the preset offset, so that the adjusted first left-offset reference voltage is less than the current right-offset reference voltage to generate the first reading voltage. Then, when characteristic changes such as threshold voltage drift occur in the long-term use of the flash memory storage cell, the fixed reference voltage is no longer used, but the reading voltage is flexibly adjusted to avoid decoding failure caused by insufficient voltage adaptation and increase the probability of successful decoding. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and, together with the description, serve to explain the principles of the present disclosure.

[0018] In order to more clearly illustrate the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0019] Figure 1 This is a flow chart of a flash memory data decoding method provided in an embodiment of the present application;

[0020] Figure 2 A schematic diagram of a read voltage adjustment process of a flash memory data decoding method provided in an embodiment of the present application;

[0021] Figure 3 A second flow chart of a flash memory data decoding method provided in an embodiment of the present application;

[0022] Figure 4 The third flowchart of a flash memory data decoding method provided in an embodiment of the present application;

[0023] Figure 5 A schematic structural diagram of a flash memory data decoding device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0024] The following will be combined with the accompanying drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0025] It should be noted that, in the description of this application, the terms "comprises," "includes," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. The terms "first," "second," etc., in this application are used to distinguish similar objects, and are not used to describe a particular order or sequence.

[0026] In order to enable those skilled in the art to better understand the present application, the present application is further described in detail below with reference to the accompanying drawings and specific implementation methods.

[0027] It should be noted that the embodiments of the present application are mainly directed to using a soft decoding method to read data from storage cells corresponding to the same word line in a solid-state drive.

[0028] NAND flash memory cells are composed of floating-gate transistors, whose threshold voltage (the minimum voltage required to turn on the transistor) is changed by injecting or removing electrons from the floating gate. When writing data, the controller programs the memory cell based on the binary data to be stored (0 or 1). For example, injecting electrons into the floating gate increases the threshold voltage (corresponding to state 1), while removing electrons lowers the threshold voltage (corresponding to state 0).

[0029] During the read phase, the reference voltage serves as a benchmark for determining the threshold voltage state. When the applied reference voltage is higher than the threshold voltage of the memory cell, the transistor turns on, and the output signal is determined to be 0. When the reference voltage is lower than the threshold voltage, the transistor turns off, and the output signal is determined to be 1.

[0030] An embodiment of the present application provides a flash memory data decoding method, and the method is described in detail in conjunction with an execution flow of the flash memory data decoding method.

[0031] Reference Figure 1 FIG. 1 is a flow chart of a flash memory data decoding method, which includes the following steps S11-S13:

[0032] S11 . Based on the current read data voltage, read the memory cell on the target word line in the flash memory to obtain the current data read result.

[0033] The current read data voltage includes a current left-shift reference voltage, a no-shift reference voltage, and a current right-shift reference voltage.

[0034] Specifically, soft decoding uses different voltages to perform multiple reads on all memory cells corresponding to the same word line. In the embodiment of the present application, the current read data voltage can be understood as the initial read data voltage used for the initial read of all memory cells corresponding to the same word line. The current read data voltage includes three sets of reference voltages: the current left-offset reference voltage (lower than the no-offset reference voltage), the no-offset reference voltage (base voltage), and the current right-offset reference voltage (higher than the no-offset reference voltage). These three sets of voltages form the basic detection interval for the threshold voltage of the memory cell, where the no-offset reference voltage corresponds to the threshold voltage demarcation point of the memory cell under ideal conditions, and the left and right offset reference voltages are used to capture slight threshold voltage fluctuations. For example, if the no-offset reference voltage is 0V and the current left-offset reference voltage is -8V, then the initial right-offset reference voltage is 8V.

[0035] Then, by applying the three sets of voltages to the target word line, the response states of all memory cells on the target word line are sequentially read (outputting 0 when on and 1 when off). The three responses of each memory cell are combined into a first data read result (e.g., 0-1-1, 1-0-0, etc.). The consistency of these three read results serves as an important basis for determining the reliability of the memory cell data: If the three read results are the same (e.g., all 0 or all 1), it indicates that the threshold voltage of the memory cell is far away from the critical region of different states, the data is less affected by interference, the read result is highly reliable, and the corresponding LLR value is large in absolute value. If the three read results are different (e.g., 0-1-0, 1-0-1, etc.), it indicates that the threshold voltage corresponding to the data bit may fall into the overlapping region of different states and is significantly affected by factors such as voltage drift and noise. Further error correction is required, providing a reference for subsequent data decoding using error correction decoding (e.g., LDPC decoding).

[0036] It should be noted that the current read data voltage may be an initial read data voltage, or may be a read data voltage obtained by adjusting the initial read data voltage.

[0037] S12 . When the decoding of the current data reading result fails, adjust the current left-offset reference voltage according to the first preset offset to obtain a first left-offset reference voltage to generate a first read voltage.

[0038] The first read voltage includes a first left-offset reference voltage, a no-offset reference voltage, and a current right-offset reference voltage; and the first left-offset reference voltage is smaller than the current left-offset reference voltage.

[0039] If decoding of the current data read result fails, it indicates that the actual threshold voltage distribution of the memory cell has deviated from the coverage range of the current read voltage. This may be due to the gate capacitance effect caused by aging of the memory cell, which leads to a significant threshold voltage drift. Specifically, this is manifested as a right-shifted reference voltage, causing some memory cells that should be turned on to remain off at the initial left-shifted reference voltage, resulting in read errors. This in turn leads to insufficient accuracy of the log-likelihood ratio (LLR) value generated based on the initial data, and a low subsequent decoding success rate.

[0040] Then, it is necessary to immediately adjust the current left-offset reference voltage to generate a first left-offset reference voltage to obtain the first read voltage. Specifically, the first preset offset is a negative value, and then the first preset offset is added to the current left-offset reference voltage. This value can be pre-set based on the flash memory characteristics and actual application scenarios. For example, if the current left-offset reference voltage is -8V and the first preset offset is -2V, then the target left-offset reference voltage is -10V, so that the first left-offset reference voltage is less than the current left-offset reference voltage. For another example, if the current left-offset reference voltage is 8V and the first preset offset is -2V, then the target left-offset reference voltage is 6V, so that the first left-offset reference voltage is less than the current left-offset reference voltage.

[0041] For example, refer to Figure 2 As shown in (a), if the current read voltage is: -8V, 0V, +8V, the first preset offset is set to -2V. At this time, after the adjustment of S12 above, the first read voltage is obtained: -10V, 0V, +8V; Figure 2 As shown in (b) in .

[0042] This embodiment of the present application takes into account the characteristic of the reference voltage being right-shifted due to the gate capacitance effect. When the memory cell threshold voltage exceeds the coverage range of the initial left-shifted reference voltage due to right-shifting, the left-shifted reference voltage is adjusted to expand the coverage range of the left-shifted threshold voltage distribution, so that the adjusted first read voltage can better match the actual state of the threshold voltage after right-shifting. This adjustment can effectively capture the "critical region" data characteristics caused by right-shifting, laying the foundation for subsequent re-reading to obtain more accurate original data, thereby improving the success rate of secondary decoding.

[0043] S13 . Re-read the memory cells on the target word line based on the first read voltage to obtain a first data read result.

[0044] Based on the adjustment in step S13, the possible characteristic changes of the storage cell, such as the rightward deviation of the threshold voltage, are optimized, thereby correcting the deviation caused by insufficient voltage adaptation during reading in step S11, and then re-obtaining the first data reading result based on the first read voltage.

[0045] When the present application obtains the current data reading result of the storage cell through the current left-offset reference voltage, the no-offset reference voltage and the right-offset reference voltage in the current read voltage, if the decoding of the current data reading result fails, the current left-offset reference voltage is immediately and dynamically adjusted based on the preset offset, so that the adjusted first left-offset reference voltage is less than the current right-offset reference voltage to generate the first reading voltage. Then, when characteristic changes such as threshold voltage drift occur in the long-term use of the flash memory storage cell, the fixed reference voltage is no longer used, but the reading voltage is flexibly adjusted to avoid decoding failure caused by insufficient voltage adaptation and increase the probability of successful decoding.

[0046] As an extension and refinement of the above embodiment, refer to Figure 3 As shown, the embodiment of the present application also provides another flash memory data decoding method, which specifically includes the following steps S31 to S33:

[0047] S31 . Decode the first data reading result.

[0048] After obtaining the first data reading result, it is necessary to extract the first log-likelihood ratio value reflecting the data reliability from the result and combine it with the first data reading result to provide the ECC decoding module with richer decision-making basis, thereby increasing the probability of successful decoding.

[0049] Furthermore, the ECC decoding module decodes data based on both the first data read result (hard information) and the first log-likelihood ratio (soft information). Hard information provides a preliminary judgment of the data, while soft information indicates the reliability of that judgment. For example, the decoder assigns a higher confidence weight to bits with larger LLR absolute values. For bits with smaller LLR absolute values ​​(in the overlapping threshold voltage region), the decoder applies more refined error correction based on the correlation of adjacent data.

[0050] S32: If the first data reading result is decoded successfully, obtain and output first decoded data corresponding to the first data reading result.

[0051] Before performing the decoding operation, a first log-likelihood ratio value corresponding to the first data read result must be obtained. When the decoding operation based on the first data read result and the first log-likelihood ratio value passes the ECC decoding module, it indicates that the current reference voltage scheme (the first read voltage) has effectively covered the threshold voltage distribution of the memory cell, and the decoding process has successfully recovered the original data. The decoded data (i.e., the first decoded data) is directly obtained and output, terminating the subsequent voltage adjustment process.

[0052] Specifically, the decoding operation process of the first data reading result data includes the following steps 1 and 2:

[0053] Step 1: Obtain a first log-likelihood ratio value according to a first data reading result.

[0054] After obtaining the first data read result, the first data read result includes three read response combinations, such as 0 / 1 / 1, 1 / 0 / 0, and so on, for each memory cell on the target word line at the first data read voltage (target left offset, no offset, and current right offset reference voltage). These combinations correspond to specific threshold voltage distribution patterns, and the LLR values ​​corresponding to each pattern are stored in a first log-likelihood ratio mapping table (pre-generated based on sample data of the first read voltage). Therefore, based on the voltage distribution combination in the first data read result, the first log-likelihood ratio value can be directly retrieved from the mapping table. This value quantifies the probability that the data of each memory cell is 1 or 0 (positive values ​​indicate a higher probability of 1, negative values ​​indicate a higher probability of 0, and larger absolute values ​​indicate higher reliability).

[0055] Furthermore, the refinement step of obtaining the first log-likelihood ratio value according to the first data reading result includes the following steps 11 and 12:

[0056] Step 11: Perform statistical analysis on the first data reading result to obtain a first voltage distribution combination corresponding to the memory cell.

[0057] The first data read results (i.e., the three responses of each memory cell at the first read voltage) are grouped and organized by word line. For each memory cell, its responses (0 or 1) at the first left-offset, no-offset, and current right-offset reference voltages are combined into a unique three-bit binary code, forming a first voltage distribution combination (e.g., 0-1-1). This combination directly reflects the positional relationship of the memory cell threshold voltage relative to the three sets of reference voltages.

[0058] By analyzing the voltage distribution combinations of a large number of memory cells, the threshold voltage distribution characteristics of the entire word line can be inferred, providing a basis for the accurate acquisition of subsequent LLR values.

[0059] Step 12: Based on the first voltage distribution combination, obtain a corresponding first log-likelihood ratio value.

[0060] Specifically, in a pre-generated first log-likelihood ratio mapping table, each possible voltage distribution combination is mapped to a corresponding LLR value. By comparing the first voltage distribution combination of the current storage cell with the entries in the mapping table, the corresponding LLR value is quickly extracted. The LLR value represents the logarithmic probability ratio of the data in that storage cell to be 1, directly quantifying data reliability and providing soft information support for subsequent ECC decoding.

[0061] Step 121 : Obtain a first log-likelihood ratio mapping table corresponding to a first data read voltage.

[0062] The first log-likelihood ratio mapping table includes log-likelihood ratios corresponding to a plurality of voltage distribution combinations under the first read voltage.

[0063] The first voltage distribution combination (eg, 0-1-1) of each memory cell is generated based on its three read responses at the first read voltage, and the combination uniquely identifies the positional relationship of the memory cell threshold voltage relative to the three sets of reference voltages.

[0064] In the first log-likelihood ratio mapping table, each possible voltage distribution combination corresponds to a specific LLR value. By comparing the first voltage distribution combination of the current storage cell with the entries in the mapping table, the system can quickly locate and extract the corresponding LLR value. For example, if a cell's combination is 0-1-1, and the corresponding LLR value in the mapping table is +2.3, the probability of the cell's data being 1 is much higher than the probability of being 0 (approximately e^2.3≈10 times).

[0065] The mapping table contains all possible voltage distribution combinations under the first read voltage (a total of 8, that is, 2^3 three-way response combinations), ensuring that the read result of each memory cell can find the corresponding LLR value.

[0066] Each LLR value in the table is calculated based on the statistical probability of the sample data and reflects the true probability of the data being 0 or 1 for a specific voltage distribution combination. For example, for the "0-0-1" combination, if sample statistics show that the corresponding true data has a 75% probability of being 1 and a 25% probability of being 0, the LLR value for this combination in the mapping table is ln(0.75 / 0.25)≈1.099.

[0067] Step 122 : Based on the first voltage distribution combination, obtain a first log-likelihood ratio value corresponding to the first voltage distribution combination from a first log-likelihood ratio value mapping table.

[0068] Compare the first voltage distribution combination of the current memory cell (e.g., 0-1-1) with the entries in the mapping table. Obtain the corresponding LLR value (e.g., +2.3) from the matching entry. This value represents the logarithmic probability ratio of the memory cell data being 1, directly quantifying the data reliability.

[0069] Step 2: Decode the first data reading result based on the first log-likelihood ratio value to obtain first decoded data.

[0070] Furthermore, during decoding, the ECC decoding module (such as an LDPC decoder) simultaneously receives the first data read result (hard information) and the first log-likelihood ratio (soft information). The hard information provides a preliminary judgment of the data, while the soft information indicates the reliability of this judgment. For example, the decoder assigns a higher confidence weight to bits with larger LLR absolute values. For bits with smaller LLR absolute values ​​(in the overlapping threshold voltage region), the decoder performs more refined error correction based on the correlation of adjacent data, performs iterative decoding, and ultimately outputs decoded data that meets the verification requirements.

[0071] S33: If the decoding of the first data reading result fails, adjust the current right offset reference voltage according to the second preset offset, obtain the first right offset reference voltage, and generate the second read voltage.

[0072] The first right offset reference voltage is greater than the current right offset reference voltage.

[0073] If the first data read result still fails to decode, it indicates that the threshold voltage drift of the memory cell may be more complex (e.g., the right-shift amplitude exceeds the coverage range of the first read voltage). In this case, a target right-shift reference voltage (whose absolute value is greater than that of the initial right-shift reference voltage) is obtained by adding a second preset offset to the initial right-shift reference voltage in the first read voltage. This target right-shift reference voltage replaces the initial right-shift reference voltage and, together with the target left-shift reference voltage and the no-offset reference voltage, forms the second read voltage.

[0074] The current right-offset reference voltage of 8V is adjusted by a second preset offset (a positive value, such as +2V) to obtain a first right-offset reference voltage of 10V (greater than the current right-offset reference voltage). This voltage, together with the first left-offset reference voltage and the no-offset reference voltage, forms the second read voltage, further expanding the rightward detection range to capture memory cells with higher threshold voltages and addressing the limitations of a single left-offset adjustment.

[0075] S34 . Re-read the memory cells on the target word line based on the second read voltage to obtain a second data read result.

[0076] Then, the target word line memory cell is read again using the second read voltage to obtain a response combination of each memory cell under the first left offset, no offset, and first right offset reference voltages to form a second data read result.

[0077] Because the second read voltage is offset more rightward, its read result more accurately reflects severely right-skewed threshold voltage distributions. For example, a memory cell with a very high threshold voltage may appear off (output 1) at the first right-shifted reference voltage, but may be mistakenly interpreted as on (output 0) at the initial right-shifted reference voltage, thus correcting the previous read error.

[0078] In an embodiment of the present application, when only adjusting the left offset reference voltage fails to successfully decode, a preset offset is superimposed on the initial right offset reference voltage so that the absolute value of the target right offset reference voltage is greater than the initial value. This can cover the changes in storage cell characteristics caused by rightward voltage drift, make up for the limitations of a single left offset adjustment, provide decoding possibilities for more complex threshold voltage distribution scenarios, and effectively reduce the overall decoding failure rate.

[0079] As an extension and refinement of the above embodiment, refer to Figure 4 As shown, the embodiment of the present application also provides another flash memory data decoding method, which specifically includes the following steps S35 to S37:

[0080] S35: Decode the second data reading result.

[0081] The description of this step refers to S31 and will not be repeated here.

[0082] S36: If the second data reading result is decoded successfully, obtain and output second decoded data corresponding to the second data reading result.

[0083] In this embodiment of the present application, the decoding process still relies on the ECC decoding module, combining the second data read result and the corresponding second log-likelihood ratio to perform soft decoding. Because the second read voltage simultaneously optimizes the left and right offset reference voltages, covering a wider range of threshold voltage distribution, the corresponding second data read result and second log-likelihood ratio can more accurately reflect the actual state of the storage cell, providing more reliable hard and soft information support for this decoding.

[0084] When the second data read result successfully recovers valid data after decoding, it indicates that the second read voltage has adapted to the current complex threshold voltage drift state of the storage cell (such as a severe rightward shift). At this point, the second decoded data is obtained and output, terminating the entire read and decode process. This step demonstrates the process's effectiveness in handling complex scenarios. By gradually optimizing the reference voltage, successful data acquisition is ultimately achieved, ensuring data read reliability.

[0085] The process of decoding the second data reading result in the above S36 may refer to the process of decoding the second data reading result in the above steps 1 and 2, and specifically includes the following:

[0086] Step a: Obtain a second log-likelihood ratio value according to the second data reading result.

[0087] Step a1: performing statistical analysis on the second data reading result to obtain a second voltage distribution combination corresponding to the memory cell.

[0088] Step a2: Based on the second voltage distribution combination, obtain a corresponding second log-likelihood ratio value.

[0089] Step a21: Obtain a second log-likelihood ratio mapping table corresponding to a second data read voltage.

[0090] The second log-likelihood ratio mapping table includes log-likelihood ratios corresponding to a plurality of voltage distribution combinations under the second read voltage.

[0091] Step a22: Based on the second voltage distribution combination, obtain a first log-likelihood ratio value corresponding to the second voltage distribution combination from a second log-likelihood ratio mapping table.

[0092] Step b: Based on the second voltage distribution combination, obtain a corresponding second log-likelihood ratio value and perform decoding according to the second log-likelihood ratio value and the second data reading result.

[0093] The difference is that, when decoding the second data read result, the log-likelihood ratio value mapping table used is the second log-likelihood ratio value mapping table under the second read voltage.

[0094] This step converts the storage cell voltage distribution characteristics under the second read voltage into quantifiable probability information through a standardized mapping table query mechanism, providing accurate and efficient soft information support for subsequent decoding operations. It is a key technical means to cope with changes in complex storage cell characteristics.

[0095] S37. If the decoding of the second data reading result fails, a decoding failure prompt is generated and output.

[0096] If the second data read result still fails to decode, it indicates that the threshold voltage drift of the memory cell may have exceeded the preset reference voltage adjustment range, or there may be other more complex fault factors (such as physical damage to the memory cell). In this case, a decoding failure prompt is generated and output, providing timely feedback to the system about the data read anomaly so that other measures can be taken.

[0097] It should be noted that, on the basis of the original single offset adjustment, a continuous adjustment mechanism can be added to further improve the adaptability to threshold voltage drift; when the decoding of the first data reading result fails, you can choose not to adjust the right offset reference voltage immediately, but first try to continue to adjust the left offset reference voltage to the left; that is, the first left offset reference voltage is superimposed with the first preset offset, that is, two first preset offsets are superimposed on the current left offset reference voltage, and then combined with the no-offset reference voltage and the current right offset reference voltage to generate a new read data voltage, re-read the data, obtain a new data reading result, and repeat the decoding attempt based on the LLR value.

[0098] Similarly, when the decoding of the second data reading result fails, you can try to continue adjusting the right offset reference voltage to the right; similarly, re-read the data to obtain a new data reading result, and repeat the decoding attempt based on the LLR value until the left offset reference voltage and the right offset reference voltage reach the upper limit respectively. If decoding still fails, generate a decoding failure reminder.

[0099] Furthermore, by adjusting the read voltage over and over again, overcompensation is avoided. Furthermore, a progressive adjustment strategy covering a wider threshold voltage drift range improves the decoding success rate in moderate right-skew scenarios while maintaining low energy consumption, providing a more flexible optimization method for flash memory data reading.

[0100] As an extension and refinement of the above embodiment, the first log-likelihood ratio mapping table is obtained as follows:

[0101] A plurality of sample storage units are obtained in advance according to a first data reading voltage, a first sample data reading result is obtained, and a first log-likelihood ratio mapping table is generated based on a comparison between the first sample data reading result and actual data of the sample storage unit.

[0102] A number of representative sample storage cells (covering cells with different aging levels and different threshold voltage distribution characteristics) are pre-selected. These sample cells are read based on a first read voltage (including a target left offset, no offset, and an initial right offset reference voltage) to obtain three response combinations for each sample cell, i.e., the first sample data read result (e.g., 0-1-1, 1-0-0, etc.).

[0103] The first sample data read results are compared one by one with the actual data (known as 0 or 1) of the sample storage cells, and the probability that each first voltage distribution combination corresponds to the actual data being 0 or 1 is calculated. For example, if the 0-1-1 combination appears 1000 times in the sample, of which the actual data is 1 800 times and 0 200 times, then the probability that the data corresponding to this combination is 1 is 0.8, and the probability that the data is 0 is 0.2.

[0104] According to the above probability calculation results and the definition of log-likelihood ratio, the log-likelihood ratio value corresponding to each first voltage distribution combination is calculated, and the correspondence between the first voltage distribution combination and the log-likelihood ratio value is stored as a first log-likelihood ratio value mapping table.

[0105] It is also necessary to obtain a second log-likelihood ratio mapping table in advance, and adopt the same method to read multiple sample storage units using a second data read voltage to obtain a second sample data reading result. Based on the comparison between the second sample data reading result and the actual data of the sample storage unit, a second log-likelihood ratio mapping table is generated.

[0106] Similarly, multiple sample memory cells are selected and read based on a second read voltage (including a target left offset, no offset, and a target right offset reference voltage). Three response combinations are obtained for each sample cell, representing the second sample data read result. Because the second read voltage has a larger right offset, it covers a different threshold voltage range than the first read voltage. Therefore, the voltage distribution combination of the second sample data read result exhibits new characteristics.

[0107] It should also be noted that corresponding log-likelihood ratio mapping tables can be obtained in advance for a variety of different read voltages, and then in actual applications, corresponding log-likelihood ratio mapping tables can be obtained in a timely manner according to the current read voltage to improve data decoding efficiency; the embodiment of the present application reads multiple sample storage units and compares the reading results of a large number of sample data with the actual data of the samples, which can more comprehensively count the probability characteristics of the real data under different voltage distribution combinations, so that the generated first and second log-likelihood ratio mapping tables are more in line with the characteristics of the actual storage unit, providing an accurate log-likelihood ratio basis for subsequent decoding.

[0108] Through the description of the above implementation methods, those skilled in the art can clearly understand that the method according to the above embodiment can be implemented by means of software plus the necessary general hardware platform, and of course it can also be implemented by hardware, but in many cases the former is a better implementation method.

[0109] Figure 5 This is a structural diagram of a flash memory data decoding device 500 provided by the present disclosure, as shown in FIG. Figure 5 As shown, the apparatus 500 of this embodiment includes:

[0110] A data reading unit 51 is configured to read a memory cell on a target word line in the flash memory based on a current read data voltage to obtain a current data read result; the current read data voltage includes a current left offset reference voltage, a no-offset reference voltage, and a current right offset reference voltage;

[0111] an adjustment unit 52 configured to, when decoding of the current data read result fails, adjust the current left offset reference voltage according to a first preset offset to obtain a first left offset reference voltage to generate a first read voltage; the first read voltage includes the first left offset reference voltage, the no-offset reference voltage, and the current right offset reference voltage; the first left offset reference voltage is less than the current left offset reference voltage;

[0112] The data reading unit 51 is further configured to re-read the storage unit on the target word line based on the first reading voltage to obtain a first data reading result.

[0113] As an optional implementation of an embodiment of the present application, the flash memory data decoding device also includes a decoding unit for decoding the first data read result; if the first data read result is successfully decoded, the first decoded data corresponding to the first data read result is obtained and output; if the decoding of the first data read result fails, the current right offset reference voltage is adjusted according to a second preset offset, and the first right offset reference voltage is obtained to generate a second read voltage; the first right offset reference voltage is greater than the current right offset reference voltage; based on the second read voltage, the storage unit on the target word line is re-read to obtain the second data read result.

[0114] As an optional implementation of an embodiment of the present application, the decoding unit is further used to obtain and output second decoded data corresponding to the second data reading result if the second data reading result is successfully decoded; if the decoding of the second data reading result fails, generate and output a decoding failure prompt.

[0115] As an optional implementation of the embodiment of the present application, the decoding unit is further used to obtain a first log-likelihood ratio value based on the first data reading result; and decode the first data reading result based on the first log-likelihood ratio value to obtain first decoded data.

[0116] As an optional implementation of the embodiment of the present application, the decoding unit is further used to perform statistical analysis on the first data reading result to obtain a first voltage distribution combination corresponding to the storage unit; and based on the first voltage distribution combination, obtain a corresponding first log-likelihood ratio value.

[0117] As an optional implementation of an embodiment of the present application, the decoding unit is also used to obtain a first log-likelihood ratio mapping table corresponding to the first data reading voltage; the first log-likelihood ratio mapping table includes log-likelihood ratios corresponding to multiple voltage distribution combinations under the first reading voltage; based on the first voltage distribution combination, the first log-likelihood ratio corresponding to the first voltage distribution combination is obtained from the first log-likelihood ratio mapping table.

[0118] As an optional implementation of the embodiment of the present application, the decoding unit is further used to obtain multiple sample storage units in advance based on the first data reading voltage, obtain a first sample data reading result, and generate the first log-likelihood ratio mapping table based on the comparison of the first sample data reading result with the actual data of the sample storage unit.

[0119] For the description of the features in the embodiment corresponding to a flash memory data decoding device, reference can be made to the relevant description of the embodiment corresponding to the flash memory data decoding method, which will not be repeated here.

[0120] An embodiment of the present application further provides an electronic device, comprising a memory and a processor, wherein the memory stores a computer program, and the processor is configured to run the computer program to execute the steps of any of the above flash memory data decoding method embodiments.

[0121] An embodiment of the present application further provides a computer-readable storage medium, in which a computer program is stored. The computer program is configured to execute the steps of any of the above-mentioned flash memory data decoding method embodiments when running.

[0122] In an exemplary embodiment, the computer-readable storage medium may include, but is not limited to, various media that can store computer programs, such as a USB flash drive, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk, or an optical disk.

[0123] An embodiment of the present application further provides a computer program product, which includes a computer program. When the computer program is executed by a processor, the steps of any of the above flash memory data decoding method embodiments are implemented.

[0124] An embodiment of the present application also provides another computer program product, including a non-volatile computer-readable storage medium, the non-volatile computer-readable storage medium storing a computer program, and when the computer program is executed by a processor, implementing the steps of any of the above-mentioned flash memory data decoding method embodiments.

[0125] Professionals may further appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the above description has generally described the components and steps of each example according to their functions. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians may use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0126] The above describes in detail a flash memory data decoding method, device, electronic device, and readable storage medium provided by the present application. This article uses specific examples to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only intended to help understand the method and core concept of the present application. It should be noted that for ordinary technicians in this technical field, without departing from the principles of the present application, several improvements and modifications can be made to the present application, and these improvements and modifications also fall within the scope of protection of the claims of the present application.

Claims

1. A flash memory data decoding method, characterized in that: include: Based on the current read data voltage, read the memory cell on the target word line in the flash memory to obtain the current data read result; The current read data voltage includes a current left offset reference voltage, a no-offset reference voltage and a current right offset reference voltage; In the case where the decoding of the current data read result fails, adjusting the current left offset reference voltage according to a first preset offset to obtain a first left offset reference voltage to generate a first read voltage; the first read voltage includes the first left offset reference voltage, the no-offset reference voltage, and the current right offset reference voltage; The first left offset reference voltage is less than the current left offset reference voltage; re-reading the memory cell on the target word line based on the first read voltage to obtain a first data read result; The method further comprises: If the decoding of the first data read result fails and the first left offset reference voltage does not reach the preset left limit reference voltage value, the first left offset reference voltage continues to be adjusted according to the first preset offset, a new left offset reference voltage is obtained, a new read voltage is generated, and the storage unit is re-read based on the new read voltage to obtain a new data read result, until the new left offset reference voltage reaches the preset left limit or the new data read result is decoded successfully.

2. The method according to claim 1, characterized in that The method further comprises: decoding the first data reading result; If the first data reading result is successfully decoded, obtaining and outputting first decoded data corresponding to the first data reading result; If the decoding of the first data read result fails, adjusting the current right offset reference voltage according to a second preset offset to obtain a first right offset reference voltage to generate a second read voltage; the first right offset reference voltage is greater than the current right offset reference voltage; Based on the second read voltage, the memory cells on the target word line are re-read to obtain a second data read result.

3. The method according to claim 2, characterized in that The method further comprises: If the second data reading result is successfully decoded, obtaining and outputting second decoded data corresponding to the second data reading result; If the decoding of the second data reading result fails, a decoding failure prompt is generated and output.

4. The method according to claim 3, characterized in that The method further comprises: Obtaining a first log-likelihood ratio value according to the first data reading result; The first data reading result is decoded based on the first log-likelihood ratio value to obtain first decoded data.

5. The method according to claim 4, characterized in that The obtaining a first log-likelihood ratio value according to the first data reading result includes: Performing statistical analysis on the first data reading result to obtain a first voltage distribution combination corresponding to the storage unit; Based on the first voltage distribution combination, a corresponding first log-likelihood ratio value is obtained.

6. The method according to claim 5, characterized in that The acquiring a corresponding first log-likelihood ratio value based on the first voltage distribution combination includes: Obtaining a first log-likelihood ratio mapping table corresponding to the first data read voltage; the first log-likelihood ratio mapping table includes log-likelihood ratios corresponding to a plurality of voltage distribution combinations under the first read voltage; Based on the first voltage distribution combination, a first log-likelihood ratio value corresponding to the first voltage distribution combination is obtained from the first log-likelihood ratio value mapping table.

7. The method according to claim 6, characterized in that The method further comprises: A plurality of sample storage units are acquired in advance according to the first data reading voltage, a first sample data reading result is acquired, and the first log-likelihood ratio mapping table is generated based on the comparison between the first sample data reading result and actual data of the sample storage units.

8. A flash memory data decoding device, characterized in that: include: A data reading unit, configured to read a storage cell on a target word line in the flash memory based on a current read data voltage, and obtain a current data reading result; The current read data voltage includes a current left offset reference voltage, a no-offset reference voltage and a current right offset reference voltage; an adjustment unit, configured to, when decoding of the current data read result fails, adjust the current left-offset reference voltage according to a first preset offset to obtain a first left-offset reference voltage to generate a first read voltage; the first read voltage includes the first left-offset reference voltage, the no-offset reference voltage, and the current right-offset reference voltage; The first left offset reference voltage is less than the current left offset reference voltage; The data reading unit is further configured to re-read the storage unit on the target word line based on the first read voltage to obtain a first data reading result; The adjustment unit is further configured to, when the decoding of the first data read result fails and the first left offset reference voltage does not reach a preset left limit reference voltage value, continue to adjust the first left offset reference voltage according to the first preset offset amount, obtain a new left offset reference voltage, generate a new read voltage, and re-read the storage unit based on the new read voltage to obtain a new data read result, until the new left offset reference voltage reaches the preset left limit or the new data read result is successfully decoded.

9. An electronic device, characterized in that: include: memory for storing computer programs; A processor, configured to implement the steps of the flash memory data decoding method according to any one of claims 1 to 7 when executing the computer program.

10. A computer-readable storage medium, characterized in that The computer-readable storage medium stores a computer program, wherein when the computer program is executed by a processor, the steps of the flash memory data decoding method according to any one of claims 1 to 7 are implemented.

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