Method of manufacturing integrated circuit device

Abstract

A method of manufacturing an integrated circuit device may include forming a first etch stop layer on a first side of a substrate; a gate structure comprising a gate electrode layer, a first source / drain region and a second source / drain region is formed on the first etching stop layer, the first source / drain region and the second source / drain region are respectively self-aligned with the opposite side walls of the gate structure, and the lower parts of the first source / drain region and the second source / drain region are respectively in contact with and extend to a first occupying part and a second occupying part in the substrate; removing the substrate until the first etching stop layer is exposed from the second surface of the substrate, and simultaneously exposing the first occupying part and the second occupying part; forming a base dielectric layer on the rear sides of the first and second placeholders; and forming a rear conductive line to be electrically connectable to the second source / drain region.

Description

Cross-references to related applications

[0001] This application is based upon and claims the benefit of priority from Korean Patent Application No. 10-2024-0020660 filed on February 13, 2024, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference. Technical Field

[0002] The inventive concept relates to an integrated circuit device and a method of manufacturing the same, and more particularly, to an integrated circuit device in which a power delivery network (PDN) is formed on a backside of the integrated circuit device and a method of manufacturing the same. Background Art

[0003] With the advancement of electronic technology, the miniaturization of integrated circuit devices is rapidly advancing. To efficiently deliver power to highly integrated integrated circuit devices, integrated circuit devices with power delivery networks formed on the backside of the integrated circuit devices have been introduced. These integrated circuit devices are not only complex in structure but also in manufacturing. Therefore, there is a need to reduce the difficulty of the manufacturing process and improve the reliability of the integrated circuit devices. Summary of the Invention

[0004] The inventive concept provides an integrated circuit device having improved operational reliability.

[0005] The inventive concept provides a method of fabricating an integrated circuit device having improved operational reliability.

[0006] According to an embodiment conceived in the present invention, a method for manufacturing an integrated circuit device may include: forming a first etch stop layer on a first surface of a substrate; forming a gate structure including a gate electrode layer, a first source / drain region, and a second source / drain region on the first etch stop layer, wherein the first source / drain region and the second source / drain region can be self-aligned with opposite sidewalls of the gate structure, respectively, and forming the gate structure may include forming a first placeholder and a second placeholder extending into the interior of the substrate, and the lower portion of the first source / drain region and the lower portion of the second source / drain region can contact the first placeholder and the second placeholder, respectively; removing the substrate until the first etch stop layer, the first placeholder, and the second placeholder are exposed; forming a base dielectric layer that completely covers the back side of the first placeholder and the back side of the second placeholder; and forming a rear conductive line that is electrically connected to the second source / drain region and penetrates the base dielectric layer.

[0007] According to an embodiment of the present invention, a method for manufacturing an integrated circuit device may include: forming a first etch stop layer on a first surface of a substrate, the substrate including a first surface and a second surface opposite to the first surface; forming a preliminary channel stack by alternately stacking a plurality of preliminary channel layers and a plurality of sacrificial layers on the first etch stop layer; forming a first opening and a second opening in a stack structure including the preliminary channel stack, the first etch stop layer, and the substrate, the first opening and the second opening exposing a sidewall of a portion of the preliminary channel stack and being self-aligned with the sidewall of the portion of the preliminary channel stack, respectively, wherein the first opening and the second opening may be formed by removing a portion of the preliminary channel stack, the first etch stop layer, and the first etch stop layer at positions spaced a certain distance from each other. a portion of the first opening and a portion of the substrate; forming a first placeholder in the lower portion of the first opening and a second placeholder in the lower portion of the second opening; forming a first source / drain region and a second source / drain region with semiconductor materials on the first placeholder and the second placeholder, respectively; exposing the first placeholder and the second placeholder by removing the substrate until the first etch stop layer is exposed from the second side of the substrate; forming a placeholder protection liner on the exposed surface of the first placeholder and the exposed surface of the second placeholder; removing the rest of the substrate while keeping the first placeholder and the second placeholder; forming a base dielectric layer that completely covers the first placeholder and the second placeholder; and forming a rear conductive line that is electrically connected to the second source / drain region and penetrates the base dielectric layer.

[0008] According to an embodiment of the present invention, a method for manufacturing an integrated circuit device may include: forming a first etch stop layer on a first surface of a substrate, the substrate including a first surface and a second surface opposite to the first surface; forming a preliminary channel stack by alternately stacking a plurality of preliminary channel layers and a plurality of sacrificial layers on the first etch stop layer, wherein the first etch stop layer and the plurality of preliminary channel layers may have etching selectivity with respect to each other; forming a first opening and a second opening in a stack structure including the preliminary channel stack, the first etch stop layer and the substrate, the first opening and the second opening exposing sidewalls of a portion of the preliminary channel stack and being self-aligned with the sidewalls of a portion of the preliminary channel stack, respectively, wherein the first opening and the second opening may be formed by removing a portion of the preliminary channel stack, a portion of the first etch stop layer, and a portion of the substrate at positions spaced a certain distance from each other; forming a first placeholder at a lower portion of the first opening, and a placeholder at a lower portion of the second opening. forming a second placeholder; forming a first source / drain region and a second source / drain region on the first placeholder and the second placeholder respectively with semiconductor materials; forming a first conductive line, the first conductive line being electrically connected to the first source / drain region from the front side of the substrate corresponding to the first surface of the substrate; forming a second conductive line, the second conductive line being electrically connected to the plurality of gate electrode layers from the front side of the substrate; exposing the first placeholder and the second placeholder by removing the substrate from the second surface of the substrate to provide an exposed surface of the first placeholder and an exposed surface of the second placeholder; forming a placeholder protection liner on the exposed surface of the first placeholder and the exposed surface of the second placeholder; removing the rest of the substrate while retaining the first placeholder and the second placeholder; removing the first etch stop layer and a portion of the preliminary channel layer in contact with the first etch stop layer; forming a base dielectric layer that completely covers the first placeholder and the second placeholder; and forming a rear conductive line, the rear conductive line being electrically connected to the second source / drain region while penetrating the base dielectric layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0010] Figure 1 is a schematic planar layout diagram of an integrated circuit device according to some embodiments;

[0011] Figures 2A to 2C According to some embodiments Figure 1 A cross-sectional view of the integrated circuit device taken along line II';

[0012] Figures 3 to 24C is a cross-sectional view illustrating a method of manufacturing an integrated circuit device according to some embodiments;

[0013] Figure 25 is a block diagram illustrating a configuration of a semiconductor chip including an integrated circuit device according to some embodiments;

[0014] Figure 26 is a block diagram illustrating a configuration of a semiconductor chip including an integrated circuit device according to some embodiments; and

[0015] Figure 27 is a block diagram illustrating a configuration of an electronic device including an integrated circuit device according to some embodiments. DETAILED DESCRIPTION

[0016] The terms used herein are for the purpose of describing particular embodiments only and are not intended to be limiting of example embodiments. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0017] Expressions such as “at least one of” when following a list of elements modify the entire list of elements, rather than modifying the individual elements of the list. For example, “at least one of A, B, and C” and similar language (e.g., “at least one selected from the group consisting of A, B, and C”) may be interpreted to mean only A, only B, only C, or any combination of two or more of A, B, and C, such as ABC, AB, BC, and AC.

[0018] When the terms "approximately" or "substantially" are used in conjunction with a numerical value in this specification, the relevant numerical value is intended to include manufacturing or operating tolerances (e.g., ±10%) around the numerical value. In addition, when the words "generally" and "substantially" are used in conjunction with a geometric shape, it is intended that the accuracy of the geometric shape is not required, and that the tolerance of the shape is within the scope of the present disclosure. Moreover, regardless of whether a numerical value or shape is modified to "approximately" or "substantially," it should be understood that these values and shapes should be interpreted as including manufacturing or operating tolerances (e.g., ±10%) around the numerical value. When a range is specified, the range includes all values therebetween, such as increments of 0.1%.

[0019] Although the term "equal to" is used in the description of example embodiments, it should be understood that some imprecision may exist. Therefore, when one element is referred to as being "equal to" another element, it should be understood that the element or value can be "equal to" the other element within a desired manufacturing or operating tolerance (e.g., ±10%).

[0020] The concept of “substantially the same” elements may mean that the elements may be completely the same, or may mean that the elements are determined to be the same in consideration of errors or deviations that occur in a process.

[0021] Hereinafter, some embodiments will be described in detail with reference to the accompanying drawings.

[0022] Figure 1is a schematic planar layout of an integrated circuit device 100 according to some embodiments.

[0023] Reference Figure 1 , the X direction may be a first horizontal direction, and the Y direction may be a second horizontal direction perpendicular to the first horizontal direction. The Z direction may be a vertical direction perpendicular to the plane created by the X direction and the Y direction. The layout of the integrated circuit device 100 will be described in more detail below, but the technical concept of the present invention is not limited to Figure 1 layout.

[0024] The integrated circuit device 100 may include a plurality of active fins ACT extending along a first horizontal direction (X direction) and spaced apart from each other at desired and / or alternatively predetermined intervals in a second horizontal direction (Y direction). The active fins may be P-type active fins or N-type active fins. Furthermore, the integrated circuit device 100 may include a plurality of gate structures GL extending along a second horizontal direction (Y direction) perpendicular to the first horizontal direction (X direction) and spaced apart from each other at desired and / or alternatively predetermined intervals in the first horizontal direction (X direction). The gate structures GL may include a gate electrode layer and a gate insulation layer.

[0025] The integrated circuit device 100 may include a nanosheet stack structure NSS located at an overlapping position where the active fin ACT intersects the gate structure GL. A first source / drain region SD1 may be formed on one side of the nanosheet stack structure NSS, and a second source / drain region SD2 may be formed on the other side of the nanosheet stack structure NSS.

[0026] In the integrated circuit device 100, a transistor TR including a nanosheet stack structure NSS and a gate electrode is formed in the overlapping portion where the active fin ACT intersects the gate structure GL. The transistor TR may comprise a three-dimensional transistor. The transistor TR may be a multi-bridge channel transistor (MBC) including the nanosheet stack structure NSS and the gate structure GL. In some embodiments, the transistor TR may be a single transistor including a single gate electrode layer.

[0027] Figure 2A According to some embodiments Figure 1 1 is a cross-sectional view of the integrated circuit device taken along line II'.

[0028] Reference Figure 2A, the integrated circuit device 100 may include a base dielectric layer 74. With reference to the base dielectric layer 74, the first etch stop layer 12 may be formed on the base dielectric layer 74 in an upward direction or a forward direction (i.e., the Z direction) of the drawing. A nanosheet stack structure NSS and a gate structure GL may be formed above the first etch stop layer 12. The nanosheet stack structure NSS may be located between a plurality of vertically stacked gate electrode layers and may refer to a plurality of channel layers having a nanosheet shape. The gate structure GL may include a gate electrode layer and a gate insulating layer surrounding the gate electrode layer. Hereinafter, for ease of explanation, the gate structure GL may be referred to as including the nanosheet stack structure NSS. Therefore, the gate structure GL may include a gate electrode layer, a gate insulating layer, and a channel layer (or referred to as a gate channel layer).

[0029] exist Figure 2A In the embodiment, the first gate structure GL1 may include: a plurality of first channel layers 14a having a nanosheet shape and stacked on the first etch stop layer 12, a plurality of first gate electrode layers 44a, and a plurality of first gate insulating layers 42a. Each of the first channel layer 14a, the first gate insulating layer 42a contacting the first gate electrode layer 44a, and the first channel layer 14a corresponding to the first gate electrode layer 44a may constitute a transistor.

[0030] On the other hand, Figure 2A As shown, a second gate structure GL2 can be formed above the first gate structure GL1. The second gate structure GL2 includes a nanosheet-shaped first channel layer 14a located on top of the first gate structure GL1. The second gate structure GL2 may include the nanosheet-shaped first channel layer 14a located on top of the first gate structure GL1, a second gate insulating layer 42b, and a second gate electrode layer 44b. The nanosheet-shaped first channel layer 14a, the second gate insulating layer 42b, and the second gate electrode layer 44b located on top of the first gate structure GL1 may constitute a transistor. A first insulating layer 27 may be formed on the sidewalls of the second gate structure GL2. Although the insulating layer 22 is shown as existing independently between the first channel layer 14a and the second gate insulating layer 42b located on top of the first gate structure GL1, the insulating layer 22 may not exist independently. Alternatively, the insulating layer 22 may be combined with the second gate insulating layer 42b to form a single insulating layer. As will be described later, the second gate structure GL2 may be formed using a different manufacturing method than the first gate structure GL1 and may therefore have a different shape than the first gate structure GL1. For the convenience of description, the first gate structure GL1 and the second gate structure GL2 may be referred to as gate structures GL. In some embodiments, the second gate structure GL2 may not exist.

[0031] The first source / drain region 34A and the second source / drain region 34B may be formed along two sidewalls of the first gate structure GL1. The first source / drain region 34A and the second source / drain region 34B may be arranged at a certain interval along the extending direction of the active fin ACT (ie, the first horizontal direction (X direction)). Figure 1 The first source / drain region 34A and the second source / drain region 34B may be self-aligned with both sidewalls of the first gate structure GL1 while exposing both sidewalls of the first gate structure GL1 .

[0032] A first interlayer insulating layer 52, a second interlayer insulating layer 55, and a third interlayer insulating layer 62 may be formed over the second gate structure GL2 and the first source / drain region 34A and the second source / drain region 34B. A first contact plug 54 may be formed on the first source / drain region 34A while penetrating the first interlayer insulating layer 52 and electrically connected to the first source / drain region 34A. A first via plug 58 may be formed on the first contact plug 54 while penetrating the second interlayer insulating layer 55 and electrically connected to the first contact plug 54. A source / drain connection wiring layer 64 may be formed on the first via plug 58 while penetrating the third interlayer insulating layer 62 and electrically connected to the first contact plug 54. The first contact plug 54, the first via plug 58, and the source / drain connection wiring layer 64 constitute a first conductive line that can apply an operating voltage to the first source / drain region 34A.

[0033] On the other hand, a second contact plug 59 is formed on the second gate structure GL2 between the first source / drain region 34A and the second source / drain region 34B, while penetrating the first interlayer insulating layer 52 and the second interlayer insulating layer 55 and electrically connected to the second gate electrode layer 44b of the second gate structure GL2. A gate connection wiring layer 66 is formed on the second contact plug 59, while penetrating the third interlayer insulating layer 62 and electrically connected to the second contact plug 59. The second contact plug 59 and the gate connection wiring layer 66 can constitute a second conductive line that can apply an operating voltage to the first gate structure GL1 and / or the second gate structure GL2. On the other hand, in some embodiments where the integrated circuit device 100 does not have the second gate structure GL2, the second contact plug 59 can be electrically connected to the first gate electrode layer 44a located on top of the first gate structure GL1.

[0034] A power rail 86 for supplying power to the base dielectric layer 74 may be formed on the back side of the base dielectric layer 74. The power rail 86 may be electrically connected to the second source / drain region 34B through the rail via plug 84 and the back contact 82 while penetrating the base dielectric layer 74. Figure 2AAs shown, the top of the track via plug 84 can be located within the base dielectric layer 74. The back contact 82 can contact the second source / drain region 34B while penetrating the base dielectric layer 74, the first etch stop layer 12, and the first channel layer 14a from the top of the track via plug 84. Therefore, the power rail 86, the track via plug 84, and the back contact 82 can form a back conductive line that can apply an operating voltage to the second source / drain region 34B.

[0035] On the other hand, the first placeholder 32A may be formed under the first source / drain region 34A.

[0036] on the other hand, Figure 2A The illustrated integrated circuit device 100 shows that, when viewed along the -Z direction, the base dielectric layer 74 is formed on the first etch stop layer 12. This means that, according to some embodiments, in the integrated circuit device 100, the first etch stop layer 12 may remain on the first channel layer 14a.

[0037] Figure 2B It is along Figure 1 The cross-sectional view of the integrated circuit device according to other embodiments is taken along the line II'. Figure 2A The description of the illustrated embodiment is repeated.

[0038] Reference Figure 2B ,and Figure 2A In contrast, except that the base dielectric layer 74 contacts the first channel layer 14a located at the bottom of the first gate structure GL1, Figure 2B The embodiment shown is Figure 2A Thus, the power rail 86 can be electrically connected to the second source / drain region 34B through the rail via plug 84 and the back contact 82 while penetrating the base dielectric layer 74. Figure 2B As shown, the top of the track via plug 84 may be located in the base dielectric layer 74. The back contact portion 82 may contact the second source / drain region 34B while penetrating the first channel layer 14a from the top of the track via plug 84. Figure 2B The first etch stop layer 12 is shown without it, but a portion of the first etch stop layer 12 may remain in certain areas of the integrated circuit device 100 in some embodiments. Figure 2B The illustrated integrated circuit device 100 shows that the base dielectric layer 74 is formed on the first channel layer 14 a when viewed along the −Z direction.

[0039] Figure 2C It is along Figure 1 The cross-sectional view of the integrated circuit device according to other embodiments is taken along the line II'. Figure 2A The description of the illustrated embodiment is repeated.

[0040] Reference Figure 2C ,and Figure 2A or Figure 2B In contrast, except that the base dielectric layer 74 contacts the first gate insulating layer 42a located at the bottom of the first gate structure GL1, Figure 2C The embodiment shown is Figure 2A or Figure 2B Thus, the power rail 86 can be electrically connected to the second source / drain region 34B through the rail via plug 84 and the back contact 82 while penetrating the base dielectric layer 74. Figure 2C As shown, the top of the track via plug 84 may be located within the base dielectric layer 74. The back contact portion 82 may contact the second source / drain region 34B while penetrating the base dielectric layer 74 from the top of the track via plug 84. Figure 2C The first channel layer 14a at the bottom of the first gate structure GL1 is not shown, but a portion of the first channel layer 14a may be retained in certain areas of the integrated circuit device 100 in some embodiments. In some embodiments, it is not excluded that a portion of the etch stop layer 12 may also be retained in a specific area, depending on the surface profile of the specific area. On the other hand, Figure 2C The integrated circuit device 100 shown in FIG. 1 shows that the base dielectric layer 74 is formed on the first gate insulating layer 42 a when viewed along the −Z direction.

[0041] Figures 3 to 24C is a cross-sectional view illustrating a method of manufacturing the integrated circuit device 100 according to some embodiments. Figures 3 to 24C The cross-section is along Figure 1 A cross-sectional view taken along line II'.

[0042] According to some embodiments, the integrated circuit device 100 may constitute a logic unit including a multi-bridge channel field effect transistor (FET) (MBCFET) device. However, the inventive concept is not limited thereto, and the integrated circuit device 100 may include a planar FET device, a gate-all-around FET device, a fin FET device, and a FET device based on a two-dimensional material (e.g., a MoS2 semiconductor gate electrode).

[0043] Reference Figure 3, a first etch stop layer 12 can be formed on the substrate 10. The substrate 10 may include a first face 10a on its front side and a second face 10b on the back side opposite to the first face 10a in the Z direction. In some embodiments, the substrate 10 may include a Group IV semiconductor (e.g., Si or Ge), a Group IV-IV compound semiconductor (e.g., SiGe or SiC), or a Group III-V compound semiconductor (e.g., GaAs, InAs, or InP). However, as will be described later, the substrate 10 may be a sacrificial substrate because it can be completely removed in subsequent processes. The substrate 10 may have an etching selectivity relative to the first etch stop layer 12 and may be formed of various materials that can support the first gate structure GL1, the second gate structure GL2, etc. formed on the substrate 10. In some embodiments, the substrate 10 may include a bulk silicon substrate, but is not limited thereto.

[0044] Reference Figure 4 , a preliminary channel stack PCS may be formed on the first etch stop layer 12. The preliminary channel stack PCS may include a plurality of preliminary channel layers 14 and a plurality of preliminary sacrificial layers 16. A layer that may contact the first etch stop layer 12 may be the preliminary channel layer 14. In the present embodiment, it is shown that three preliminary sacrificial layers 16 and four preliminary channel layers 14 are formed on the first etch stop layer 12, but the present invention is not limited thereto.

[0045] On the other hand, the first etch stop layer 12 can be formed relatively thin because it can be used as an etch stop layer in the back-side etching process of the substrate 10, which will be described later. In some embodiments, the thickness of the first etch stop layer 12 (i.e., the vertical thickness or the thickness in the Z direction) can be 1 / 4 of the thickness of the preliminary channel layer 14 (or Figure 2A and Figure 7 In some embodiments, the thickness of the first channel layer 14a may range from about 5 nm to about 10 nm, and the thickness of the first etch stop layer 12 may range from about 2 nm to about 5 nm.

[0046] On the other hand, the plurality of preliminary sacrificial layers 16 and the plurality of preliminary channel layers 14 constituting the preliminary channel stack PCS may be formed by an epitaxial growth method, and the plurality of preliminary sacrificial layers 16 and the plurality of preliminary channel layers 14 may include different semiconductor materials.

[0047] In some embodiments, the preliminary sacrificial layer 16 may include SiGe, and the preliminary channel layer 14 may include Si, but is not limited thereto. The plurality of preliminary sacrificial layers 16 and the plurality of preliminary channel layers 14 may have the same thickness, but are not limited thereto.

[0048] Reference Figure 5, a preliminary mask pattern can be formed on the preliminary channel stack PCS. The preliminary mask pattern can be formed by sequentially forming an insulating layer 22, a dummy polysilicon layer 24, and a capping insulating layer 26 on the preliminary channel layer 14 located on top of the preliminary channel stack PCS, and then etching them using an etching mask (not shown). The preliminary mask pattern can be formed into a plurality of portions that are spaced apart at a certain interval in the first horizontal direction (X direction). The insulating layer 22 can constitute a portion of the second gate insulating layer 42b of the second gate structure GL2, as described above with respect to Figure 2A The dummy polysilicon layer 24 may be doped with impurities. The capping insulating layer 26 may include a silicon nitride layer.

[0049] Reference Figure 6 , you can Figure 5 A spacer insulating layer 27 for the spacers is formed on the entire surface of the resultant product. The spacer insulating layer 27 may be formed to a substantially uniform thickness on the exposed surfaces of the insulating layer 22, the dummy polysilicon layer 24, the capping insulating layer 26, and the preliminary channel layer 14. The spacer insulating layer 27 may include a silicon oxide layer.

[0050] Reference Figure 7 , an etching process may be performed on the spacer insulating layer 27 to form a mask pattern, wherein the spacer insulating layer 27 is formed on the sidewall of the preliminary mask pattern, as shown in FIG. Figure 5 As shown. The mask pattern may include an insulating layer 22, a dummy polysilicon layer 24, a capping insulating layer 26, and a spacer insulating layer 27. A first opening 31a and a second opening 31b may be formed between the mask patterns. Next, an etching process may be performed on the preliminary channel stack PCS using the mask pattern having the first opening 31a and the second opening 31b as an etching mask to form a first preliminary source / drain region and a second preliminary source / drain region. The etching process is performed using the mask pattern having the first opening 31a and the second opening 31b as an etching mask until the first opening 31a and the second opening 31b extend to a desired and / or predetermined depth below the first face 10a of the substrate 10 while penetrating the preliminary channel stack PCS and the first etch stop layer 12.

[0051] Portions of the preliminary channel stacks PCS may be removed through an etching process, and the preliminary channel stacks PCS may be separated from each other in the X direction.

[0052] Reference Figure 8AA first placeholder 32A and a second placeholder 32B may be formed on the exposed portion of the substrate 10, respectively. The exposed portion is exposed by extending into the substrate 10 through the first opening 31a and the second opening 31b. The first placeholder 32A and the second placeholder 32B may be epitaxial layers formed on the exposed portion of the substrate 10 by selective epitaxial growth of a semiconductor material. In some embodiments, the first placeholder 32A and the second placeholder 32B may be epitaxially grown Si layers, epitaxially grown SiC layers, or epitaxially grown SiGe layers. In this embodiment, the first placeholder 32A and the second placeholder 32B may be epitaxially grown SiGe layers.

[0053] Subsequently, a semiconductor material doped with impurities may be selectively epitaxially grown on the epitaxially grown first and second placeholders 32A and 32B to form first and second source / drain regions 34A and 34B, respectively. In some embodiments, the impurities may include boron (B), arsenic (As), or phosphorus (P). The first and second source / drain regions 34A and 34B may include, but are not limited to, doped SiGe layers, doped Ge layers, doped SiC layers, or doped InGaAs layers.

[0054] Continue to refer to Figure 8B and Figure 8C , the placeholders and source / drain regions of the PMOS transistor and the NMOS transistor may be different from each other due to their operating characteristics. Figure 8A A case where the gate structure includes a PMOS transistor is shown. Figure 8B and Figure 8C They are respectively Figure 8A The schematic diagram corresponding to the "A" part. Figure 8B A case where the gate structure includes an NMOS transistor is shown. Figure 8C The gate structure includes Figure 8A The process of forming the placeholder and the source / drain regions in the region where the PMOS transistor is formed and the process of forming the placeholder and the source / drain regions in the region where the NMOS transistor is formed may be performed in different steps.

[0055] Reference Figure 8B, a second source / drain region 34B may be formed on the epitaxially grown second placeholder 32B. In some embodiments, the second source / drain region 34B may include a first epitaxial layer 34Ba and a second epitaxial layer 34Bb. In some embodiments, the first epitaxial layer 34Ba may include the same material as the second placeholder 32B. In some embodiments, the first epitaxial layer 34Ba may include the same material as the second placeholder 32B, but the composition ratios thereof may be different. In some embodiments, both the first epitaxial layer 34Ba and the second placeholder 32B may include SiGe layers, but the composition ratios of Si and Ge thereof may be different.

[0056] Reference Figure 8C The second source / drain regions 34B may be formed directly on the epitaxially grown second placeholders 32B. In some embodiments, the second placeholders 32B may include a SiGe layer, and the second source / drain regions 34B may include a semiconductor material layer different from the SiGe layer.

[0057] Reference Figure 9 , you can Figure 8A An insulating layer is formed on the entire surface of the resultant product, wherein the first source / drain region 34A and the second source / drain region 34B are formed to fill the first opening 31a and the second opening 31b, as shown in FIG. Figure 7 As shown. The insulating layer may include a liner insulating layer 35 and a filling insulating layer 37. In some embodiments, the liner insulating layer 35 may include a silicon nitride layer, and the filling insulating layer 37 may include a silicon oxide layer. In some embodiments, the filling insulating layer 37 may include a polysilazane layer called Tosin (Tosz), but is not limited thereto.

[0058] Reference Figure 10 , you can Figure 9 An etching process is performed on the resulting product to retain portions of the liner insulating layer 35 and the filling insulating layer 37 above the first source / drain region 34A and the second source / drain region 34B. At this time, the capping insulating layer 26 can be removed from the mask pattern used to define the first preliminary source / drain region and the second preliminary source / drain region, thereby exposing the dummy polysilicon layer 24.

[0059] Reference Figure 11 , a mask insulating layer 36 may be formed on the remaining portion of the liner insulating layer 35 and the filling insulating layer 37 above the first source / drain region 34A and the second source / drain region 34B, wherein the mask insulating layer 36 may be used to remove the dummy polysilicon layer 24. In some embodiments, the mask insulating layer 36 may include a silicon nitride layer. Figure 10A mask insulating layer material is formed on the entire surface of the resultant product to completely fill the space above the liner insulating layer 35 and the filling insulating layer 37 remaining above the first source / drain region 34A and the second source / drain region 34B, and then an etch-back process is performed until the dummy polysilicon layer 24 is exposed to form a mask insulating layer 36.

[0060] Reference Figure 11 , it is possible to selectively remove only the exposed dummy polysilicon layer 24. At this time, the insulating layer 22 under the dummy polysilicon layer 24 can be retained or removed.

[0061] Reference Figure 12 , the first gate structure GL1 (refer to Figure 2A ) of the plurality of sacrificial layers 16, 16a. The plurality of sacrificial layers 16a can be removed by a radical-assisted SiGe etching (RASE) process. A plurality of first spaces 42 can be generated in the portion of the first gate structure GL1 where the plurality of sacrificial layers 16a have been removed. The surface of the first channel layer 14a can be exposed through the first spaces 42. At this time, the first etch stop layer 12, which is formed thinner than the plurality of sacrificial layers 16a on the substrate 10, can remain without being removed by the RASE process.

[0062] Reference Figure 13 , a first gate insulating layer 42a may be thinly formed on the surface of the first channel layer 14a exposed to the first space 42. The first gate insulating layer 42a may not completely fill the first space 42, and a second space smaller than the first space 42 may remain.

[0063] The first gate insulating layer 42a may include a high-k dielectric film. The high-k dielectric film may include a material having a dielectric constant greater than that of the silicon oxide film. For example, the high-k dielectric film may have a dielectric constant of about 10 to about 25. The high-k dielectric film may include a material selected from the group consisting of hafnium oxide, hafnium oxynitride, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, lead zinc niobate, and combinations thereof, but is not limited thereto.

[0064] The high-k dielectric layer can be formed by an atomic layer deposition (ALD) process, a chemical vapor deposition (CVD) process, or a physical vapor deposition (PVD) process. The thickness of the high-k dielectric film can be about 10 angstroms (Å) to about 40 Å, but is not limited thereto.

[0065] On the other hand, the second gate insulating layer 42 b may be formed on the exposed surfaces of the spacer insulating layer 27 and the insulating layer 22 simultaneously with the formation of the first gate insulating layer 42 a .

[0066] Next, refer to Figure 13A replacement metal gate (RMG) process may be performed on the first gate insulating layer 42a to form a first gate electrode layer 44a, thereby completely filling the remaining portion of the second space. At this time, a second gate electrode layer 44b may be formed on the second gate insulating layer 42b.

[0067] The first gate electrode layer 44a and the second gate electrode layer 44b may include a metal layer or a metal nitride layer. In some embodiments, the first gate electrode layer 44a and the second gate electrode layer 44b may include at least one selected from the group consisting of Ti, W, Al, Ru, Nb, Mo, Hf, Ni, Co, Pt, Yb, Tb, Dy, Er, Pd, TiN, TaN, and combinations thereof, but are not limited thereto.

[0068] Reference Figure 14 , the mask insulating layer 36 , the liner insulating layer 35 , and the filling insulating layer 37 may be removed to expose the first source / drain region 34A and the second source / drain region 34B.

[0069] Reference Figure 15 After forming the second gate structure GL2 and the first interlayer insulating layer 52 , a surface planarization process may be performed on the first interlayer insulating layer 52 .

[0070] For example, refer to Figure 14 and Figure 15 , the mask insulating layer 36, the liner insulating layer 35 and the filling insulating layer 37 can be removed. Figure 13 A chemical mechanical polishing (CMP) process is performed on the entire surface of the resultant product to form a second gate electrode layer 44b having a desired height, and then the mask insulating layer 36, the liner insulating layer 35, and the filling insulating layer 37 may be removed. Subsequently, the first interlayer insulating layer 52 may fill the removed portion from which the liner insulating layer 35 and the filling insulating layer 37 have been removed. Alternatively, in order to Figure 13 The resulting product is obtained Figure 15 The resulting product can be removed, the liner insulating layer 35, the filling insulating layer 37 and the mask insulating layer 36 can be removed, a sacrificial material layer (not shown) can be filled in the removed portion from which the liner insulating layer 35 and the filling insulating layer 37 are removed, a CMP process can be performed on the entire surface thereof to form a second gate electrode 44 b having a desired height, the sacrificial material layer can be removed, and then the first interlayer insulating layer 52 can fill the removed portion from which the sacrificial material is removed.

[0071] Reference Figure 16By removing a portion of the first interlayer insulating layer 52, a first contact hole 53 for exposing the first source / drain region 34A may be formed, and the first contact hole 53 may be filled with a first contact plug 54. Subsequently, a second interlayer insulating layer 55 may be formed on the first interlayer insulating layer 52, a portion of the second interlayer insulating layer 55 may be removed to form a second contact hole 57, and then the second contact hole 57 may be filled to form a first via plug 58.

[0072] Subsequently, a third interlayer insulating layer 62 may be formed on the second interlayer insulating layer 55, a third contact hole 63 may be formed, and then the third contact hole 63 may be filled to form a source / drain connection wiring layer 64. The first contact plug 54, the first via plug 58, and the source / drain connection wiring layer 64 constitute a first conductive line that can apply an operating voltage to the first source / drain region 34A.

[0073] On the other hand, a fourth contact hole 56 penetrating the first interlayer insulating layer 52 and the second interlayer insulating layer 55 may be formed on the second gate electrode layer 44 b, and then the fourth contact hole 56 may be filled to form a second contact plug 59. Subsequently, after forming a fifth contact hole 65 penetrating the third interlayer insulating layer 62 and exposing the second contact plug 59, the fifth contact hole 65 may be filled to form a gate connection wiring layer 66. The second contact plug 59 and the gate connection wiring layer 66 may constitute a second conductive line that may apply an operating voltage to the first gate structure GL1 and the second gate structure GL2.

[0074] Reference Figure 17 , can be flipped Figure 16 The structure of the integrated circuit device 100 can then be manufactured using a process.

[0075] Reference Figure 18 , a portion of the substrate 10 may be partially etched and removed until the first placeholder 32A and the second placeholder 32B are exposed by performing an entire surface etching process on the substrate 10. The etching process for the substrate 10 may be performed by a chemical mechanical polishing process.

[0076] Reference Figure 19, an additional etching process may be performed on the substrate 10 to remove the remaining substrate 10 until the first etch stop layer 12 is exposed. The first etch stop layer 12 may have an etching selectivity relative to the substrate 10, so the first etch stop layer 12 may serve as an etch stop layer. At this time, the first placeholder 32A and the second placeholder 32B may remain without being etched. That is, the substrate 10 may not be completely removed, and portions of the substrate 10 may remain on the sidewalls of the first placeholder 32A and the second placeholder 32B in the form of stringers 10S. In the case of a substrate in which stringers are retained, such as in the case of a bulk silicon substrate, the silicon stringers 10S may be leakage paths between adjacent gate structures (e.g., the first gate structure GL1). Therefore, the stringers 10S need to be completely removed.

[0077] Subsequently, a gate structure separation process may be performed to completely remove the leakage path between the first gate structures GL1 .

[0078] Reference Figure 20 , you can Figure 19 A placeholder protection liner 72 is formed over the entire surface of the resulting product. In some embodiments, the placeholder protection liner 72 may include a silicon nitride layer. Due to the surface profile characteristics of the first and second placeholders 32A and 32B, the thickness t2 of the placeholder protection liner 72 on top of the first and second placeholders 32A and 32B (where the first and second placeholders 32A and 32B have a convex profile) may be greater than its thickness t1 on the first etch stop layer 12 having a flat profile. The placeholder protection liner 72, formed relatively thickly on top of the first and second placeholders 32A and 32B, may protect the first and second placeholders 32A and 32B during a subsequent etching process that may be performed to separate the first gate structure GL1 from each other and remove the stringer 10S.

[0079] Reference Figure 21A When the etching process for separating the first gate structure GL1 is first performed, the sidewalls of the first and second placeholders 32A and 32B are relatively thinner than the tops of the first and second placeholders 32A and 32B, and thus the stringers 10S remaining on the sidewalls of the first and second placeholders 32A and 32B can be quickly exposed to the atmosphere of the etching process. Therefore, during the etching process, the stringers 10S formed on the sidewalls of the first and second placeholders 32A and 32B can be quickly removed while protecting the first and second placeholders 32A and 32B.

[0080] Figure 21AThe embodiment of FIG. 1 shows that the stringer 10S is completely removed due to the etching process mainly performed to separate the first gate structure GL1. In this case, a base dielectric layer 74 may be formed to completely cover the exposed first and second placeholders 32A and 32B, as shown in FIG. Figure 22A In some embodiments, the base dielectric layer 74 may include an oxide layer, such as a silicon oxide layer. Figure 21A The case where the stringer 10S is completely removed is shown, but in some embodiments, the present inventive concept does not exclude that the stringer 10S may remain on the sidewalls of the first placeholder 32A and the second placeholder 32B with a very thin thickness (for example, a thickness of about 8 nm or less), but the thickness does not affect the device characteristics.

[0081] Figure 22A is Figure 21A Figure after forming a base dielectric layer 74 directly on the result product. Figure 22A , a base dielectric layer 74 may be formed while retaining the first etch stop layer 12 .

[0082] Reference Figure 21B , even after the etching process for separating the first gate structure GL1 is first performed, the stringer 10S (refer to Figure 19 ) may still remain on the sidewalls of the first placeholder 32A and the second placeholder 32B. Figure 21B A result product after an etching process for separating the first gate structure GL1 is additionally performed is shown.

[0083] Reference Figure 21B An etching process for separating the first gate structure GL1 may be additionally performed until the first etch stop layer 12 is removed, thereby removing all stringers 10S. In this case, a base dielectric layer 74 may then be formed to completely cover the exposed first and second placeholders 32A and 32B. Figure 22B is Figure 21B Figure after forming a base dielectric layer 74 directly on the result product. Figure 22B After removing the first etch stop layer 12, a base dielectric layer 74 may be formed while exposing the first channel layer 14a of the first gate structure GL1. Figure 21B The stringer 10S is shown as being completely removed from the first placeholder 32A and the second placeholder 32B. However, in some embodiments, the present inventive concept does not exclude the possibility that the stringer 10S may remain on the sidewalls of the first placeholder 32A and the second placeholder 32B with a very thin thickness (e.g., a thickness of about 8 nm or less), which does not affect device characteristics.

[0084] Reference Figure 21CEven after the etching process for separating the first gate structure GL1 is additionally performed, portions of the stringer 10S may remain on the sidewalls of the first and second placeholders 32A and 32B. Figure 21C A result product after further additionally performing an etching process for separating the first gate structure GL1 is shown.

[0085] Reference Figure 21C An etching process for separating the first gate structure GL1 may be further additionally performed until the first channel layer 14a is removed, thereby removing all stringers 10S. In this case, a base dielectric layer 74 may be subsequently formed to completely cover the exposed first and second placeholders 32A and 32B. Figure 22C is Figure 21C Figure after forming a base dielectric layer 74 directly on the result product. Figure 22C After removing the first channel layer 14 a , a base dielectric layer 74 may be formed while exposing a portion of the first gate insulating layer 42 a of the first gate structure GL1 .

[0086] On the other hand, despite Figure 21C The case where the stringer 10S is completely removed from the first placeholder 32A and the second placeholder 32B is shown, but in some embodiments, the present inventive concept does not exclude that the stringer 10S may remain on the sidewalls of the first placeholder 32A and the second placeholder 32B with a very thin thickness (for example, a thickness of about 8 nm or less), which does not affect the device characteristics.

[0087] On the other hand, Figure 21D As shown, when the first channel layer 14a is completely removed and the first gate structure GL1 is separated, even if a portion of the stringer 10S remains, the stringer 10S does not affect the device characteristics. Accordingly, in some embodiments, the stringer 10S may not be completely removed, and all or part of the stringer 10S may remain on the sidewalls of the first placeholder 32A and the second placeholder 32B.

[0088] Figure 22D is Figure 21D Figure after forming a base dielectric layer 74 directly on the result product. Figure 22D The first channel layer 14 a may be removed while retaining the stringer 10S on the sidewalls of the first and second placeholders 32A and 32B, and a base dielectric layer 74 may be formed while exposing a portion of the first gate insulating layer 42 a of the first gate structure GL1 .

[0089] Reference Figure 23A ,exist Figure 22AIn the resulting product, a portion of the base dielectric layer 74 and the second placeholder 32B can be removed to expose the second source / drain region 34B. Subsequently, a back contact 82 can be formed to contact the second source / drain region 34B, and a conductive track via plug 84 can be formed to contact the back contact 82. In some embodiments, the track via plug 84 may include at least one of W, Co, Mo, Ni, Ru, Cu, Al, silicides thereof, and alloys thereof, but is not limited thereto. Alternatively, the track via plug 84 may further include a conductive barrier layer (not shown) in contact with the base dielectric layer 74. The conductive barrier layer may include at least one of Ru, Ti, TiN, Ta, TaN, W, TiSiN, and WSi.

[0090] Reference Figure 23B ,exist Figure 22B In the resulting product, a portion of the base dielectric layer 74 and the second placeholder 32B may be removed to expose the second source / drain region 34B. Subsequently, a back contact 82 may be formed to contact the second source / drain region 34B, and a conductive track via plug 84 may be formed to contact the back contact 82.

[0091] Reference Figure 23C ,exist Figure 22C In the resulting product, a portion of the base dielectric layer 74 and the second placeholder 32B may be removed to expose the second source / drain region 34B. Subsequently, a back contact 82 is formed to contact the second source / drain region 34B, and a conductive track via plug 84 may be formed to contact the back contact 82.

[0092] Reference Figure 24A ,against Figure 23A As a result, a power rail 86 can be formed on the back side where the base dielectric layer 74 is located. The power rail 86 can be electrically connected to the second source / drain region 34B through the track via plug 84 and the back contact 82 while penetrating the base dielectric layer 74.

[0093] Reference Figure 24B ,against Figure 23B As a result, power rails 86 may be formed on the base dielectric layer 74. Figure 24C ,against Figure 23C As a result, power rails 86 may be formed on base dielectric layer 74 .

[0094] Figure 2A 、 Figure 2B and Figure 2C Shown respectively Figure 24A 、 Figure 24B and Figure 24C Being turned upside down.

[0095] Figure 251 is a block diagram illustrating a configuration of a semiconductor chip including an integrated circuit device 100 according to some embodiments. Figure 25 , the semiconductor chip 200 may include a logic region 202, an SRAM region 204, and an input / output region 206. The logic region 202 may include a logic cell region 203. The SRAM region 204 may include an SRAM cell region 205 and an SRAM peripheral circuit region 208. The first transistor 210 may be located in the logic cell region 203, and the second transistor 212 may be located in the SRAM cell region 205. The third transistor 214 may be located in the SRAM peripheral circuit region 208, and the fourth transistor 216 may be located in the input / output region 206.

[0096] The semiconductor chip 200 may include the integrated circuit device 100 according to some embodiments. In some embodiments, the first transistor 210 , the second transistor 212 , the third transistor 214 , and the fourth transistor 216 may include the multi-bridge channel transistors described above.

[0097] Figure 26 1 is a block diagram illustrating a configuration of a semiconductor chip including an integrated circuit device 100 according to some embodiments. Figure 26 , semiconductor chip 250 may include a logic region 252. Logic region 252 may include a logic cell region 254 and an input / output region 256. A first transistor 258 and a second transistor 260 may be located in logic cell region 254. The first transistor 258 and the second transistor 260 may be transistors of different conductivity types. A third transistor 262 may be located in input / output region 256. Semiconductor chip 250 may include integrated circuit device 100 according to some embodiments. In some embodiments, first transistor 258, second transistor 260, and third transistor 262 may include the multi-bridge channel transistors described above.

[0098] Figure 27 is a block diagram illustrating a configuration of an electronic device including an integrated circuit device according to some embodiments. Figure 27 , electronic device 300 may include a system-on-chip 310. System-on-chip 310 may include a processor 311, an embedded memory 313, and a cache memory 315. Processor 311 may include one or more processor cores C1-CN. Processor cores C1-CN may process data and signals. Processor cores C1-CN may include integrated circuit device 100 according to some embodiments.

[0099] One or more of the elements disclosed above may be included or implemented in a processing circuit, such as hardware including logic circuitry; a hardware / software combination such as a processor executing software; or a combination of both. For example, the processing circuit may more specifically include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable gate array (FPGA), a system on a chip (SoC), a programmable logic unit, a microprocessor, an application-specific integrated circuit (ASIC), and the like.

[0100] While the inventive concept has been particularly shown and described with reference to embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. A method for manufacturing an integrated circuit device, the method comprising: forming a first etch stop layer on the first side of the substrate; forming a gate structure including a gate electrode layer, a first source / drain region, and a second source / drain region on the first etch stop layer, wherein the first source / drain region and the second source / drain region are self-aligned with opposite sidewalls of the gate structure, respectively; forming the gate structure includes forming a first placeholder and a second placeholder extending into the interior of the substrate, wherein lower portions of the first source / drain region and the second source / drain region contact the first placeholder and the second placeholder, respectively; removing the substrate until the first etch stop layer, the first placeholder, and the second placeholder are exposed; forming a base dielectric layer that completely covers the back side of the first placeholder and the back side of the second placeholder; and A rear conductive line is formed, the rear conductive line being electrically connected to the second source / drain region and penetrating the base dielectric layer.

2. The method according to claim 1, wherein The gate structure includes the gate electrode layer, the channel layer, and a gate insulating layer between the gate electrode layer and the channel layer, and The channel layer and the first etch stop layer have an etch selectivity to each other.

3. The method according to claim 2, wherein: The thickness of the first etch stop layer is half or less than the thickness of the channel layer, and The channel layer contacts the first etch stop layer.

4. The method according to claim 1, wherein The material of the first source / drain region and the material of the second source / drain region include the same material as the material of the first placeholder and the material of the second placeholder, and A composition ratio of a material of the first source / drain region and a composition ratio of a material of the second source / drain region are different from a composition ratio of a material of the first placeholder and a composition ratio of a material of the second placeholder.

5. The method according to claim 1, wherein The gate structure includes: a plurality of gate electrodes vertically stacked between the first source / drain region and the second source / drain region.

6. The method according to claim 1, after removing the substrate until the first etch stop layer is exposed, the method further comprising: forming a placeholder protection liner on exposed surfaces of the first etch stop layer, the first placeholder, and the second placeholder; as well as The remaining portion of the substrate is removed while maintaining the first placeholder and the second placeholder.

7. The method according to claim 6, wherein: The gate structure includes: a channel layer contacting the first etch stop layer, and Removing the remaining portion of the substrate further includes removing the first etch stop layer until the channel layer in contact with the first etch stop layer is exposed.

8. The method according to claim 6, wherein: The gate structure includes: a channel layer contacting the first etch stop layer, and Removing the remaining portion of the substrate further includes removing the first etch stop layer and a portion of the channel layer contacting the first etch stop layer until a portion of the gate insulating layer is exposed.

9. A method of manufacturing an integrated circuit device, the method comprising: forming a first etch stop layer on a first side of a substrate, the substrate comprising the first side and a second side opposite to the first side; forming a preliminary channel stack by alternately stacking a plurality of preliminary channel layers and a plurality of sacrificial layers on the first etch stop layer; forming a first opening and a second opening in a stack structure including the preliminary channel stack, the first etch stop layer, and the substrate, the first opening and the second opening exposing a sidewall of a portion of the preliminary channel stack and being self-aligned with the sidewall of the portion of the preliminary channel stack, respectively, wherein the first opening and the second opening are formed by removing a portion of the preliminary channel stack, a portion of the first etch stop layer, and a portion of the substrate at positions spaced a distance from each other; forming a first place-occupying portion at a lower portion of the first opening, and forming a second place-occupying portion at a lower portion of the second opening; forming a first source / drain region and a second source / drain region on the first place-occupying portion and the second place-occupying portion respectively using semiconductor material; exposing the first placeholder and the second placeholder by removing the substrate until the first etch stop layer is exposed from the second side of the substrate; forming a placeholder protection liner on the exposed surface of the first placeholder and the exposed surface of the second placeholder; removing a remaining portion of the substrate while maintaining the first placeholder and the second placeholder; forming a base dielectric layer completely covering the first placeholder and the second placeholder; and A rear conductive line is formed, the rear conductive line being electrically connected to the second source / drain region and penetrating the base dielectric layer.

10. The method according to claim 9, wherein: The first etch stop layer and one of the plurality of preliminary channel layers contacting the first etch stop layer have etch selectivities with each other.

11. The method according to claim 9, wherein The material of the first source / drain region and the material of the second source / drain region include the same material as the material of the first placeholder and the material of the second placeholder, and A composition ratio of a material of the first source / drain region and a composition ratio of a material of the second source / drain region are different from a composition ratio of a material of the first placeholder and a composition ratio of a material of the second placeholder.

12. The method according to claim 9, further comprising: After forming the first source / drain region and the second source / drain region, a gate structure is formed, the gate structure including a plurality of gate electrode layers vertically stacked between the first source / drain region and the second source / drain region.

13. The method according to claim 12, wherein: Forming the gate structure includes: removing the plurality of sacrificial layers from the preliminary channel stack; forming a gate insulating layer on an exposed surface of the preliminary channel stack, the exposed surface being exposed to a space where the plurality of sacrificial layers are removed; and The plurality of gate electrode layers are formed on the gate insulating layer to fill the space.

14. The method according to claim 9, further comprising: A first conductive line is formed, wherein The first conductive line is electrically connected to the first source / drain region from the front side of the substrate, and The front side of the substrate corresponds to the first face of the substrate.

15. The method according to claim 12, further comprising: A second conductive line is formed, wherein The second conductive line is electrically connected to the plurality of gate electrode layers.

16. The method according to claim 9, wherein Exposing the first placeholder and the second placeholder includes: Partially removing the substrate from the second side until a portion of the first placeholder and a portion of the second placeholder are exposed; and The substrate is additionally removed until the first etch stop layer is exposed.

17. The method according to claim 16, further comprising: The first etch stop layer and a portion of one of the plurality of preliminary channel layers that is in contact with the first etch stop layer are removed.

18. A method of manufacturing an integrated circuit device, the method comprising: forming a first etch stop layer on a first side of a substrate, the substrate comprising the first side and a second side opposite to the first side; forming a preliminary channel stack by alternately stacking a plurality of preliminary channel layers and a plurality of sacrificial layers on the first etch stop layer, wherein the first etch stop layer and the plurality of preliminary channel layers have an etching selectivity to each other; forming a first opening and a second opening in a stack structure including the preliminary channel stack, the first etch stop layer, and the substrate, the first opening and the second opening exposing a sidewall of a portion of the preliminary channel stack and being self-aligned with the sidewall of the portion of the preliminary channel stack, respectively, wherein the first opening and the second opening are formed by removing a portion of the preliminary channel stack, a portion of the first etch stop layer, and a portion of the substrate at positions spaced a distance from each other; forming a first place-occupying portion at a lower portion of the first opening, and forming a second place-occupying portion at a lower portion of the second opening; forming a first source / drain region and a second source / drain region on the first place-occupying portion and the second place-occupying portion respectively using semiconductor material; forming a first conductive line electrically connected to the first source / drain region from a front side of the substrate corresponding to the first side of the substrate; forming a second conductive line electrically connected to a plurality of gate electrode layers from the front side of the substrate; exposing the first placeholder and the second placeholder by removing the substrate from the second side of the substrate to provide an exposed surface of the first placeholder and an exposed surface of the second placeholder; forming a placeholder protection liner on the exposed surface of the first placeholder and the exposed surface of the second placeholder; removing a remaining portion of the substrate while maintaining the first placeholder and the second placeholder; removing the first etch stop layer and a portion of the preliminary channel layer in contact with the first etch stop layer; forming a base dielectric layer completely covering the first placeholder and the second placeholder; and A rear conductive line is formed, the rear conductive line being electrically connected to the second source / drain region while penetrating the base dielectric layer.

19. The method according to claim 18, wherein The thickness of the first etch stop layer is half or less than the thickness of one of the plurality of preliminary channel layers that is in contact with the first etch stop layer.

20. The method according to claim 18, wherein The substrate comprises a bulk silicon substrate, The first etch stop layer comprises silicon germanium, The plurality of preliminary channel layers include a silicon layer, The plurality of sacrificial layers include silicon germanium, The first placeholder and the second placeholder include silicon germanium, The first source / drain region and the second source / drain region include silicon germanium, A composition ratio of silicon germanium in the first source / drain region and the second source / drain region is different from a composition ratio of silicon germanium in the first placeholder and the second placeholder.

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