Low-sensitivity low-thermal-resistance high-temperature-resistant SiC power semiconductor device packaging framework

Abstract

The invention belongs to the technical field of semiconductor device packaging, and discloses a low-sensitivity, low-thermal-resistance and high-temperature-resistant SiC power semiconductor device packaging framework which comprises an upper substrate, a lower substrate, a decoupling capacitor, a ceramic airtight frame, a bonding wire / metal foil, a power semiconductor chip, a cushion block and a high-temperature encapsulating material. The structural characteristic that the double-sided cooling module is provided with the upper substrate and the lower substrate is utilized, the specially-designed ceramic airtight frame is adopted, and a small airtight system is constructed between the upper substrate and the lower substrate. The packaging framework can provide airtight sealing protection for core components of the module on the premise that the internal and external heat dissipation path length and the commutation loop path length of the double-sided cooling power module are not increased and the low-thermal-resistance and low-parasitic-inductance performance advantages of the module are not affected.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor device packaging, and in particular relates to a low-inductance, low-thermal-resistance, and high-temperature-resistant SiC power semiconductor device packaging architecture and method. Background Art

[0002] Wide bandgap power devices, due to their advantages such as high critical electric field, high thermal conductivity, low on-resistance, high switching speed, and low switching losses, have broad application prospects in a wide range of harsh operating environments, including aerospace, electric vehicles, and energy exploration. To fully leverage the high-temperature and high-pressure operation capabilities of wide bandgap devices, wide bandgap power module packaging technology is developing towards high-temperature resistance, high-pressure resistance, and high reliability. Hermetic sealing plays a key role in high-temperature power module packaging, providing sufficient mechanical protection and high-temperature water and oxygen resistance.

[0003] Compared to traditional single-sided cooled wire-bonded power modules, double-sided cooled SiC power semiconductor modules add additional heat dissipation paths and adopt a three-dimensional commutation structure, which significantly reduces thermal resistance and parasitic inductance, thereby significantly improving the power density of power semiconductor devices. However, the traditional airtight packaging architecture uses a thick airtight cavity to enclose the sealed device, and uses terminals passing through the airtight cavity wall to achieve electrical connection between the inside and outside of the cavity, which significantly increases the length of the device's heat dissipation path and the length of the commutation loop path. In addition, the terminals passing through the airtight cavity need to cooperate well with the sealed device to achieve electrical connection. Therefore, using a traditional airtight architecture to seal a double-sided cooled power semiconductor module will significantly increase the module's thermal resistance and parasitic inductance, while also increasing the difficulty of the manufacturing process.

[0004] To solve the above problems, it is particularly important to design an easy-to-implement hermetic packaging architecture that does not affect the low inductance and low thermal resistance performance of double-sided cooling high-temperature SiC power semiconductor modules.

[0005] Through the above analysis, the problems and defects of the existing technology are as follows:

[0006] Traditional hermetic packaging architectures use an airtight cavity to enclose sealed components, with terminals used to establish electrical connections inside and outside the cavity. This significantly increases the device's heat dissipation path and the length of the commutation circuit. Furthermore, the terminals passing through the cavity must mate well with the sealed component to achieve electrical connectivity. Therefore, using traditional hermetic architectures to seal double-sided cooled power semiconductor modules significantly increases the module's thermal resistance and parasitic inductance, while also increasing the difficulty of the manufacturing process. Summary of the Invention

[0007] In response to the problems existing in the prior art, the present invention provides a low-inductance, low-thermal-resistance, and high-temperature-resistant SiC power semiconductor device packaging architecture.

[0008] The present invention is implemented as follows: a low-inductance, low-thermal-resistance, high-temperature-resistant SiC power semiconductor device packaging architecture includes:

[0009] Upper substrate, lower substrate, decoupling capacitor, ceramic airtight frame, bonding wire / metal foil, power semiconductor chip, spacer, high-temperature potting material;

[0010] Connect the DC+ power terminal and the drain of the upper arm chipset to the DC+ metallization area of the lower substrate, and connect the DC- power terminal to the DC- metallization area of the lower substrate; connect the upper arm Kelvin source, gate, and Kelvin drain signal terminals to the upper arm Kelvin source metallization area, gate metallization area, and DC+ metallization area of the lower substrate, respectively; connect the pad to the power source and AC metallization area of the upper arm power chipset, and use bonding wires or metal foil to connect the Kelvin source and gate of the chip to the metallized conductive pads on the upper arm ceramic airtight frame boss.

[0011] Connect the bottom sealing ring and two conductive pads of the high-arm ceramic airtight frame to the DC+ metallization area, the high-arm Kelvin source metallization area, and the gate metallization area, respectively. Connect the top sealing ring of the high-arm ceramic airtight frame to the AC metallization area. The DC+ metallization area, AC metallization area, and high-arm ceramic airtight frame form the high-arm airtight cavity, ensuring an airtight seal for the high-arm core components.

[0012] Symmetrically, the AC power terminal and the drain of the lower arm chipset are connected to the AC metallization area of the upper substrate, and the Kelvin source, gate, and Kelvin drain signal terminals of the lower arm are respectively connected to the lower arm Kelvin source metallization area, gate metallization area and AC metallization area of the upper substrate; the pad is connected to the power source and DC-metallization area of the lower arm power chipset, and the Kelvin source and gate of the chip are connected to the metallized conductive pads on the lower arm ceramic airtight frame boss using bonding wires or metal foil.

[0013] The bottom sealing ring and two conductive pads of the lower arm's ceramic frame are connected to the AC metallization area, the lower arm's Kelvin source metallization area, and the gate metallization area, respectively. The top sealing ring of the lower arm's ceramic airtight frame is connected to the DC-metallization area. The AC metallization area, DC-metallization area, and lower arm ceramic airtight frame form the lower arm's airtight cavity, ensuring an airtight seal for the lower arm's core components.

[0014] Furthermore, the substrate: processes include but are not limited to copper / silver coated DBC, AMB, DPC;

[0015] Substrate metallization area plating: including but not limited to silver plating, nickel silver plating, nickel plating, nickel gold plating, and gold plating.

[0016] Furthermore, the decoupling capacitor includes but is not limited to ceramic capacitors and film capacitors.

[0017] Furthermore, the ceramic airtight frame: the process includes but is not limited to high-temperature co-firing process and low-temperature co-firing process; the metallized area plating includes but is not limited to silver plating, nickel-silver plating, nickel plating, nickel-gold plating, and gold plating; the ceramic matrix material includes but is not limited to aluminum oxide, aluminum nitride, and silicon nitride.

[0018] Furthermore, the power semiconductor chips include but are not limited to Si-based, SiC-based, and GaN-based power devices;

[0019] The interconnection processes between the chip and the substrate, the terminal and the substrate, and the ceramic frame and the substrate include but are not limited to: silver / copper sintering, welding, transient liquid phase bonding, and ultrasonic bonding.

[0020] Furthermore, the material of the pad includes but is not limited to copper pad, copper diamond pad, silver diamond pad, molybdenum pad, copper molybdenum copper pad; its surface metallization includes but is not limited to silver plating, nickel silver plating, nickel plating, nickel gold plating, and gold plating.

[0021] Furthermore, the high-temperature potting material includes but is not limited to: polyimide, parylene, alumina film, modified glass, and special ceramics.

[0022] The present invention also provides a packaging method for a low-inductance, low-thermal-resistance, high-temperature-resistant SiC power semiconductor device packaging architecture, comprising the following steps:

[0023] (1) providing an upper substrate and a lower substrate, wherein the substrates are prepared by an AMB process, a DBC process, or a DPC process, and the substrate material is silicon nitride, aluminum nitride, or aluminum oxide, and forming a metallized area on the surface of the substrate;

[0024] (2) connecting the power source of the power semiconductor chip to the metallized area of the substrate through a pad, wherein the pad is made of copper, copper diamond, silver diamond, molybdenum or copper molybdenum copper and is metal-plated on the surface;

[0025] (3) connecting the Kelvin source and gate of the power semiconductor chip to the metallized pads on the ceramic airtight frame boss through bonding wires or metal foil;

[0026] (4) preparing a ceramic airtight frame by high-temperature co-firing, low-temperature co-firing or DPC process, and connecting the metal sealing ring of the ceramic airtight frame to the corresponding metallized area of the upper substrate or the lower substrate;

[0027] (5) Decoupling capacitors are set between the positive and negative busbars, and high-temperature potting materials are covered on the chip, interconnection area and internal structure surface to complete the packaging.

[0028] Furthermore, the connection between the chip and the substrate, and between the terminal and the ceramic airtight frame adopts silver sintering, copper sintering, welding, transient liquid phase bonding or ultrasonic bonding process; the high-temperature potting material is polyimide, parylene, alumina film, modified glass or special ceramics.

[0029] In combination with the above technical solutions and the technical problems solved, the advantages and positive effects of the technical solutions to be protected by the present invention are as follows:

[0030] This invention leverages the structural characteristics of a double-sided cooling module, consisting of two upper and lower substrates. By employing a specially designed ceramic airtight frame, a compact airtight system is constructed between the upper and lower substrates. This packaging architecture provides airtight protection for the module's core components without increasing the length of the double-sided cooling power module's internal and external heat dissipation paths or the commutation circuit path, or compromising the module's inherent advantages of low thermal resistance and low parasitic inductance.

[0031] The technical solution of the present invention fills the technical gap in high-performance ceramic airtight double-sided cooling high-temperature power semiconductor device packaging architecture at home and abroad.

[0032] The technical solution of the present invention solves the technical difficulty that traditional airtight architecture is difficult to apply to double-sided cooling high-temperature power semiconductor device packaging, and realizes airtight packaging while ensuring low thermal resistance and low parasitic inductance of the module, thereby enabling the airtight protection capability of the double-sided cooling module.

[0033] The present invention relates to a ceramic hermetic double-sided cooling high-temperature SiC power semiconductor device packaging architecture. The main components include upper and lower ceramic substrates, a ceramic hermetic frame, a SiC power chip, a metal interconnect structure (pads, bonding wires, or metal foil), a decoupling capacitor, and a high-temperature, corrosion-resistant potting material. The substrates are manufactured using AMB, DBC, or DPC processes, and the hermetic frame is manufactured using high-temperature co-firing (HTCC), low-temperature co-firing (LTCC), or direct copper plating (DPC). Silver sintering, copper sintering, welding, or transient liquid phase bonding processes are used to achieve low thermal resistance and high reliability interconnections between the chip, substrate, and frame. The overall structure forms a high-temperature hermetic packaging module suitable for extreme environments above 250°C.

[0034] The present invention addresses the problems of solder joint failure, insufficient airtightness, and increased interface thermal fatigue in traditional double-sided cooled SiC power devices in high temperature environments (>200°C), and proposes a new packaging method that uses a collaborative design of a ceramic airtight frame + metal seal + high-temperature potting material. In the prior art, metal wire bonding and conventional silicone potting materials are prone to migration, cracking, and sealing failure at high temperatures, making it difficult to meet the requirements of high-temperature airtightness and long-term reliability in scenarios such as aerospace and electric vehicle high-voltage platforms. Therefore, the present invention focuses on solving the problems of stress release at the metal / ceramic heterogeneous interface at high temperatures, long-term airtight maintenance, and insulation stability during high-frequency and high-voltage operation.

[0035] By incorporating aluminum nitride (AlN) or silicon nitride (Si3N4) ceramic materials with excellent thermomechanical matching properties, and using sol-gel-modified polyimide, parylene, or specialty ceramic films as high-temperature insulating encapsulation media, this invention significantly improves the device's overall thermal cycling tolerance and breakdown voltage rating. Independently extending the Kelvin source and gate electrodes through a raised metallized pad on top of the ceramic airtight frame reduces dynamic Rds(on) degradation, reduces package parasitic inductance, and improves the reliability and efficiency of high-frequency switching devices.

[0036] Compared with traditional single-sided cooling or non-hermetic packaging technologies, the ceramic airtight double-sided cooling packaging architecture of the present invention achieves systematic improvements in key indicators such as device temperature resistance, power density, airtight life and high-voltage insulation level. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Figure 1 This is a structural diagram of the low-inductance, low-thermal-resistance, high-temperature-resistant SiC power semiconductor device packaging architecture provided by an embodiment of the present invention.

[0038] Figure 2 This is a structural diagram of a specially designed ceramic airtight frame provided in an embodiment of the present invention.

[0039] FIG3( a ) is a structural diagram of a ceramic airtight frame of an upper bridge arm according to an embodiment of the present invention.

[0040] FIG3( b ) is a structural diagram of the ceramic airtight frame of the bridge arm in an embodiment of the present invention.

[0041] Figure 4 It is a top view of the packaging architecture provided by an embodiment of the present invention.

[0042] Figure 5 It is a front view of the packaging architecture provided by an embodiment of the present invention.

[0043] Figure 6 This is a sample diagram of a specially designed ceramic airtight frame provided in an embodiment of the present invention.

[0044] Figure 7 This is a diagram of the internal structure of a sample prepared using the packaging architecture provided in an embodiment of the present invention.

[0045] Figure 8 This is an appearance diagram of a sample prepared using the packaging architecture provided in an embodiment of the present invention.

[0046] Figure 9 This is a model diagram of a double-sided cooling module sealed with a traditional airtight structure according to an embodiment of the present invention.

[0047] Figure 10This is a comparison chart of the parasitic inductance simulation extraction of the double-sided cooling module sealed by the embodiment of the present invention and the traditional airtight architecture.

[0048] Figure 11 This is a thermal simulation comparison diagram of a double-sided cooling module sealed with a traditional airtight structure.

[0049] Figure 1: 1. Upper substrate; 2. Lower substrate; 3. Decoupling capacitor; 4. Ceramic airtight frame; 5. Bonding wire / metal foil; 6. Power semiconductor chip; 7. Spacer; 8. High-temperature potting material; 101. AC metallization area; 102. Kelvin source metallization area of lower bridge arm; 103. Gate metallization area of lower bridge arm; 111. AC terminal; 112. Kelvin drain terminal of lower bridge arm; 113. Gate terminal of lower bridge arm; 114. Kelvin source terminal of lower bridge arm; 201. DC+ metallization area; 202. DC- metallization area; 203. Gate metallization area of upper bridge arm; 204. Kelvin source of upper bridge arm Pole metallization area; 211, DC+ terminal; 212, DC- terminal; 213, upper bridge arm Kelvin drain terminal; 214, upper bridge arm gate terminal; 215, upper bridge arm Kelvin source terminal; 401, ceramic sidewall substrate; 402, ceramic boss; 403, cavity; 411, metallized conductive pad; 412, metallized conductive pad; 413, metallized conductive pad; 421, metallized conductive pad; 422, metallized conductive pad; 423, metallized conductive pad; 431, upper side metal sealing ring; 432, lower side metal sealing ring; 441, metal conductive pad; 442, metal conductive pad. DETAILED DESCRIPTION

[0050] In order to make the purpose, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0051] The purpose of the present invention is to overcome the shortcomings of traditional airtight architecture that are not suitable for double-sided cooling modules, and to provide a ceramic airtight double-sided cooling high-temperature SiC power module packaging architecture, which has the characteristics of airtight core components, low thermal resistance, low inductance, high temperature resistance, and no significant increase in process difficulty.

[0052] like Figure 1 As shown, a low-inductance, low-thermal-resistance, high-temperature-resistant SiC power semiconductor device packaging architecture provided by an embodiment of the present invention includes: an upper substrate 1, a lower substrate 2, a decoupling capacitor 3, a ceramic airtight frame 4, bonding wires / metal foil 5, a power semiconductor chip 6, a spacer 7, and a high-temperature potting material 8;

[0053] The specially designed ceramic airtight frame 4 of the present invention comprises a ceramic sidewall substrate 401, a ceramic boss 402, a cavity 403, metallized conductive pads 411, 412, 413, 421, 422, 423, an upper metal sealing ring 431, a lower metal sealing ring 432, and metal conductive pads 441 and 442. The metallized conductive pads 411, 413, 421, 423 are electrically interconnected with the conductive pad 442 via vertically downward metal vias (completely filled) within the ceramic boss 402. Similarly, the metallized conductive pads 412 and 422 are electrically interconnected with the conductive pad 441 via vertically downward metal vias (completely filled) within the ceramic boss 402.

[0054] The low-inductance, low-thermal-resistance, and high-temperature-resistant SiC power semiconductor device packaging architecture consists of two sets of upper and lower packaging structures arranged in mirror image. The upper and lower bridge arms each have a ceramic airtight frame. Their structures and numbering are shown in Figures 3(a) and 3(b).

[0055] The top of the lower substrate 2 is provided with a DC+ metallization region 201, a DC- metallization region 202, an upper arm Kelvin source metallization region 204, and an upper arm gate metallization region 203. Accordingly, the DC+ power terminal 211 and the upper arm Kelvin drain signal terminal 213 are connected to the DC+ metallization region 201, the upper arm Kelvin source signal terminal 215 is connected to the upper arm Kelvin source metallization region 204, the upper arm gate signal terminal 214 is connected to the upper arm gate metallization region 203, the DC- power terminal 212 is connected to the DC- metallization region, and the two side pads of the decoupling capacitor 3 are connected to the DC+ and DC- metallization regions, respectively.

[0056] The drain of the upper arm power semiconductor chipset is connected to the DC+ metallization area 201 of the lower substrate, the power source is connected to the AC metallization area 101 through a pad, the gate is respectively connected to the metallization pads 412.a and 422.a on the upper arm ceramic airtight frame boss, and the Kelvin source is respectively connected to the metallization pads 411.a, 413.a, 421.a, and 423.a on the upper arm ceramic airtight frame boss.

[0057] The upper metal sealing ring 431.a of the high-arm ceramic airtight frame is connected to the AC metallization area 101, while the lower metal sealing ring 432.a is connected to the DC+ metallization area 201. The AC metallization area, DC+ metallization area, and ceramic airtight frame form the high-arm airtight cavity, ensuring an airtight seal for the high-arm core components. The conductive pad 441.a below the ceramic boss is connected to the high-arm gate metallization area 203, while the conductive pad 442.a below the ceramic boss is connected to the high-arm Kelvin source metallization area 204, providing drive signals for the chip.

[0058] Symmetrically, the bottom of the upper substrate 1 is provided with an AC metallization region 101, a lower-arm Kelvin source metallization region 102, and a lower-arm gate metallization region 103. An AC power terminal 111 and a lower-arm Kelvin drain signal terminal 112 are connected to the AC metallization region 101, a lower-arm Kelvin source signal terminal 114 is connected to the lower-arm Kelvin source metallization region 102, and a lower-arm gate signal terminal 113 is connected to the lower-arm gate metallization region 103.

[0059] The drain of the lower arm power semiconductor chipset is connected to the AC metallization area 101 of the upper substrate, the power source is connected to the DC-metallization area 202 of the lower substrate through a pad, the gate is respectively connected to the metallization pads 412.b and 422.b on the lower arm ceramic airtight frame boss, and the Kelvin source is respectively connected to the metallization pads 411.b, 413.b, 421.b, and 423.b on the boss.

[0060] The upper metal sealing ring 431.b of the lower arm ceramic airtight frame is connected to the DC-metallization region 202, while the lower metal sealing ring 432.b is connected to the AC metallization region 101. The DC-metallization region, AC metallization region, and ceramic airtight frame form the lower arm airtight cavity, ensuring an airtight seal for the lower arm core components. The conductive pad 441.b below the ceramic boss is connected to the lower arm gate metallization region 103, while the conductive pad 442.b below the ceramic boss is connected to the lower arm Kelvin source metallization region 102.

[0061] The device is internally insulated with a high-temperature potting material 8, which covers all surfaces of the module and has good heat resistance and electrical insulation.

[0062] It should be noted that, in order to demonstrate the universal applicability of the airtight double-sided cooling high-temperature SiC power semiconductor module packaging architecture of the present invention, except for the specially designed ceramic airtight frame 4, the rest of the packaging structure is similar to the conventional double-sided cooling SiC power semiconductor module packaging.

[0063] It should be noted that the above materials have a wide range of options, some of which are listed below:

[0064] Substrate: Processes include but are not limited to copper / silver coated DBC, AMB, DPC, etc.

[0065] Substrate metallization area plating: including but not limited to silver plating, nickel silver plating, nickel plating, nickel gold plating, and gold plating.

[0066] Decoupling capacitors: including but not limited to ceramic capacitors, film capacitors, etc.

[0067] Ceramic airtight frame: The process includes but is not limited to high-temperature co-firing process and low-temperature co-firing process; the metallized area plating includes but is not limited to silver plating, nickel-silver plating, nickel plating, nickel-gold plating, gold plating, etc.; the ceramic base material includes but is not limited to alumina, aluminum nitride, silicon nitride, etc.

[0068] Power semiconductor chips include but are not limited to Si-based, SiC-based, GaN-based and other power devices.

[0069] The interconnection processes between chip and substrate, terminal and substrate, ceramic frame and substrate include but are not limited to: silver / copper sintering, welding, transient liquid phase bonding, ultrasonic bonding, etc.

[0070] The materials of the pads include but are not limited to copper pads, copper diamond pads, silver diamond pads, molybdenum pads, copper molybdenum copper pads, etc.; the surface metallization includes but is not limited to silver plating, nickel silver plating, nickel plating, nickel gold plating, gold plating, etc.

[0071] Potting materials include but are not limited to: polyimide, parylene, alumina film, modified glass, special ceramics, etc.

[0072] It should be noted that the specific connection process and component metallization coating can be determined by the module's application scenario. The bonding wire / metal foil material and wire diameter are determined by the chip pad metallization material and size. The ceramic airtight frame material, dimensions, thickness, number of conductive pads, electrical connection logic, and specific manufacturing process used are determined by factors such as the number of chipsets, the expected application scenario, process manufacturing capabilities, and cost. Of course, the ceramic frame structure placed within the module is not limited to the specific ceramic frame described in this invention, and the electrical logic and other aspects can be modified according to actual needs.

[0073] The core of the present invention lies in: using a specially designed ceramic airtight frame as the side wall of the airtight sealed cavity, and the upper and lower substrates of the double-sided cooling module as the upper and lower covers of the airtight sealed cavity, a small airtight system is constructed inside the double-sided cooling module to provide airtight protection for the core components of the power module such as chips, bonding wires, and gaskets. Unlike the traditional external surrounding airtight sealing architecture, the airtight sealed cavity described in the present invention utilizes the structural characteristics of the double-sided cooling module itself to construct an airtight system inside the module, without increasing the internal and external heat dissipation path length and the commutation circuit path length of the double-sided cooling SiC power module (that is, ensuring the advantages of low inductance and low thermal resistance), nor significantly increasing the difficulty of power module preparation.

[0074] In addition, the external drive signal (small current) is introduced into the airtight sealed cavity through the internal vias of the ceramic airtight frame, and the thick metallized areas of the upper and lower substrates serve as the upper and lower covers of the airtight sealed cavity and carry the high power level current at the same time. This design effectively avoids the problem of the co-fired ceramic having a metallized layer that is too thin to carry large current.

[0075] Specific embodiment:

[0076] In this embodiment, both the upper and lower arms have chipsets consisting of two SiC power chips connected in parallel. It should be noted that the chips in a chipset can be two, three, or even more chips connected in parallel, simply by adjusting the size of the ceramic frame or using multiple ceramic frames to group them together for airtightness.

[0077] In this embodiment, the upper and lower bridge arms each have a ceramic airtight frame, and their structures and numbers are shown in FIG3( a ) and FIG3( b ).

[0078] The specially designed ceramic airtight frame 4 of the present invention comprises a ceramic sidewall substrate 401, a ceramic boss 402, a cavity 403, metallized conductive pads 411, 412, 413, 421, 422, 423, an upper metal sealing ring 431, a lower metal sealing ring 432, and metal conductive pads 441 and 442. The metallized conductive pads 411, 413, 421, 423 are electrically interconnected with the conductive pad 442 via vertically downward metal vias (completely filled) within the ceramic boss 402. Similarly, the metallized conductive pads 412 and 422 are electrically interconnected with the conductive pad 441 via vertically downward metal vias (completely filled) within the ceramic boss 402.

[0079] It should be noted that the size, position of the ceramic frame and the boss, as well as the number of conductive pads and electrical interconnection logic can be adjusted according to actual needs.

[0080] In this embodiment, a ceramic airtight frame made of alumina was prepared through a high-temperature co-firing process. The outer length and width of the ceramic frame are 16*16mm, the boss thickness is 0.8mm, the length and width of the cavity are 8mm*13mm, the sidewall thickness of the ceramic frame is 1.5mm, and the coating is electroless nickel-gold (ENIG). In addition, a 0.2mm thick Kovar is welded to the ceramic airtight frame through a high-temperature brazing process to serve as a stress buffer layer. The total thickness of the ceramic frame is 2mm, which is consistent with the internal thickness of conventional double-sided cooling power semiconductor modules, such as Figure 5 shown.

[0081] In this embodiment, a silicon nitride AMB substrate is selected, the silicon nitride ceramic thickness is 0.32 mm, the copper thickness is 0.3 mm, and the surface treatment is electroless nickel-gold plating (ENIG); the chip metallization is nickel-palladium-gold, and the copper terminal surface treatment is electroless nickel-gold plating (ENIG); the pad is a copper-molybdenum alloy containing 70% molybdenum, and the surface treatment is nickel-silver.

[0082] In this embodiment, the insulation is a composite conformal coating composed of a 15 μm thick Parylene-HT film and a 90 nm thick aluminum oxide inorganic layer film deposited inside and outside the module.

[0083] like Figure 7 、 Figure 8 The specific connection and potting of each part in the embodiment are described as follows:

[0084] 1. Connection instructions for chips and other core components:

[0085] The drain of the upper bridge arm power semiconductor chipset is connected to the DC+ metallization area 201 of the lower substrate, and the power source is connected to the AC metallization area 101 through a pad;

[0086] The drain of the lower bridge arm power semiconductor chipset is connected to the upper substrate AC metallization region 101 , and the power source is connected to the upper substrate DC-metallization region 202 through a pad.

[0087] The gate of the upper arm power semiconductor chipset is connected to the metallized pads 412.a and 422.a on the upper arm ceramic airtight frame boss through bonding wires; the Kelvin source of the upper arm power semiconductor chipset is connected to the metallized pads 411.a, 413.a, 421.a, and 423.a on the upper arm ceramic airtight frame boss through bonding wires.

[0088] The gate of the lower arm power semiconductor chipset is connected to the metallized pads 412.b and 422.b on the lower arm ceramic airtight frame boss through bonding wires; the Kelvin source of the lower arm power semiconductor chipset is connected to the metallized pads 411.b, 413.b, 421.b, and 423.b on the lower arm ceramic airtight frame boss through bonding wires.

[0089] 2.Terminal connection instructions:

[0090] The top of the lower substrate 2 is provided with a DC+ metallization region 201, a DC- metallization region 202, an upper arm Kelvin source metallization region 204, and an upper arm gate metallization region 203. Accordingly, the DC+ power terminal 211 and the upper arm Kelvin drain signal terminal 213 are connected to the DC+ metallization region 201, the upper arm Kelvin source signal terminal 215 is connected to the lower arm Kelvin source metallization region 204, the upper arm gate signal terminal 214 is connected to the upper arm gate metallization region 203, the DC- power terminal 212 is connected to the DC- metallization region, and the decoupling capacitor 3 is connected to the DC+ and DC- metallization regions, respectively.

[0091] The bottom of the upper substrate 1 is provided with an AC metallization region 101, a lower-arm Kelvin source metallization region 102, and a lower-arm gate metallization region 103. Accordingly, an AC power terminal 111 and a lower-arm Kelvin drain signal terminal 112 are connected to the metallization region 101, a lower-arm Kelvin source signal terminal 114 is connected to the lower-arm Kelvin source metallization region 102, and a lower-arm gate signal terminal 113 is connected to the lower-arm gate metallization region 103.

[0092] 3. Ceramic airtight frame connection instructions:

[0093] The upper metal sealing ring 431.a of the high-arm ceramic airtight frame is connected to the AC metallization area 101, while the lower metal sealing ring 432.a is connected to the DC+ metallization area 201. The AC metallization area, DC+ metallization area, and ceramic airtight frame form the high-arm airtight cavity. The conductive pad 441.a below the ceramic boss is connected to the high-arm gate metallization area 203, while the conductive pad 442.a below the ceramic boss is connected to the high-arm Kelvin source metallization area 204.

[0094] The upper metal sealing ring 431.b of the lower arm ceramic airtight frame is connected to the DC-metallization region 202, while the lower metal sealing ring 432.b is connected to the AC metallization region 101. The DC-metallization region, the AC metallization region, and the ceramic airtight frame form the lower arm airtight cavity. The conductive pad 441.b below the ceramic boss is connected to the lower arm gate metallization region 103, while the conductive pad 442.b below the ceramic boss is connected to the lower arm Kelvin source metallization region 102.

[0095] 4. Potting instructions:

[0096] In this embodiment, Kapton tape is used to mask areas where no insulating material is required, a 15 μm Parylene HT layer is formed by CVD, and then a 90 nm alumina inorganic layer is formed by ALD to form a high-temperature resistant and highly insulating composite conformal coating 8.

[0097] The relevant evidence of the technical effects achieved by the embodiments of the present invention is as follows:

[0098] The model of the ceramic airtight double-sided cooling high-temperature power semiconductor device packaging architecture of the present invention is as follows Figure 9 As shown in (a), a model of a double-sided cooling power semiconductor device packaging architecture using a traditional airtight housing is established. Figure 9 (b) is shown. The parasitic inductance of the two is extracted by simulation under 100kHz conditions. The results are as follows Figure 2 As shown; the embodiment of the present invention maintains the advantage of low parasitic inductance of the double-sided module, the parasitic inductance is only 3.43nH, as shown Figure 10 (a); On the contrary, the module sealed with a traditional airtight structure extends the path length of the commutation loop, which significantly increases the parasitic inductance. The extracted parasitic inductance is 8.55nH, which is 249% higher than that of the embodiment of the present invention. Figure 10 (b) As shown. Under the same loss and heat dissipation conditions, thermal simulation is performed on the two. The thermal simulation results of the embodiment of the present invention are as follows. Figure 11 As shown in (a), the thermal simulation results of the package using the traditional airtight architecture are as follows Figure 11 (b) Traditional airtight architectures add a thick, low-thermal-conductivity Kovar layer to the heat dissipation path, significantly increasing thermal resistance. However, the present invention maintains the module's inherent heat dissipation path. This embodiment maintains the low thermal resistance advantage of a double-sided cooling module, achieving a junction temperature 34% lower than modules packaged using traditional airtight architectures.

[0099] Example 1:

[0100] In a typical high-power density application, a silicon nitride (Si3N4) ceramic substrate is selected. The upper and lower substrates are prepared using an active metal brazing (AMB) process. The metal layer uses copper (Cu) and is nickel-gold plated (Ni / Au) on the surface to improve interface stability and oxidation resistance. The power semiconductor chip is a 1200V-rated SiC MOSFET chip. The power source is connected to the metallized area of the lower substrate through a silver sintering process to achieve excellent interface thermal stability at high temperatures. The chip's Kelvin source and gate are connected to the metallized pads on the top of the ceramic airtight frame via aluminum bonding wires (Al-bondwire), respectively, to achieve independent gate control circuits and improve switching transient response speed.

[0101] The ceramic airtight frame is made of aluminum nitride (AlN) ceramic and is sealed to the upper and lower substrates via a metal sealing ring at the bottom, ensuring the device maintains excellent airtightness even under long-term operation at 250°C. A sol-gel, high-temperature, corrosion-resistant organic-inorganic hybrid material is used as the encapsulation medium within the frame, completely encapsulating the chip, bonding area, and decoupling capacitors, effectively improving the insulation withstand voltage rating. The decoupling capacitors are high-temperature tantalum capacitors, connected in series between the busbars within the ceramic frame to optimize DC bus stability and electromagnetic interference suppression during device switching transients.

[0102] Example 2:

[0103] In the device architecture designed for extreme aerospace environments, aluminum nitride (AlN) substrates are used to fabricate the upper and lower substrates via a direct copper bonding (DBC) process. The copper layer is silver-plated (Ag) to reduce contact resistance and ensure compatibility with subsequent bonding processes. The power semiconductor chip selected is a 650V-rated SiC JBS (junction barrier Schottky) device. The chip's power source is connected to the lower substrate metallization layer via nano-silver paste sintering to reduce thermomechanical stress at the contact interface. The Kelvin source and gate electrodes are connected via a copper interlayer (Cuclip) instead of traditional bonding wires, achieving an ultra-low parasitic inductance structure and further improving high-frequency switching characteristics.

[0104] The ceramic airtight frame utilizes a multi-layer silicon nitride (MLSiN) composite ceramic structure, with top and bottom metallized sealing areas silver-sintered to the upper and lower substrates to form an integral airtight cavity. The internal potting material utilizes siloxane-modified polyimide (Si-PI), a high-temperature insulating material that fully covers the chip surface and internal metal connection areas, enhancing high-temperature insulation strength. The decoupling capacitors utilize high-temperature stable ceramic capacitors (C0G / NP0 dielectrics) to quickly suppress transient voltage spikes on the DC bus, ensuring the device's electrical stability and long-term reliable operation in harsh environments.

[0105] The above description is only a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any modifications, equivalent substitutions and improvements made by any technician familiar with this technical field within the technical scope disclosed by the present invention and within the spirit and principles of the present invention should be covered by the scope of protection of the present invention.

Claims

1. A low-inductance, low-thermal-resistance, high-temperature-resistant SiC power semiconductor device packaging architecture, characterized in that: include: Upper substrate, lower substrate, decoupling capacitor, ceramic airtight frame, bonding wire or metal foil, power semiconductor chip, spacer and high-temperature potting material; The upper and lower substrates are respectively provided with metallized areas and are connected to the power semiconductor chip and terminals. The power source of the power semiconductor chip is connected to the metallized area of the substrate through a pad, and the Kelvin source and gate of the chip are connected to the metallized conductive pads on the ceramic airtight frame boss through bonding wires or metal foil; the decoupling capacitor is arranged between the positive and negative busbars, and the potting material covers all surfaces of the device that need to be insulated. The ceramic airtight frame is connected to the corresponding metallized area of the upper substrate or the lower substrate through a metal sealing ring and a conductive pad, thereby achieving airtight sealing and electrical connection.

2. The low-inductance, low-thermal-resistance, high-temperature-resistant SiC power semiconductor device packaging architecture according to claim 1, characterized in that: The upper substrate and the lower substrate are made by high-temperature co-firing, low-temperature co-firing, AMB, DBC or DPC process. The substrate materials include silicon nitride, aluminum nitride, diamond, diamond mixed ceramic, zirconium oxide toughened aluminum oxide or aluminum oxide. The metallized area materials on both sides include silver, aluminum, and copper. The surface coating of the metallized area is silver plating, nickel-silver plating, nickel plating, nickel-gold plating, gold plating or bare copper.

3. The low-inductance, low-thermal-resistance, high-temperature-resistant SiC power semiconductor device packaging architecture according to claim 1, characterized in that: The decoupling capacitor is a ceramic capacitor or a film capacitor.

4. The low-inductance, low-thermal-resistance, high-temperature-resistant SiC power semiconductor device packaging architecture according to claim 1, characterized in that: The ceramic airtight frame is made by a high-temperature co-firing process, a low-temperature co-firing process, an AMB process, a DBC process or a DPC process. The base material is silicon nitride, aluminum nitride, diamond, diamond mixed ceramic, zirconium oxide toughened aluminum oxide or aluminum oxide. The metallized area is silver-plated, nickel-silver-plated, nickel-plated, nickel-gold-plated, gold-plated or bare copper. The boss conductive pad of the ceramic airtight frame is electrically connected to its external conductive pad.

5. The low-inductance, low-thermal-resistance, high-temperature-resistant SiC power semiconductor device packaging architecture according to claim 1, characterized in that: The power semiconductor chip includes a Si-based, SiC-based, GaN-based, diamond-based or gallium oxide-based power device, and the interconnection between the chip, terminal, ceramic frame and substrate adopts silver sintering, copper sintering, welding, hot pressing bonding, transient liquid phase bonding or ultrasonic bonding process.

6. The low-inductance, low-thermal-resistance, high-temperature-resistant SiC power semiconductor device packaging architecture according to claim 1, characterized in that: The pad material is copper, copper diamond, silver diamond, carbon-based reinforced metal, molybdenum or copper-molybdenum-copper, and the pad surface is silver-plated, nickel-silver-plated, nickel-plated, nickel-gold-plated, gold-plated or bare copper.

7. The low-inductance, low-thermal-resistance, high-temperature-resistant SiC power semiconductor device packaging architecture according to claim 1, characterized in that: The bonding wire is a gold wire, an aluminum wire, a copper wire or an alloy wire thereof, and the metal foil is a copper foil, an aluminum foil, a silver foil or a metal composite foil.

8. The low-inductance, low-thermal-resistance, high-temperature-resistant SiC power semiconductor device packaging architecture according to claim 1, characterized in that: The high-temperature potting material is polyimide, parylene, aluminum oxide film, modified glass or special ceramics.

9. A packaging method for a low-inductance, low-thermal-resistance, high-temperature-resistant SiC power semiconductor device packaging architecture, characterized in that: The following steps are involved: (1) providing an upper substrate and a lower substrate, wherein the substrates are manufactured by high-temperature co-firing, low-temperature co-firing, AMB, DBC or DPC processes, and the substrate materials include silicon nitride, aluminum nitride, diamond, diamond-mixed ceramic, zirconium oxide toughened aluminum oxide or aluminum oxide, and the metallized area materials on both sides of the substrates include silver, aluminum, and copper, and the surface coating of the metallized area is silver-plated, nickel-silver-plated, nickel-plated, nickel-gold-plated, gold-plated or bare copper; (2) connecting the power source of the power semiconductor chip to the metallized area of the lower substrate through a pad, wherein the pad is made of copper, copper diamond, silver diamond, carbon-based reinforced metal, molybdenum or copper molybdenum copper, and the surface is metal-plated; (3) connecting the Kelvin source and gate of the power semiconductor chip to the metallized pads on the ceramic airtight frame boss through bonding wires or metal foil; (4) preparing a ceramic airtight frame by a high-temperature co-firing process, a low-temperature co-firing process, an AMB process, a DBC process, or a DPC process, and connecting the bottom and top metal sealing rings and the external conductive metal pads of the ceramic airtight frame to the corresponding metallized areas of the upper substrate or the lower substrate to achieve airtight sealing and electrical connection; (5) Decoupling capacitors are set between the positive and negative busbars, and high-temperature potting materials are covered on the chip, interconnection area and internal structure surface to complete the packaging.

10. The packaging method of the low-inductance, low-thermal-resistance, high-temperature-resistant SiC power semiconductor device packaging architecture according to claim 9, characterized in that: The connection between the chip and the substrate, and between the terminal and the ceramic airtight frame adopts silver sintering, copper sintering, welding, hot pressing bonding, transient liquid phase bonding or ultrasonic bonding process; the high-temperature potting material is polyimide, parylene, aluminum oxide film, modified glass or special ceramics.

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