Phase controller of switching converter for measuring load current under light load

Abstract

According to one aspect of the present application, a multi-phase switching converter is provided that includes a power stage and a phase controller that provides a regulated supply voltage based on an input voltage under light load conditions. The power stage receives a phase control signal and drives an inductor to generate an inductive current according to the phase control signal, wherein a load current of the multiphase switching converter is formed by the inductive current. The phase controller receives a current signal from the power stage at the pin, the current signal representing an inductive current in the power stage in an analog continuous form. The phase controller integrates the current signal in the analog continuous form to generate a voltage output representing the magnitude of the load current, and determines the magnitude of the load current according to the voltage output.

Description

Technical Field

[0001] The present patent application is related to and claims priority from a pending Indian provisional patent application, entitled “Anaccurate method to measure low load currents in AOT (adaptive ON-time) DC-DC converters,” filed on May 15, 2024, with attorney case number AURA-61-INPR, which is incorporated herein in its entirety to the extent not inconsistent with the description of the present application.

[0002] The current application is related to and claims priority from a U.S. formal patent application, entitled “PHASECONTROLLER OF A SWITCHING CONVERTER MEASURING LOAD-CURRENT UNDER LIGHT LOAD,” filed April 17, 2025, and filed with attorney case number AURA-065-US, which is incorporated herein by reference in its entirety to the extent not inconsistent with the description of this application.

[0003] Embodiments of the present application generally relate to a switching converter, and are specifically used to measure a load current in the switching converter under light load. Background Art

[0004] As is well known in the relevant field, a switching converter is a component that converts a certain input AC (alternating current) or DC (direct current) voltage into a desired DC output voltage. Switching converters can be used as standalone power supplies or as voltage regulators in various environments, such as laptops and mobile phones.

[0005] Switching converters typically use multiple power stages in conjunction with a phase controller. The phase controller provides control signals to each power stage, causing it to generate the desired load current. Each active power stage is driven to generate a corresponding portion of the desired load current in a corresponding phase of a series, hence the name multiphase switching converter.

[0006] Switching converters typically operate under light-load conditions. Light-load conditions are characterized by a small load current demand (i.e., a small fraction, such as less than 10% of the maximum rated power). It is generally desirable for switching converters to operate efficiently even under light-load conditions.

[0007] Achieving such high efficiency requires accurate load current measurement, which the phase controller then uses to drive the power stage. However, accurately measuring the load current at light loads can be challenging, as the total rated load current range at light loads is many times wider than the rated load current range at light loads.

[0008] Several aspects of the present application relate to measuring load current in a switching converter under light load. Summary of the Invention

[0009] According to one aspect of the present application, a multiphase switching converter is provided for providing a regulated power supply voltage based on an input voltage under light load conditions. The multiphase switching converter includes:

[0010] a power stage coupled to receive a phase control signal and drive an inductor to generate an inductor current according to the phase control signal, wherein a load current of the multi-phase switching converter is formed by the inductor current; and

[0011] a phase controller coupled to receive a current signal from the power stage, the current signal representing an inductor current in the power stage in analog continuous form, the phase controller being configured to:

[0012] The current signal in analog continuous form is integrated to generate a voltage output representing the magnitude of the load current; and the magnitude of the load current is determined based on the voltage output.

[0013] Optionally, the phase controller includes:

[0014] a pin receiving the current signal from the power stage;

[0015] a main control signal generator module coupled to receive the regulated power supply voltage, the first reference voltage of the expected magnitude, and the magnitude of the on-time of the phase controller, and to generate a common control signal having corresponding characteristics;

[0016] a phase distributor coupled to receive the common control signal and generate the phase control signal based on a transition of the common control signal; and

[0017] a current measurement module coupled to receive the current signal and determine the magnitude of the load current, wherein the current measurement module comprises:

[0018] an integrator module coupled to receive the current signal and provide the voltage output; and

[0019] A processing module is coupled to receive the voltage output, determine the magnitude of the on-time based on the magnitude of the voltage output, and provide the magnitude of the on-time to the main control signal generator block.

[0020] Optionally, the current measurement module includes a first resistor coupled between the pin and the integrator block,

[0021] Wherein, the integrator block includes:

[0022] a transconductance amplifier characterized by a transconductance value (gm), the transconductance amplifier coupled to receive a voltage drop across the first resistor as a differential input and to generate an output current from an output node proportional to a magnitude of the voltage drop caused by the current signal flowing through the first resistor; and

[0023] a capacitor having a first end and a second end, wherein the first end of the capacitor is coupled to the output node and the second end of the capacitor is coupled to a constant reference potential, the capacitor being characterized by a capacitance value, the capacitor being coupled to receive the output current of the transconductance amplifier and to provide the voltage output at the first end;

[0024] Wherein, the processing block includes:

[0025] a comparator, configured to compare a voltage at a first terminal of the capacitor with a threshold voltage, wherein when the voltage at the first terminal is lower than the threshold voltage, the comparator triggers a reset signal;

[0026] a counter coupled to receive the reset signal and to generate a count of the number of times the reset signal is triggered within a sampling window; and

[0027] a mapping module coupled to receive the count and map the count to a corresponding magnitude of the on-time;

[0028] wherein the threshold voltage is proportional to a predetermined amount of change in the amount of charge in the capacitor,

[0029] The duration of the sampling window is selected to be greater than the time required for the voltage at the first end of the capacitor to change by the threshold voltage.

[0030] Optionally, the current signal is proportional to the inductor current, and the inductor current is scaled by a scaling factor to obtain the current signal.

[0031] Optionally, the mapping module includes a lookup table comprising a plurality of entries to perform the mapping, wherein each entry in the plurality of entries includes a range of the count and a corresponding size of the on-time.

[0032] Optionally, the integrator module further includes a switch coupled across the capacitor, the switch being operable to close when the reset signal is triggered, a first end of the switch being coupled to the output node, and a second end of the switch being coupled to a second reference voltage; wherein, when the switch is closed, the voltage across the capacitor is equal to the second reference voltage.

[0033] Optionally, the capacitance value of the capacitor is adjustable to offset any changes in the magnitude of gm.

[0034] Optionally, the transconductance amplifier includes a differential gain stage, the differential gain stage including:

[0035] a first transistor;

[0036] a second transistor;

[0037] a second resistor having a second resistance value;

[0038] a third resistor having a third resistance value; and

[0039] current source,

[0040] The control terminal of the first transistor is coupled to the first terminal of the first resistor, the control terminal of the first transistor forms the non-inverting input terminal of the transconductance amplifier, the current terminal of the first transistor is coupled to the first terminal of the second resistor, the second terminal of the second resistor is coupled to the first terminal of the current source, and the second terminal of the current source is coupled to the constant reference potential;

[0041] wherein the control terminal of the second transistor is coupled to the second terminal of the first resistor, the control terminal of the second transistor forms the inverting input terminal of the transconductance amplifier, the current terminal of the second transistor is coupled to the first terminal of the third resistor, and the second terminal of the third resistor is coupled to the connection point between the second terminal of the second resistor and the first terminal of the current source;

[0042] Wherein, the second resistance value is equal to the third resistance value;

[0043] The second resistor and the third resistor are matched with the first resistor.

[0044] Optionally, the current measurement module further includes:

[0045] a calibration module operable to correct an offset error of the transconductance amplifier; and

[0046] a first switch coupled between the second end of the first resistor and the calibration module, the first switch being operable to close when the main-level signal is in a first logic state and to open when the main-level signal is in a second logic state;

[0047] The calibration module is coupled between the first switch and the inverting input terminal of the transconductance amplifier.

[0048] The first end of the first resistor is coupled to the non-inverting input end of the transconductance amplifier.

[0049] According to another aspect of the present application, a phase controller for a multiphase switching converter is provided. The multiphase switching converter provides a regulated power supply voltage based on an input voltage under light load conditions. The phase controller provides a phase control signal to a power stage of the multiphase switching converter. The power stage is configured to connect the input voltage to an inductor when the phase control signal is in a first state, and disconnect the input voltage from the inductor when the corresponding phase control signal is in a second state. The load current of the multiphase switching converter is formed by an inductor current, and the phase controller includes:

[0050] Current sense pin,

[0051] a main control signal generator module coupled to receive the regulated supply voltage, the first reference voltage of the desired magnitude, and the on-time duration, and to generate a common control signal having corresponding characteristics,

[0052] a phase distributor coupled to receive the common control signal and generate the phase control signal based on a transition of the common control signal; and

[0053] a current measurement module coupled to receive a current signal from the power stage through a current sense pin, the current signal representing an inductor current in the power stage in analog continuous form, wherein the current measurement module comprises:

[0054] an integrator module coupled to receive the current signal and provide the voltage output; and

[0055] A processing module is coupled to receive the voltage output and determines a magnitude of the load current based on the voltage output.

[0056] Optionally, the current measurement module includes a first resistor coupled between the current sensing pin and the integrator module,

[0057] Wherein, the integrator block includes:

[0058] a transconductance amplifier characterized by a transconductance value (gm), the transconductance amplifier coupled to receive a voltage drop across the first resistor as a differential input and to generate an output current from an output node proportional to a magnitude of the voltage drop caused by the current signal flowing through the first resistor; and

[0059] a capacitor having a first end and a second end, wherein the first end of the capacitor is coupled to the output node and the second end of the capacitor is coupled to a constant reference potential, the capacitor being characterized by a capacitance value, the capacitor being coupled to receive the output current of the transconductance amplifier and to provide the voltage output at the first end;

[0060] Wherein, the processing block includes:

[0061] a comparator, configured to compare a voltage at a first terminal of the capacitor with a threshold voltage, wherein when the voltage at the first terminal is lower than the threshold voltage, the comparator triggers a reset signal;

[0062] a counter coupled to receive the reset signal and to generate a count of the number of times the reset signal is triggered within a sampling window; and

[0063] a mapping module coupled to receive the count and map the count to a corresponding magnitude of the on-time;

[0064] wherein the threshold voltage is proportional to a predetermined amount of change in the amount of charge in the capacitor,

[0065] The duration of the sampling window is selected to be greater than the time required for the voltage at the first end of the capacitor to change by the threshold voltage.

[0066] Optionally, the current signal is proportional to the inductor current, and the inductor current is scaled by a scaling factor to obtain the current signal.

[0067] Optionally, the mapping module comprises a lookup table comprising a plurality of entries to perform the mapping, wherein each entry of the plurality of entries comprises a range of the count and a corresponding magnitude of the on-time.

[0068] Optionally, the integrator module further includes a switch coupled across the capacitor, the switch being operable to close when the reset signal is triggered, a first end of the switch being coupled to the output node, and a second end of the switch being coupled to a second reference voltage; wherein, when the switch is closed, the voltage across the capacitor is equal to the second reference voltage.

[0069] Optionally, the capacitance value of the capacitor is adjustable to offset any changes in the magnitude of gm.

[0070] Optionally, the transconductance amplifier includes a differential gain stage, the differential gain stage including:

[0071] a first transistor;

[0072] a second transistor;

[0073] a second resistor having a second resistance value;

[0074] a third resistor having a third resistance value; and

[0075] current source,

[0076] The control terminal of the first transistor is coupled to the first terminal of the first resistor, the control terminal of the first transistor forms the non-inverting input terminal of the transconductance amplifier, the current terminal of the first transistor is coupled to the first terminal of the second resistor, the second terminal of the second resistor is coupled to the first terminal of the current source, and the second terminal of the current source is coupled to the constant reference potential;

[0077] wherein the control terminal of the second transistor is coupled to the second terminal of the first resistor, the control terminal of the second transistor forms the inverting input terminal of the transconductance amplifier, the current terminal of the second transistor is coupled to the first terminal of the third resistor, and the second terminal of the third resistor is coupled to the connection point between the second terminal of the second resistor and the first terminal of the current source;

[0078] Wherein, the second resistance value is equal to the third resistance value;

[0079] The second resistor and the third resistor are matched with the first resistor.

[0080] Optionally, the current measurement module further includes:

[0081] a calibration module operable to correct an offset error of the transconductance amplifier; and

[0082] a first switch coupled between the second end of the first resistor and the calibration module, the first switch being operable to close when the main-level signal is in a first logic state and to open when the main-level signal is in a second logic state;

[0083] The calibration module is coupled between the first switch and the inverting input terminal of the transconductance amplifier.

[0084] The first end of the first resistor is coupled to the non-inverting input end of the transconductance amplifier.

[0085] According to another aspect of the present application, a method for a phase controller of a multiphase switching converter is provided, wherein the multiphase switching converter provides a regulated power supply voltage based on an input voltage under a light load condition, the method comprising:

[0086] Receiving a current signal in an analog continuous form representing an inductor current in a power stage of the multiphase switching converter, wherein a load current of the multiphase switching converter is formed by the inductor current; integrating the current signal to generate a voltage output corresponding to the magnitude of the current signal; and determining the magnitude of the load current based on the voltage output. BRIEF DESCRIPTION OF THE DRAWINGS

[0087] Exemplary embodiments of the present application will be briefly described below with reference to the accompanying drawings.

[0088] Figure 1 is a block diagram of an example system employed in several aspects of the present application.

[0089] Figure 2 Detailed description of a voltage regulator module (VRM) in an embodiment of the present application.

[0090] Figure 3A It is a schematic diagram used to illustrate the implementation details of the power stage in the embodiment of the present application.

[0091] Figure 3B This is a flow chart used to illustrate a load current measurement method in a phase controller in an embodiment of the present application.

[0092] Figure 4A It is a schematic diagram used to illustrate the implementation details of the phase controller in the embodiment of the present application.

[0093] Figure 4B It is a schematic diagram used to illustrate the implementation details of the current measurement module in the embodiment of the present application.

[0094] Figure 5 This is a timing diagram used to illustrate a method of measuring load current based on a current signal received from a power stage in an embodiment of the present application.

[0095] Figure 6 is a schematic diagram for illustrating implementation details of the differential gain stage of a transconductance amplifier in an embodiment of the present application.

[0096] In the drawings, like reference numerals generally indicate identical, functionally similar, and / or structurally similar elements. The drawing in which an element first appears is indicated by the leftmost digit in the corresponding reference numeral. DETAILED DESCRIPTION

[0097] 1. Overview

[0098] Aspects of the present application provide a multiphase switching converter comprising a power stage and a phase controller, and providing a regulated power supply voltage based on an input voltage. The power stage receives a phase control signal and drives an inductor according to the phase control signal to generate an inductor current, wherein the load current of the multiphase switching converter is formed by the inductor current. The phase controller receives a current signal from the power stage from a pin, the current signal representing the inductor current in the power stage in an analog continuous form. The phase controller integrates the current signal in the analog continuous form to generate a voltage output representing the magnitude of the load current, and determines the magnitude of the load current based on the voltage output.

[0099] It will be appreciated that accurately determining the load current allows for accurate determination of the characteristics of the phase control signal (eg, on-time) to achieve maximum efficiency.

[0100] According to another aspect of the present application, a main control signal generator module of a phase controller receives a regulated power supply voltage, a reference voltage of a desired magnitude, and an on-time magnitude, and generates a common control signal with corresponding characteristics. A phase distributor of the phase controller receives the common control signal and generates a phase control signal based on the transition timing of the common control signal. A current measurement module of the phase controller receives the current signal and determines the magnitude of the load current.

[0101] According to another aspect of the present application, the current measurement module includes an integrator module, which receives a current signal and provides a voltage output; and a processing module, which receives the voltage output, determines the on-time according to the size of the voltage output, and provides the on-time to the main control signal generator module.

[0102] In one embodiment, a current measurement module includes a first resistor connected between a pin and an integrator module. The integrator module includes a transconductance amplifier characterized by a transconductance value (gm). The transconductance amplifier receives a voltage drop across the first resistor as a differential input and generates an output current proportional to the voltage drop caused by the current signal flowing through the first resistor. The integrator module includes a capacitor having a first terminal and a second terminal, the capacitor characterized by a capacitance value. The capacitor receives the output current of the transconductance amplifier and provides a voltage output at the first terminal, wherein the second terminal of the capacitor is connected to a reference voltage. A processing module of the current measurement module includes a comparator for comparing the voltage at the first terminal of the capacitor with a threshold voltage. When the voltage at the first terminal is lower than the threshold voltage, the comparator issues a reset signal, and when the reset signal is issued, the capacitor discharges. A counter of the processing module receives the reset signal and counts the number of times the reset signal is triggered within a sampling window. A mapping module of the processing module receives the number of times and maps it to a corresponding on-time value.

[0103] According to one aspect of the present application, the threshold voltage is proportional to a predetermined amount of change in the charge in the capacitor, and the duration of the sampling window is set to be greater than the amount of time required for the voltage at the first terminal of the capacitor to change by the threshold voltage.

[0104] Several aspects of the present application will be described below in conjunction with examples. However, those skilled in the relevant art will appreciate that the present application can be implemented in the absence of one or more specific details or using other methods, components, materials, etc. In other cases, to avoid obscuring the features disclosed in the present application, well-known structures, materials, or operations are not shown in detail. In addition, the described features / aspects can be implemented in various combinations, but for the sake of brevity, only some of these combinations are described herein.

[0105] 2. Example System

[0106] Figure 1 1 is a block diagram of an example system used in several aspects of the present application. The system 100 shown in the figure includes a power supply 110, a central processing unit (CPU) 120, a memory 130, a network interface 140, and peripheral devices 150. In one embodiment, the system 100 corresponds to a computer (desktop, laptop, etc.), but in other embodiments, the system 100 can represent other types of systems. It should be understood that the system 100 can include more than Figure 1 More or fewer modules as shown.

[0107] CPU 120, generally representing a processor or system-on-chip (SoC), is shown receiving a pair of supply voltages (Va and Vb) from power supply 110 via respective paths 112A and 112B. For example, Va may be less than Vb and may be used to power the core portion of the CPU, which may include the arithmetic logic unit (ALU), microprogram sequencer, registers, etc. Vb may be used to power the remainder of CPU 120, such as input / output (I / O) units, I / O buffers, on-chip peripherals, etc. CPU 120 provides various signals to power supply 110 (all of which are considered to be included in bidirectional path / bus 121) that, among other things, specify its power requirements. Examples of such signals may include signals specifying a particular operating mode (in terms of power consumption), such as PS1, PS2, PS3, etc., which refer to "power-saving states for improved efficiency." CPU 120 receives power stage health information from phase controller 210 via bidirectional path / bus 121.

[0108] Memory 130 represents internal memory, which may include both volatile and nonvolatile memory. For example, in a personal computer, memory may include magnetic storage (hard disk) and solid-state storage (RAM, flash memory, etc.). As shown in the figure, memory 130 receives a power supply voltage via path 113 to power various circuits and modules within it.

[0109] The network interface 140 is used to provide two-way communication between the system 100 and a computer network (typically the Internet). The network interface 140 implements the electronic circuitry required to communicate using a specific physical layer and data link layer standard (e.g., Ethernet or Wi-Fi™). The network interface 140 may also include a network protocol stack to communicate with other computers on the same local area network (LAN) and to facilitate large-scale network communication using routable protocols such as the Internet Protocol (IP). The network interface 140 receives a power supply voltage via path 114 to power the internal circuits and modules. The network interface 140 receives and sends data from the external system and the CPU 120 via paths 141 and 124, respectively.

[0110] Peripheral device 150 represents one or more peripheral circuits, such as a speaker, a microphone, a user interface device, etc. Peripheral device 150 receives a power supply voltage from path 115 and communicates with external devices on path 151 .

[0111] Power supply 110 receives power from one or more power sources (e.g., batteries) via path 101 and provides the required power supply voltages via paths 112A, 112B, 113, 114, and 115. In one embodiment, power supply 110 is configured to include one or more multi-phase DC-DC converters for generating the power supply voltages. Power supply 110 receives signals from CPU 120 via path 121. These signals may indicate the power mode in which CPU 120 should operate during a specific time period. These power modes indicate the amount of power from power supply 110 required / consumed by CPU 120. Power supply 110 responds to these signals by controlling the multi-phase converters to reduce / increase current output according to specific power mode signals (e.g., PS1, PS2, and PS3).

[0112] In one embodiment, power supply 110 is a voltage regulator module (VRM), sometimes also referred to as a processor power module (PPM), which includes one or more step-down switching (buck) converters for generating one or more smaller voltages from a high-voltage power supply. However, in other embodiments, other types of DC-DC converters, such as boost converters, buck-boost converters, hysteretic converters, etc., may be used in place of a buck converter. Furthermore, power supply 110 may be implemented as a standalone switching converter with only one power stage (thus, not a multi-phase converter). Using a VRM, multiple devices / ICs requiring different supply voltages can be mounted on the same platform, such as the motherboard of a personal computer (PC).

[0113] The following describes the internal details of the VRM, such as Figure 2 shown.

[0114] 3. Voltage Regulator Module (VRM)

[0115] Figure 2 1 is a block diagram showing details of a voltage regulator module (VRM) in an embodiment of the present application. Figure 1 ) is a voltage regulation module implemented in the form of a multi-phase switching converter, generating two regulated power supplies (rails) Va (240) and Vb (250), which includes a phase controller 210, smart power stages (power stages) (SPS) SPSA-1 (220-1) to SPSA-6 (220-6), SPSB-1 (230-1) to SPSB-3 (230-3), inductors 225A-1 to 225A-6, 227B-1 to 227B-3, and output capacitors 226A-1 to 226A-6, 228B-1 to 228B-3. Node 299 represents ground (0 volts).

[0116] In this embodiment, the power supply Va (240) is generated by a six-phase buck converter (a total of six SPSs, 220-1 to 220-6), and the power supply Vb (250) is generated by a three-phase buck converter (a total of three SPSs, 230-1 to 230-3). Nodes / paths 240 and 250 correspond to Figure 1 Paths 112A and 112B in FIG. For simplicity, Figure 2 Other power supply circuits that generate power on paths 113, 114, and 115 are not shown.

[0117] The power stages 220-1 to 220-6 and 230-1 to 230-3 may be collectively referred to as the corresponding reference numerals 220 and 230 hereinafter, as will be apparent from the context. Furthermore, the signals / nodes 211-1 to 211-6, 213-1 to 213-6, 215-1 to 215-6, 216-1 to 216-3, and 218-1 to 218-3 may also be collectively referred to as the corresponding reference numerals 211, 213, 215, 216, and 218 hereinafter, as will be apparent from the context. Similar rules may be followed for other modules / components / signals in this application.

[0118] In the embodiment of the present application, each power stage and phase controller are implemented as separate integrated circuits (ICs). However, in other embodiments, the implementation of the power stage and phase controller may be different.

[0119] The combination of phase controller 210, power stage, inductor, and capacitor (and their corresponding circuitry) constitutes a "phase" of a multi-phase switching converter. Thus, for example, SPSA-1, inductor 225A-1, capacitor 226A-1, and their corresponding components within phase controller 210 represent one phase of a six-phase buck converter.

[0120] Each power stage can be implemented as a high-side switch, a low-side switch, a gate drive circuit for the two switches, and other circuits. Examples of other circuits include, but are not limited to, a temperature monitoring circuit, an inductor current detection (or simulation) circuit, etc., which are used to provide information such as the temperature of the SPS / power stage, the magnitude of the inductor current, etc. to the phase controller 210. Each SPS receives a power supply as an input, which is connected to the high-side switch. Figure 2 In FIG, the power supply is labeled 201 and has a voltage of Vin. In one embodiment, Vin has a value of 12 volts (V). Each SPS also receives a voltage Vcc via path 202. In one embodiment, Vcc has a voltage of 3.3 V and is provided by phase controller 210.

[0121] Each SPS communicates with the phase controller 210 via corresponding signals PWM, SYNC, CS, and TEMP. Thus, in the figure, SPSA-1 is connected to the phase controller 210 via signals / paths PWMA-1 (211), SYNC-A (212), CSA-1 (213), and TEMPA (214). Although Figure 2The corresponding connections of signals PWMA-6, SYNC-A and CSA-6 to phase controller 210 are not shown in FIG. SPSA-6 communicates with phase controller 210 via signals PWMA-6, SYNC-A, CSA-6 and TEMPA (214). Similarly, SPSB-1 is connected to phase controller 210 via signals / paths PWMB-1 (216), SYNC-B (217), CSB-1 (218) and TEMPB (219). Although Figure 2 The corresponding connections of PWMB-3, SYNC-A, and CSB-3 to the phase controller 210 are not shown. SPSB-3 communicates with the phase controller 210 via signals PWMB-3, SYNC-B, CSB-3, and TEMPB (219). The other SPSs are connected to the phase controller 210 in a similar manner. In other embodiments, the number of such signals may be greater or lesser, depending on the requirements of the specific operating environment.

[0122] The TEMP signal is an output from the SPS to phase controller 210, providing information about the SPS temperature. Phase controller 210 processes the TEMP signal (or the information contained therein) to adjust the supply current for that phase or shut down the VRM. The TEMP outputs of each converter phase are connected together and fed into a single input to phase controller 210.

[0123] The CS (current sense) signal is an input from the SPS / phase to the phase controller 210 and contains information about the instantaneous magnitude of the inductor current in that phase. This information can be in the form of current, voltage, or a digital value, depending on the specific implementation of the power stage and phase controller 210. The CS module in the SPS performs current sensing and sends the CS signal to the phase controller 210.

[0124] In an embodiment of the present application, the current sensing module of the power stage sends the detected inductor current information to the phase controller 210 in the form of a current. This current can be the same magnitude as the inductor current, or (more typically) a scaled-down version (in terms of magnitude) of the inductor current. Accordingly, in this embodiment, the phase controller 210 is designed to receive information in the form of a current, and when scaling is used, the scaling factor is known to both the phase controller 210 and the (corresponding) power stage.

[0125] The PWM signal is the input to the SPS from phase controller 210 and can be considered a "phase control signal," controlling the operation (on and off states) of the power switches in the corresponding phase SPS. A PWM signal cycle consists of a first interval (on-time), during which only the high-side (HS) switch of the SPS is on, and a second interval, during which only the low-side (LS) switch of the SPS is on. The PWM signal (or, more generally, a drive signal derived from the PWM signal) controls the on and off states of the SPS high-side and low-side switches.

[0126] In an embodiment of the present application, phase controller 210 employs a constant on-time control technique to generate Va. Therefore, in this embodiment, a PWM signal is a variable-frequency, fixed-pulse-width (constant on-time) signal (i.e., a pulse-frequency modulated signal). For ease of reference, the abbreviation PWM is still used herein to refer to this type of signal. The frequency of this signal is typically proportional to the desired regulated voltage (Va) and the load current.

[0127] In an alternative embodiment, phase controller 210 can dynamically adjust the on-time based on the input voltage (Vin), Va, and load current, so that the switching frequency remains constant over the input voltage range. This control technique is known as adaptive on-time control and is well known in the art. However, the PWM signal may have other characteristics, depending on the specific implementation details of power supply 110.

[0128] In yet another embodiment, the PWM signal may vary between a constant on-time variable frequency signal and a fixed frequency pulse width modulated signal based on load current requirements, desired efficiency of the power supply 110 , and other considerations, as will be apparent to those skilled in the relevant art(s).

[0129] As is well known in the related art, the PWM signals for each SPS in a multiphase voltage regulator are interleaved / alternated, meaning they are delayed in phase with each other. This prevents two high-side switches (i.e., corresponding SPSs) in the converter from turning on at the same time. This technique is used for reasons such as ensuring that the peak instantaneous current drawn from Vin remains relatively low, improving efficiency, and reducing output voltage ripple.

[0130] When the SPS detects a logic low on the PWM signal, the low-side switch turns on; when it detects a logic high on the PWM signal, the high-side switch turns on. When the SPS detects a high-impedance (hi-Z) state on the PWM signal (typically midway between the power supply and ground), it turns off both its high-side and low-side switches. Therefore, the SPS is considered "active" when the corresponding PWM signal switches between high and low, generating an output voltage and current; it is considered "inactive" when the corresponding PWM signal is in a high-impedance state (midway between logic high and logic low). In the inactive state, the power stage has no effect on the load current.

[0131] The phase controller 210 controls the operation of the power stage through the above-mentioned signals to provide various functions, including the regulation function of enabling the corresponding power stage group to generate regulated voltages Va and Vb. Therefore, Va and Vb are shown as inputs to the phase controller 210 so that one or more feedback loops within the phase controller 210 can regulate Va and Vb. The phase controller 210 also receives inductor current information (the current flowing through each inductor) from each SPS to implement various operations, such as voltage regulation, current limiting, short-circuit protection for current mode control, and balancing the current generated by each SPS on the same power rail (e.g., power rail Va) so that the current generated by each SPS is substantially equal. The phase controller 210 can also perform various other operations, which are not described here for the sake of brevity.

[0132] Phase controller 210 is also used to control the power level, reducing / increasing the current output based on load demand. Furthermore, phase controller 210 may receive a signal from CPU 120 indicating the desired power level at which the CPU should operate (e.g., PS1, PS2, etc., as mentioned above). In response, phase controller 210 may enable / disable one or more power stages 220 based on the power level and load current.

[0133] Phase controller 210 can be designed to implement automatic phase management (APM). Therefore, the specific number of phases activated by phase controller 210 can vary depending on, for example, the magnitude of the load current drawn from a power rail (e.g., Va 240). Generally, the lower the load current, the fewer phases are active, and vice versa. For example, phase controller 210 can store (in internal memory) predetermined load current thresholds to determine the number of active phases. The thresholds are set to ensure that a given load current demand is met by substantially equal phase output currents, taking into account the maximum current each phase can provide.

[0134] For example, for a medium load current drawn from the power rail Va (240), the phase controller 210 may activate three power stages to generate Va (240) and maintain the other three power stages in an "inactive" mode. When the load current increases from a previous value and exceeds a predetermined threshold, the phase controller 210 may activate all six power stages assigned to the power rail Va (240). However, when the load current decreases from a previous value and falls below another predetermined threshold, the phase controller 210 may deactivate (reduce or cut off) two of the three previously active power stages, maintaining only one power stage in an active state while maintaining the other five power stages in an inactive mode.

[0135] As is well known in the art, switching converters operate in one of two modes: continuous conduction mode (CCM) and discontinuous conduction mode (DCM). CCM refers to a mode in which the inductor current flows continuously throughout the switching cycle. In CCM mode, the inductor current can be negative. In CCM mode, the switching converter typically operates at a fixed frequency and a variable duty cycle.

[0136] DCM refers to a mode in which the inductor current drops to zero during a certain portion of the switching cycle. In DCM mode, the inductor current is not allowed to go negative. When the inductor current reaches zero, the low-side switch turns off. This prevents the inductor current (negative current) from flowing in the opposite direction, which would otherwise draw current from the load. Therefore, the inductor current remains at zero until the high-side switch turns on in the next PWM cycle. To achieve the desired load current, the switching frequency is varied in DCM mode.

[0137] Typically, the phase controller 210 controls the power stage in CCM mode under high load conditions and controls the power stage in DCM mode under light load conditions. "Light load" as referred to in this application refers to a situation where the load at the output end is only a small portion (for example, less than 10%) of the maximum rated power. When the phase controller 210 operates in DCM mode, only a small number of power stages are maintained in an active state. In one embodiment, the phase controller 210 controls one power stage in an active state in DCM mode. It is well known in the relevant art that the phase controller 210 controls the power stage in DCM mode to improve efficiency.

[0138] The phase controller can operate one of the power stages as the "master" during a given time period, meaning that this power stage is always included in the set of active power stages, even if stages are added and / or deleted during the given time period. Thus, the master stage remains active throughout the (given) time period, regardless of the load current. The phase controller 210 periodically changes the master stage based on a technique such as a round-robin sequence to evenly distribute pressure across the power stages. Thus, even in DCM mode, a single active power stage cycles over time (e.g., from SPS-1 to SPS-2, etc.) for pressure balancing.

[0139] The following description continues to illustrate an embodiment of a power stage according to one aspect of the present application.

[0140] 4. Power level

[0141] Figure 3A is a block diagram used to illustrate the implementation details of the power stage in an embodiment of the present application. FIG3 shows the SPSA-1 (220-1) in detail. Other SPSs can also be implemented similarly to the SPSA-1. The SPSA-1 includes a gate driver 310, a high-side (HS) switch 320, a low-side (LS) switch 330, and a current sensing module 350. FIG3 also shows an inductor 225A-1 and an output capacitor 226A-1. When the power stage 220 is implemented as an integrated circuit (IC), P31 to P35 represent pins PWM, Vcc, Vin, SW, and CS. In an alternative implementation (such as a discrete form), P31 to P35 represent corresponding circuit nodes. Vcc (202) is used to power the internal modules of the power stage 220-1. The drain terminal of the HS switch 320 is connected to Vin (201), and the source terminal of the LS switch 330 is connected to ground (299). Although for the sake of simplicity Figure 3A Not shown, the power stage 220 may include various other modules / circuits, such as a level shifter for the gate driver 310 , a temperature sensor, etc.

[0142] Gate driver 310 receives PWM signal PWMA-1 (211-1) (from phase controller 210) and generates appropriate voltages in response to the logic level of the PWM signal, turning HS switch 320 and LS switch 330 on and off at corresponding time intervals, as indicated by the logic level of the PWM signal. HS switch 320 and LS switch 330 are shown as N-channel MOSFETs (metal oxide semiconductor field effect transistors), with gate driver 310 driving the gate terminals of the MOSFETs. However, other switch implementations with similar characteristics may also benefit from the features described herein.

[0143] exist Figure 3AIn the example shown in FIG1 , when PWMA-1 is at a logic high level, gate driver 310 generates appropriate voltages on paths 312 (en-HS) and 313 (en-LS), respectively, to turn on MOSFET 320 and turn off MOSFET 330. When PWMA-1 is at a logic low level, gate driver 310 generates appropriate voltages on paths 312 and 313, respectively, to turn off MOSFET 320 and turn on MOSFET 330. When PWMA-1 is in a Hi-Z (high impedance or mid-rail) state, gate driver 310 generates appropriate voltages on paths 312 and 313, respectively, to turn off MOSFET 320 and 330. It should be noted that, in addition to a single module, two separate gate drivers can be used, one for driving the gate of the HS switch on or off, and the other for driving the gate of the LS switch on or off. Gate driver 310 can be implemented in a known manner.

[0144] In each cycle of the PWM signal, when the HS switch 320 is turned on, current flows from Vin through the HS switch 320 and the inductor 225A-1 connected to the SPSA-1 (220-1) to the load (connected to the Va node) at an increasing slope. When the LS switch 330 is turned on, the inductor current flows through the loop formed by the LS switch 330, the inductor 225A-1, and the load at a decreasing slope. As described above, in the DCM mode, when the inductor current becomes zero, the LS switch 330 is turned off, and the inductor current remains zero until the HS switch 320 is turned on in the next PWM cycle. Therefore, the waveform IL (290-1) and the current signal CSA-1 (213-1) are triangular, as shown in FIG. Figure 5 shown.

[0145] The current sensing module 350 is used to determine the magnitude (e.g., instantaneous magnitude) of the inductor current flowing through the inductor 225A-1 and provide information indicating the magnitude of the inductor current on the path 213. The current sensing module 350 can determine the magnitude of the inductor current by one of a variety of known methods. For example, Figure 3A , the current sensing module 350 is shown as receiving the voltage drop across switches 320 and 330. The current sensing module 350 obtains the instantaneous magnitude of the inductor current (or a reduced version thereof) based on the voltage drop.

[0146] In one embodiment, current sensing module 350 provides / reports inductor current information in the form of an analog continuous current signal, whose magnitude is scaled relative to the instantaneous inductor current. The term "analog" indicates that the instantaneous current magnitude is a non-discrete level, and the term "continuous" indicates that the current magnitude is represented as an instantaneous value at a continuous time. In other words, the current signal is scaled relative to the actual real-time inductor current waveform. Current sensing module 350 can be implemented using known methods.

[0147] Phase controller 210 uses the current signal (representing the inductor current) to operate one or more regulation feedback loops, thereby operating the power switches (320 and 330) in the power stage to generate the desired regulated voltage Va as output 240. As described above, the operation of the power switches in the power stage is controlled by the PWMA signal. Phase controller 210 generates PWMA-1 with an appropriate pulse width and / or frequency to generate Va while achieving the highest possible efficiency. Efficiency is the ratio of the output power of the power supply to the input power received from the power supply Vin.

[0148] As is well known in the relevant art, various loss factors, such as switching loss (associated with the turn-on / off of the power switch), conduction loss (the voltage drop across the power switch), and dead-time loss (caused by current flowing through the body diode of the LS switch during the dead-time interval), all affect the overall efficiency of a switching converter. Among these factors, some, such as switching loss, are related to the switching frequency.

[0149] Generally speaking, lower switching frequencies reduce switching losses in power switches. However, because a sufficiently high switching frequency is required to supply the load current, the switching frequency cannot be arbitrarily reduced. Higher load currents require higher switching frequencies. Therefore, accurately determining the load current allows for the correct switching frequency to achieve the highest efficiency.

[0150] The VRM 100 is generally suitable for a wide load current range (approximately 0-1600 amperes (A)). Therefore, conventional current measurement techniques in the phase controller 210 are generally designed to cover a wide range, resulting in lower accuracy.

[0151] In DCM mode, the load current range (approximately 0-5A) is many times smaller than the total rated range, and the load current needs to be measured as accurately as possible to achieve high efficiency. Therefore, the traditional measurement technology used in phase controller 210 is not suitable for measuring the required accuracy of load current in DCM mode.

[0152] Therefore, a technology capable of measuring load current under light load conditions is needed. The phase controller 210 implemented according to several aspects of the present application provides a function of measuring load current under light load conditions, as described below in conjunction with embodiments.

[0153] 5. Flowchart

[0154] Figure 3B This is a flow chart for illustrating a method for measuring load current under light load in a phase controller of a multi-phase switching converter in an embodiment of the present application. Figure 1 and Figure 2The system / multi-phase switching converter in the present invention is described for reference only. However, many features may also be implemented in other systems and / or other environments without departing from the scope and spirit of several aspects of the present application, as will be understood by those skilled in the relevant art after reading the disclosure provided herein.

[0155] In addition, some or all of the steps may be performed in a different order than described below to suit specific circumstances, as will be apparent to those skilled in the relevant art. Several aspects of this application encompass many such implementations. The flowchart begins at step 351, and control immediately passes to step 360.

[0156] In step 360, the phase controller 210 receives a current signal in analog continuous form, which represents the inductor current in the power stage. The power stage corresponds to a single active power stage, wherein the multiphase switching converter 110 operates in DCM mode. Therefore, the load current of the multiphase switching converter 110 is formed by the inductor current of the active power stage. The current signal corresponds to Figure 2 Signal 213 in.

[0157] In step 370, the phase controller 210 integrates the current signal to generate a voltage output representing the load current. It should be understood that time integration of the current signal can obtain a corresponding amount of charge, which, when stored in a capacitor, generates a corresponding voltage output.

[0158] As is well known in the related art, the inductor current waveform is typically triangular, and the load current is the average value of the inductor current. Since the current signal represents the actual inductor current, integrating the current signal can be used to estimate the corresponding load current. Specifically, integrating a higher load current results in a higher charge, which in turn leads to a higher voltage output. Therefore, the voltage output represents the magnitude of the load current.

[0159] In step 380, phase controller 210 determines the magnitude of the load current based on the voltage output generated in step 370. Phase controller 210 then uses this load current magnitude to drive the power stage. For example, phase controller 210 varies the on-time of PWMA-1 based on the magnitude of the load current. Accurately determining the load current ensures accurate determination of the correct on-time for maximum efficiency. This change in on-time may, in turn, result in a corresponding change in the switching frequency, depending on, for example, the design of the control loop within phase controller 210.

[0160] Therefore, the phase controller of the present application can measure the load current under light load. The implementation details of the phase controller performing such measurement in the embodiment of the present application will be provided below.

[0161] 6. Phase controller

[0162] Figure 4A 4 is a block diagram illustrating implementation details of the phase controller in an embodiment of the present application. The phase controller 210 includes an error amplifier 410, a mode module 415, a PWM generator 420, a phase distributor 430, a phase manager 440, and a current measurement module 450. For the sake of clarity, Figure 4A Also shown are power stages 220-1 to 220-6 and their corresponding inductors and capacitors. Figure 4A Only the six-phase converter including power stages SPSA-1 (220-1) to SPSA-6 (220-6) that collectively generate voltage Va (240) and the corresponding parts of phase controller 210 required to generate voltage Va (240) are shown. When phase controller 210 is implemented as an integrated circuit (IC), P41 to P46 represent pins CS of the six SPSs, SPS-1 to SPS-6, respectively. In alternative embodiments (e.g., discrete form), P41 to P46 represent corresponding circuit nodes.

[0163] Also note that Figure 4A Only the elements relevant to understanding the content of this application are depicted. It is understood that the phase controller 210 may include Figure 4A . Furthermore, for ease of illustration, the phase controller 210 is described and illustrated herein using only current mode control techniques. However, it should be understood that the phase controller 210 may employ other types of control techniques. The internal modules of the phase controller 210 may be powered by a power supply not shown.

[0164] Mode module 415 receives a signal from CPU 120 via path 121, determines the desired power level based on signal 121, and generates a "mode" signal on path 416, indicating whether the SPS should operate in CCM or DCM. In one embodiment, if signal 121 determines power levels PS2 and PS3 (low power level), mode module 415 generates a logic high on path 416; otherwise, it generates a logic low. In another embodiment, mode module 415 may receive load current information (on a corresponding path) and determine whether the multiphase switching converter 110 should operate in CCM or DCM based on the load current. In this embodiment, mode module 415 generates a logic high on path 416 if the load current is less than a predetermined threshold; otherwise, it generates a logic low. This threshold may be pre-programmed into the non-volatile memory of phase controller 210 or received as user input via a corresponding device (not shown). Mode module 415 may be implemented in a known manner.

[0165] Vref represents the desired target voltage provided at node Va (240). Thus, Vref represents a stable reference DC voltage, which is generated internally by the phase controller 210 in a known manner. The error amplifier 410 receives the reference voltage Vref (401), the output voltage, and Va (240) (or a fraction of Va obtained using a voltage divider network) and generates a voltage Vc (411) representing the voltage difference between Vref (401) and Va (240), which constitutes the input of the PWM generator 420. The error amplifier 410 can be implemented in a known manner. The current measurement module 350 processes the inductor current flowing through the active power stage inductor in DCM mode to generate a T-ON duration on path 453, which constitutes another input of the PWM generator 420.

[0166] PWM generates a signal PWM-CLK (427) based on the Vc signal and the current-load value. PWM-CLK (427) can be a series of pulses (such as a fixed pulse width), and its frequency can be changed according to the changes of Vin, Vout and load current.

[0167] The signal PWM-CLK (427) is typically a short pulse of fixed duration and is used to clock components (such as flip-flops) within the phase divider 430. Modules 410 and 420 can be considered together as a "master signal generator" that generates a "common control signal" PWM-CLK (427) to maintain the voltage Va (240) at a desired constant level, namely Vref (401). The PWM generator 420 includes the components required to generate the signal PWM-CLK (427). Figure 4A The PWM generator 420 may be implemented in a known manner, for example, a sawtooth wave generator, a comparator, etc.

[0168] The phase manager 440 receives inputs on path 422 representing load current requirements, the sensed inductor currents of each power stage, overshoot / undershoot of the voltage Va (240), etc., and generates a distributed phase signal on path 442, an effective phase signal on path 443, and a main phase signal on path 447. The phase manager 440 controls the increase or decrease of the phase (and thus the power stage) according to the load current requirements.

[0169] In one embodiment, the assigned phase signal (442), the effective phase signal (443), and the master phase signal (447) each occupy n bytes, where "n" represents the total number of phases of the multi-phase switching converter 110. Therefore, each byte of the assigned phase signal, the effective phase signal, and the master phase signal corresponds to a power level. The "assigned phase" signal indicates the phases assigned to a particular rail, and a single "effective phase" signal indicates a specific phase assigned to that rail. These phases are activated for a given duration to support the load current demand of the power rail. The "master phase" signal indicates the power level that operates as the master level for that duration. Phase manager 440 can be implemented in a known manner.

[0170] Phase distributor 430 (PD 430) receives PWM-CLK signal (427) and effective phase signal (443), and generates PWM signals (211-1 to 211-6) according to the timing of the change of PWM-CLK signal. PD 430 may include a T-ON generator ( Figure 4A (not shown), a constant on-time control technique is employed. Therefore, in an exemplary embodiment, PD 430 generates a PWM signal (211) having a predetermined (constant) on-time (logic high level duration), but its frequency can be varied as described above. Several aspects of the present application are also applicable to the above-described adaptive on-time technique, which will be apparent to a person skilled in the art who has read the disclosure herein. PD 430 can be implemented in a known manner. Current measurement module 450 receives sensed inductor current information (current signal on path 213), a distribution phase signal on path 442, and a main phase signal on path 447 from the SPSs, i.e., SPS-1 to SPS-6, and generates a T-ON duration on path 453.

[0171] The following description continues to illustrate an example implementation of a current measurement module for measuring load current in an embodiment of the present application.

[0172] 7. Current measurement module

[0173] Figure 4B 4 is a schematic diagram for illustrating the implementation details of the current measurement module in an embodiment of the present application. The current measurement module 450 shown in the figure includes sensing resistors Rs1 to Rs6, switches 462-1 to 462-6, switches 464-1 to 464-6, a calibration module 465, a transconductance amplifier 470, a capacitor 475, a switch 474, a comparator 480, a counter 485 and a mapping module 490. P41 to P46 represent CS pins, respectively, for receiving signals from ( Figure 2(Sensing current information) of SPS-1 to SPS-6. In this embodiment, it is assumed that all six power stages (SPS-1 to SPS-6) are assigned to the A rail and that only SPS-1 is active in the DCM mode during the target duration. The internal modules of the current measurement module 450 can be powered by a power supply not shown. Only the components related to the load current measurement in the DCM mode are depicted in the figure. It should be understood that the current measurement module 450 may include a Figure 4B More or fewer modules as shown.

[0174] Each of the switches 462-1 to 462-6 can be closed or opened based on the logic state of each bit of the signal 442. In one embodiment, when the signal 442[x] is at a logic high level, the switch 462-X is closed, otherwise it is open. Each of the switches 464-1 to 464-6 can be closed or opened based on the logic state of each bit of the signal 447. In one embodiment, when the signal 447[x] is at a logic high level, the switch 464-X is closed, otherwise it is open. Although Figure 4B Although not shown, each of switches 462-1 to 462-6 and 464-1 to 464-6 is closed or open based on the logic state of signal 416 (mode). Specifically, the switch is closed only when both signal 416 and the corresponding bit corresponding to the switch (in signal 442 or 447) are at a logic high level.

[0175] Calibration module 465 is used to correct offset error and gain error in transconductance amplifier 470. Offset error refers to the non-zero output current resulting from equal voltages V1 and V2 and / or unequal bias currents of the input transistors within amplifier 470. Calibration module 465 is a voltage source connected to the inverting input path of amplifier 470. The voltage source is adjusted to eliminate offset error. Gain error is corrected by adjusting the capacitance of capacitor 475 in an appropriate manner. Calibration module 465 can be implemented using known methods.

[0176] The transconductance amplifier 470 receives the voltage drop (differential voltage) across the resistor 463 - 1 at its input terminal and generates a current (Iout, 472 ) proportional to the voltage drop. Figure 6 An exemplary implementation of the amplifier 470 gain stage is described.

[0177] Switch 474 can be closed or opened based on the logic state of signal 483 (reset). In one embodiment, when signal 483 is triggered, switch 474 is closed, otherwise it is open. Switch 474 is connected between the top of capacitor 475 and a reference voltage (V-cm, 489).

[0178] When switch 474 is closed, capacitor 475 charges (to V-cm). As current Iout flows during each PWM cycle, capacitor 475 discharges, causing the voltage across the capacitor to change accordingly. Therefore, amplifier 470 and capacitor 475 can be considered an "integrator module" together. The bottom terminal of capacitor 475 is connected to ground (299).

[0179] In one embodiment, V-cm is equal to the mid-rail voltage (approximately 1.7V). Setting V-cm to the mid-rail voltage allows the integrator module to operate in the linear region. However, in alternative embodiments, V-cm can be set to a voltage other than the mid-rail voltage (e.g., ground potential, 0V), which will be apparent to those skilled in the art after reading the disclosure herein. It should be noted that, unless otherwise noted, all voltages mentioned in this specification are relative to ground potential (0V).

[0180] Comparator 480 receives a voltage (dVcap, 478) (the voltage at the top of capacitor 475) at its inverting input and a threshold voltage vcomp-ref (477) at its non-inverting input. When the magnitude of dVcap is lower than the magnitude of the threshold voltage vcomp-ref, the comparator output jumps and signal 483 is triggered. The voltage vcomp-ref can be obtained from Vcc (202) in a known manner, such as using a voltage divider network. The method for determining the magnitude of vcomp-ref in the embodiments of the present application will be described in further detail below. Comparator 480 can be implemented in a known manner.

[0181] Counter 485 receives the "reset" signal on path 483 and the duration of the sampling window on path 484 and generates a terminal count on path 487. Counter 485 counts the number of times the "reset" signal is triggered within the sampling window of duration 484. Each time the "reset" signal is triggered, the counter value is incremented by one. Counter 485 includes a timer (not shown) whose time interval (tik) is synchronized with the end of the duration of the same value received on path 484. Counter 485 outputs the current count value via path 487 and resets the count value to zero at each time interval of the timer. The duration of the sampling window 484 can be programmed by the user in a known manner within phase controller 210. Counter 485 can be implemented in a known manner.

[0182] Mapping module 490 receives the "terminal count" signal on path 487 and generates the size of the T-ON duration on path 453. In one embodiment, mapping module 490 includes a lookup table (LUT) that maps the "terminal count" range to the corresponding T-ON duration. The LUT can be received through user input (via corresponding means not shown in the figure) or can be configured in a known manner during design.

[0183] In an alternative embodiment, the LUT may include a mapping module 490 for mapping the final count range to various values of control parameters other than T-ON (e.g., the peak value of the inductor current) based on the control scheme implemented in phase controller 210. In yet another alternative embodiment, mapping module 490 may not be included in circuit 450, and final count 487 may be provided on path 453, which may be used by PWM generator 420 or any other block in phase controller 210 for further processing.

[0184] Although the exemplary embodiment depicts mapping block 490 as part of current measurement module 450, mapping block 490 may also be implemented as part of PWM generator 420. In such an implementation, a "terminal count" value is provided on path 453, and PWM generator 420 may use a lookup table (LUT) to map the terminal count to a corresponding T-ON duration / peak inductor current and generate a signal 427 having corresponding characteristics. Mapping block 490 may be implemented in a known manner.

[0185] During operation, all six power stages are assigned to Rail A, with switches 462-1 through 462-6 closed. Only SPS-1 is active, with switch 464-1 closed and switches 464-2 through 464-6 open. Current flows through path 213-1, resulting in a corresponding voltage drop across sense resistor Rs1 (463-1). This voltage drop is provided as a differential input to amplifier 470, which generates a corresponding current output, Iout, on path 472. Iout discharges capacitor 475.

[0186] Therefore, during each switching cycle, the "integrator module" (amplifier 470 and capacitor 475) integrates the current signal 213, and the voltage dVcap decreases accordingly due to the discharge of capacitor 475. The magnitude of dVcap is compared with the threshold voltage vcomp-ref. When the comparator trips (triggering the "reset" signal), switch 474 is closed, capacitor 475 is charged (to V-cm), and then integration resumes.

[0187] The duration defined by two consecutive comparator trip events represents the time required for the voltage across capacitor 475 to change to "vqref." The parameters "qref," "vqref," the gm (transconductance) of amplifier 470, the capacitance of capacitor 475, and the resistance of sense resistor 463 are designed so that the voltage "dVcap" reaches the threshold "vcomp-ref" within one or more switching cycles. The number of trips is calculated within a long sampling window (on the order of milliseconds compared to the PWM signal period). The number of trips is proportional to the magnitude of the load current. The greater the number of comparator trips per sampling window, the greater the load current, and vice versa. In addition, the longer the sampling window duration, the more accurate the load current measurement.

[0188] Although, for ease of understanding, this exemplary embodiment only describes the operation of the current measurement module 450 in DCM mode using only one active power stage, several aspects of the present application are equally applicable to the case of multiple active power stages in DCM mode, which will be apparent to those skilled in the art after reading the contents of this application. For example, if there are multiple active power stages in DCM mode, the currents sensed by each active power stage can be summed (via corresponding devices), and the voltage drop across a single sense resistor can be coupled as the differential input of the amplifier 470. Alternatively, each current signal can be passed through a corresponding amplifier, and the output of the amplifier can then be integrated via a corresponding capacitor.

[0189] The following description continues to illustrate the settings of the above-mentioned design parameters.

[0190] 8. Set design parameters

[0191] For convenience, the variables used in the equations governing component selection and design parameters are first listed:

[0192] tsw: duration of a single switching cycle (PWM cycle)

[0193] ton: duration of HS switch conduction within PWM cycle

[0194] toff: duration of LS switch conduction within PWM cycle

[0195] qref: reference change in charge in capacitor 475

[0196] treset: The duration between two consecutive reset events

[0197] tm: sampling window, the storage time is much longer than treset

[0198] vqref: the voltage change across capacitor 475 corresponding to the change in charge qref

[0199] Ics: instantaneous magnitude of current signal CSA-1

[0200] indsw(t): The instantaneous magnitude of the actual inductor current flowing through inductor 225A-1

[0201] dqsw: The amount of charge delivered by SPS-1 in a single switching cycle

[0202] gm: transconductance of amplifier 470

[0203] Vin: input voltage

[0204] Vout: rail voltage (such as Va)

[0205] dvsw: voltage change across capacitor 475 during a single switching cycle

[0206] Rs: resistance of sensing resistor 463-1

[0207] iout: current output of amplifier 470

[0208] *: multiplication sign

[0209] Selection of components and design parameters

[0210] The value of Rs should be chosen so that the voltage drop across Rs caused by current signal 213 matches the input voltage swing range of amplifier 470 while ensuring that the entire inductor current range (e.g., 0-5 A) in DCM mode is covered. Ideally, Rs should be chosen to support the full range of amplifier 470.

[0211] For example, assume the current signal received on path CSA-1 is scaled by a factor of 10⁻¹ (i.e., 10 microamperes per ampere (uA / A)). Therefore, an inductor current of 1A can be represented by a current signal of 10uA. Based on expected parameters such as maximum load current, switching frequency range, and other loss components, Rs can be determined. In one embodiment, Rs is equal to 500Ω.

[0212] Some other component value / setting selection options are described below.

[0213] The charge delivered by the SPS-1 in a single switching cycle is:

[0214]

[0215] Average load current during tm duration =

[0216]

[0217] The voltage change across capacitor 475 during a single switching cycle =

[0218]

[0219] iout(t)=indsw(t)*Ri*gm -----------Formula (4)

[0220] Ri=Kisps*Rs; -----------Formula (5)

[0221] Where Kisps is the SPS current gain in [A / A].

[0222] According to equations (1), (3) and (4):

[0223] dvsw=dqsw*{(Ri*gm) / C}-----------Formula (6)

[0224] According to equations (2) and (6):

[0225] Average load current during tm duration =

[0226]

[0227] It should be understood that due to limited voltage headroom at the circuit level, it may not be possible to accurately measure dvsw during the tm time. Therefore, the integrator is reset periodically and the number of such reset events during the tm time is counted to estimate the average load current.

[0228]

[0229] in

[0230] The values of gm and C can be selected based on a variety of factors, such as the input voltage range of comparator 480, whether capacitor 475 is to be implemented on-chip and, if so, the chip area limitations, and any other practical considerations, such as the duration of the sampling window. In one embodiment, C is equal to 5 pico-Faradays (pF) and gm is equal to 10 micro-Siemens (uS). Any suitable combination of gm and C can be selected based on the specific implementation of current measurement module 450, as will be apparent to those skilled in the art reading this application.

[0231] It should be understood that the integrator module is designed for a specific combination of gm and C magnitudes. Variations in these magnitudes can result in inaccurate load current measurements. Therefore, if the magnitude of gm changes to gm' (e.g., due to PVT variations), the magnitude of C can be appropriately adjusted to C' to keep K essentially constant. This adjustment minimizes errors in load current measurements.

[0232] The magnitude of Vqref is the voltage change across the capacitor 475 caused by the change in the charge qref in the capacitor 475 . vqref is set to the threshold voltage (vcomp-ref, 477 ) of the non-inverting input of the comparator 480 .

[0233] The sizes of "qref", "vcomp-ref", and the sampling window duration are appropriately chosen so that the voltage across the capacitor reaches vqref within a plurality (e.g., about 10) of switching cycles, and the number of comparator trip events in the sampling window is neither too small nor too large. In general, the sizes of "qref", "vcomp-ref", "C", and the sampling window duration are designed to provide a reasonable trade-off between accuracy, the quiescent current consumed by the current measurement block, the area limitations of the chip, and a measurement time suitable for a particular implementation.

[0234] For example, assuming the sampling window duration is 1 millisecond, C = 5 pF, gm = 10 uS, qref = 70 microcoulombs (uC), therefore, according to the above formula, vqref = 0.7V.

[0235] Therefore, a 1A load current releases 70uC of charge within 70us, while a 5A load current releases the same charge (70uC) within 14us. Accordingly, a 1A load current causes approximately 14 comparator trips within a 1ms sampling window, while a 5A load current causes approximately 70 comparator trips within a 1ms sampling window. Therefore, the number of comparator trips is proportional to the load current. In other words, the greater the load current, the steeper the slope of the dVcap waveform over time, the faster dVcap reaches vcomp-ref, and thus the greater the number of comparator trips within the sampling window, and vice versa.

[0236] The following describes a method for measuring the load current using the above design parameters.

[0237] 9. Load current measurement

[0238] Figure 5 1 is a timing diagram (not to scale) used to illustrate example waveforms of some signals and voltages at certain nodes of the phase controller in an embodiment of the present application. Figure 5Example waveforms are depicted for signal CSA-1 (213-1), load current (I-load), voltage dVcap (478) at the inverting input of comparator 480, reset signal (483), counter value, inductor current (290-1), terminal count signal (487), and time interval (tik) signal. The "counter value" signal and "time interval" signal are generated internally by counter 485. The "counter value" signal represents the instantaneous value of the counter and is used to count the number of times the "reset" signal is triggered. The triggering of the "time interval" signal is synchronized with the end of the above-mentioned sampling window duration. I-load (with a magnitude of IL-avg) represents the load current at node Va.

[0239] SPS-1 is the only active power stage, operating in DCM mode in steady state. The figure shows the corresponding inductor current IL (290-1) and current signal (CSA-1). The peak value of the inductor current is IL-peak, and the peak value of the current signal is CS-peak. V-cm is 1.7V, and vcomp-ref is 1V.

[0240] Before time t510, assume that the counter value is 26. At time t510, voltage dVcap falls below comparator threshold voltage vcomp-ref. Consequently, comparator 480 trips and triggers signal 483. When signal 483 triggers, switch 474 closes, thereby charging capacitor 475. Therefore, at time t510, dVcap is reset to V-cm.

[0241] Furthermore, when the signal 483 is triggered, the counter 485 increases the count value by 1. Therefore, the counter value is shown to increase from 26 to 27 at t510.

[0242] During the time interval t510-t514, current signal 213 continues to integrate, causing capacitor 475 to discharge. Because the voltage at the inverting input of amplifier 470 (V1) is higher than the voltage at the non-inverting input (V2), voltage dVcap decreases during each PWM cycle by an amount corresponding to the amount of charge transferred during that cycle. In alternative embodiments, the inputs of amplifier 470 can be interchanged, and the comparator inputs can be adjusted accordingly, as would be apparent to one skilled in the art after reading this disclosure. The magnitude of dVcap decreases during each PWM cycle, falling below vcomp-ref at t514.

[0243] At t514, signal 483 triggers, switch 474 closes, capacitor 475 charges to V-cm, and the counter value increments to 28, continuing to integrate. Therefore, during the period defined by two consecutive comparator trigger events (t510-t514 in the figure), the voltage change across the capacitor is equal to vqref (here, 0.7V), corresponding to the reference charge qref (here, 70uC).

[0244] At t518, counter 485 issues an "interval" signal, synchronized with the end of the sampling window (here, assumed to be 1 millisecond). When the "interval" signal is triggered, the current counter value (here, 28) is output on the terminal count path. It is important to note that the end of the sampling window may or may not coincide with the triggering of the reset signal. In other words, the duration of the sampling window may not be an integer multiple of the duration of the reset event. However, this error is negligible for determining the load current.

[0245] Mapping module 490 determines the mapping of the count 28 to the corresponding T-ON duration based on the LUT and provides the T-ON duration on path 453. As described above, approximately 14 transitions correspond to a load current of 1 A. Therefore, 28 transitions correspond to a load current of 2 A.

[0246] An exemplary implementation of a portion of a transconductance amplifier in an embodiment of the present application is provided below.

[0247] 10. Transconductance amplifier

[0248] Figure 6 4 is a schematic diagram illustrating implementation details of a differential gain stage of a transconductance amplifier in an embodiment of the present application. Transconductance amplifier 470 includes NMOS transistors 630 and 640, resistors 635 and 645 (each with a resistance value of R'), and a current source 650. Transistors 630 and 640 receive voltages V2 (467) and V1 (466) at their gate terminals, respectively.

[0249] In one embodiment, resistors Rs (463) and R' (645) are matched (e.g., when the current measurement module is implemented as part of a phase controller IC, Rs and R' will be on the same chip) so that Rs and R' track each other. As a result, the PVT (process voltage temperature) variation of the gain ("gm*Rs") of amplifier 470 is very small, thereby minimizing errors in the load current measurement.

[0250] Therefore, several aspects of the present application are directed to measuring load current under light load conditions.

[0251] 11. Conclusion

[0252] References in this specification to "one embodiment," "an embodiment," or similar expressions mean that a particular feature, structure, or characteristic associated with that embodiment is included in at least one embodiment disclosed herein. Therefore, the phrases "in one embodiment," "in an embodiment," and similar expressions throughout this specification may (but do not necessarily) all refer to the same embodiment.

[0253] Although Figure 1 、 2 , 3A, 4A, 4B and 6 show terminals / nodes being directly connected to various other terminals (i.e., "connected to"), but it should be understood that other elements may also be present in the path (as appropriate to the particular environment), so the connections may be viewed as being "electrically coupled" to the same connection terminal.

[0254] It should be understood that the specific types of transistors described above (e.g., NMOS, PMOS, etc.) are for illustration only. However, alternative embodiments using transistors of different configurations and having similar characteristics will be readily apparent to those skilled in the art upon reviewing the disclosure provided herein. For example, an NMOS transistor can be replaced with a PMOS (P-channel MOS) transistor, with the connections to the power supply and ground terminals interchanged.

[0255] Therefore, in this application, the power supply and ground terminals are referred to as constant reference potentials, the source (emitter) and drain (collector) of the transistor (providing a current path when turned on and an open circuit when turned off) are referred to as current terminals, and the gate (base) terminal is referred to as the control terminal.

[0256] Although various embodiments of the present disclosure have been described above, it should be understood that these embodiments are presented by way of example only and not limitation. Therefore, the breadth and scope of the present disclosure should not be limited by any of the above embodiments, but should be defined according to the following claims and their equivalents.

Claims

1. A multiphase switching converter for providing a regulated supply voltage based on an input voltage under light load conditions, characterized in that: The multi-phase switching converter comprises: a power stage coupled to receive a phase control signal and drive an inductor to generate an inductor current according to the phase control signal, wherein a load current of the multi-phase switching converter is formed by the inductor current; and a phase controller coupled to receive a current signal from the power stage, the current signal representing an inductor current in the power stage in analog continuous form, the phase controller being configured to: integrating the current signal in analog continuous form to generate a voltage output representing the magnitude of the load current; and The magnitude of the load current is determined according to the voltage output.

2. The multi-phase switching converter according to claim 1, wherein: The phase controller comprises: a pin receiving the current signal from the power stage; a main control signal generator module coupled to receive the regulated power supply voltage, the first reference voltage of the expected magnitude, and the magnitude of the on-time of the phase controller, and to generate a common control signal having corresponding characteristics; a phase distributor coupled to receive the common control signal and generate the phase control signal based on a transition of the common control signal; and a current measurement module coupled to receive the current signal and determine the magnitude of the load current, wherein the current measurement module comprises: an integrator module coupled to receive the current signal and provide the voltage output; and A processing module is coupled to receive the voltage output, determine the magnitude of the on-time based on the magnitude of the voltage output, and provide the magnitude of the on-time to the main control signal generator block.

3. The multi-phase switching converter according to claim 2, wherein: The current measurement module includes a first resistor coupled between the pin and the integrator block, Wherein, the integrator block includes: a transconductance amplifier characterized by a transconductance value (gm), the transconductance amplifier coupled to receive a voltage drop across the first resistor as a differential input and to generate an output current from an output node proportional to a magnitude of the voltage drop caused by the current signal flowing through the first resistor; and a capacitor having a first end and a second end, wherein the first end of the capacitor is coupled to the output node and the second end of the capacitor is coupled to a constant reference potential, the capacitor being characterized by a capacitance value, the capacitor being coupled to receive the output current of the transconductance amplifier and to provide the voltage output at the first end; Wherein, the processing block includes: a comparator, configured to compare a voltage at a first terminal of the capacitor with a threshold voltage, wherein when the voltage at the first terminal is lower than the threshold voltage, the comparator triggers a reset signal; a counter coupled to receive the reset signal and to generate a count of the number of times the reset signal is triggered within a sampling window; and a mapping module coupled to receive the count and map the count to a corresponding magnitude of the on-time; wherein the threshold voltage is proportional to a predetermined amount of change in the amount of charge in the capacitor, The duration of the sampling window is selected to be greater than the time required for the voltage at the first end of the capacitor to change by the threshold voltage.

4. The multi-phase switching converter according to claim 3, wherein: The current signal is proportional to the inductor current, and the inductor current is scaled by a scaling factor to obtain the current signal.

5. The multi-phase switching converter according to claim 4, wherein: The mapping module includes a lookup table having a plurality of entries to perform the mapping, wherein each entry of the plurality of entries includes a range of the count and a corresponding magnitude of the on-time.

6. The multi-phase switching converter according to claim 4, wherein: The integrator module also includes a switch coupled across the capacitor, the switch being operable to close when the reset signal is triggered, a first end of the switch being coupled to the output node, and a second end of the switch being coupled to a second reference voltage; wherein, when the switch is closed, the voltage across the capacitor is equal to the second reference voltage.

7. The multi-phase switching converter according to claim 5, wherein: The capacitance of the capacitor can be adjusted to offset any changes in the magnitude of gm.

8. The multi-phase switching converter according to claim 7, wherein: The transconductance amplifier includes a differential gain stage, the differential gain stage including: a first transistor; a second transistor; a second resistor having a second resistance value; a third resistor having a third resistance value; and current source, The control terminal of the first transistor is coupled to the first terminal of the first resistor, the control terminal of the first transistor forms the non-inverting input terminal of the transconductance amplifier, the current terminal of the first transistor is coupled to the first terminal of the second resistor, the second terminal of the second resistor is coupled to the first terminal of the current source, and the second terminal of the current source is coupled to the constant reference potential; wherein the control terminal of the second transistor is coupled to the second terminal of the first resistor, the control terminal of the second transistor forms the inverting input terminal of the transconductance amplifier, the current terminal of the second transistor is coupled to the first terminal of the third resistor, and the second terminal of the third resistor is coupled to the connection point between the second terminal of the second resistor and the first terminal of the current source; Wherein, the second resistance value is equal to the third resistance value; The second resistor and the third resistor are matched with the first resistor.

9. The multi-phase switching converter according to claim 8, wherein: The current measurement module further includes: a calibration module operable to correct an offset error of the transconductance amplifier; and a first switch coupled between the second end of the first resistor and the calibration module, the first switch being operable to close when the main-level signal is in a first logic state and to open when the main-level signal is in a second logic state; The calibration module is coupled between the first switch and the inverting input terminal of the transconductance amplifier. The first end of the first resistor is coupled to the non-inverting input end of the transconductance amplifier.

10. A phase controller for a multiphase switching converter, wherein the multiphase switching converter provides a regulated power supply voltage based on an input voltage under light load conditions, the phase controller providing a phase control signal to a power stage of the multiphase switching converter, characterized in that: The power stage is configured to connect the input voltage to the inductor when the phase control signal is in a first state, and disconnect the input voltage from the inductor when the corresponding phase control signal is in a second state; wherein a load current of the multi-phase switching converter is formed by an inductor current, and the phase controller includes: Current sense pin, a main control signal generator module coupled to receive the regulated supply voltage, the first reference voltage of the desired magnitude, and the on-time duration, and to generate a common control signal having corresponding characteristics, a phase distributor coupled to receive the common control signal and generate the phase control signal based on a transition of the common control signal; and a current measurement module coupled to receive a current signal from the power stage through a current sense pin, the current signal representing an inductor current in the power stage in analog continuous form, wherein the current measurement module comprises: an integrator module coupled to receive the current signal and provide the voltage output; and A processing module is coupled to receive the voltage output and determines a magnitude of the load current based on the voltage output.

11. The phase controller according to claim 10, wherein: The current measurement module includes a first resistor coupled between the current sensing pin and the integrator module, wherein the integrator block includes: a transconductance amplifier characterized by a transconductance value (gm), the transconductance amplifier coupled to receive a voltage drop across the first resistor as a differential input and to generate an output current from an output node proportional to a magnitude of the voltage drop caused by the current signal flowing through the first resistor; and a capacitor having a first end and a second end, wherein the first end of the capacitor is coupled to the output node and the second end of the capacitor is coupled to a constant reference potential, the capacitor being characterized by a capacitance value, the capacitor being coupled to receive the output current of the transconductance amplifier and to provide the voltage output at the first end; Wherein, the processing block includes: a comparator, configured to compare a voltage at a first terminal of the capacitor with a threshold voltage, wherein when the voltage at the first terminal is lower than the threshold voltage, the comparator triggers a reset signal; a counter coupled to receive the reset signal and to generate a count of the number of times the reset signal is triggered within a sampling window; and a mapping module coupled to receive the count and map the count to a corresponding magnitude of the on-time; wherein the threshold voltage is proportional to a predetermined amount of change in the amount of charge in the capacitor, The duration of the sampling window is selected to be greater than the time required for the voltage at the first end of the capacitor to change by the threshold voltage.

12. The phase controller according to claim 11, wherein: The current signal is proportional to the inductor current, and the inductor current is scaled by a scaling factor to obtain the current signal.

13. The phase controller according to claim 12, wherein: The mapping module includes a lookup table having a plurality of entries to perform the mapping, wherein each entry of the plurality of entries includes a range of the count and a corresponding magnitude of the on-time.

14. The phase controller according to claim 12, wherein: The integrator module also includes a switch coupled across the capacitor, the switch being operable to close when the reset signal is triggered, a first end of the switch being coupled to the output node, and a second end of the switch being coupled to a second reference voltage; wherein, when the switch is closed, the voltage across the capacitor is equal to the second reference voltage.

15. The phase controller according to claim 13, wherein: The capacitance of the capacitor can be adjusted to offset any changes in the magnitude of gm.

16. The phase controller according to claim 15, wherein: The transconductance amplifier includes a differential gain stage, the differential gain stage including: a first transistor; a second transistor; a second resistor having a second resistance value; a third resistor having a third resistance value; and current source, The control terminal of the first transistor is coupled to the first terminal of the first resistor, the control terminal of the first transistor forms the non-inverting input terminal of the transconductance amplifier, the current terminal of the first transistor is coupled to the first terminal of the second resistor, the second terminal of the second resistor is coupled to the first terminal of the current source, and the second terminal of the current source is coupled to the constant reference potential; wherein the control terminal of the second transistor is coupled to the second terminal of the first resistor, the control terminal of the second transistor forms the inverting input terminal of the transconductance amplifier, the current terminal of the second transistor is coupled to the first terminal of the third resistor, and the second terminal of the third resistor is coupled to the connection point between the second terminal of the second resistor and the first terminal of the current source; Wherein, the second resistance value is equal to the third resistance value; The second resistor and the third resistor are matched with the first resistor.

17. The phase controller according to claim 16, wherein: The current measurement module further includes: a calibration module operable to correct an offset error of the transconductance amplifier; and a first switch coupled between the second end of the first resistor and the calibration module, the first switch being operable to close when the main-level signal is in a first logic state and to open when the main-level signal is in a second logic state; The calibration module is coupled between the first switch and the inverting input terminal of the transconductance amplifier. The first end of the first resistor is coupled to the non-inverting input end of the transconductance amplifier.

18. A method for a phase controller of a multiphase switching converter that provides a regulated supply voltage based on an input voltage under light load conditions, characterized in that: The method comprises: receiving a current signal in an analog continuous form representing an inductor current in a power stage of the multi-phase switching converter, wherein a load current of the multi-phase switching converter is formed by the inductor current; integrating the current signal to generate a voltage output corresponding to the magnitude of the current signal; and The magnitude of the load current is determined according to the voltage output.

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